FDN357N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
Features
General Description
SuperSOTTM-3 N-Channel logic level enhancement mode power field
effect transistors are produced using ON Semiconductor's proprietary, high
cell density, DMOS technology. This very high density process is especially
tailored to minimize on-state resistance. These devices are particularly
suited for low voltage applications in notebook computers, portable phones,
PCMCIA cards, and other battery powered circuits where fast switching,
and low in-line power loss are needed in a very small outline surface mount
package
SuperSOTTM-8
SuperSOTTM-6
SOT-23
1.9 A, 30 V, RDS(ON) = 0.090 Ω @ VGS = 4.5 V
RDS(ON) = 0.060 Ω @ VGS = 10 V.
Industry standard outline SOT-23 surface mount
package using proprietary SuperSOTTM-3 design for
superior thermal and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
SO-8
SOIC-16
SOT-223
D
D
7
35
S
G
TM
SuperSOT -3
Absolute Maximum Ratings
S
G
TA = 25oC unless other wise noted
Symbol
Parameter
FDN357N
Units
VDSS
Drain-Source Voltage
30
V
VGSS
Gate-Source Voltage - Continuous
±20
V
ID
Drain/Output Current - Continuous
1.9
A
- Pulsed
PD
TJ,TSTG
Maximum Power Dissipation
10
(Note 1a)
0.5
(Note 1b)
0.46
Operating and Storage Temperature Range
-55 to 150
W
°C
THERMAL CHARACTERISTICS
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
250
°C/W
RθJC
Thermal Resistance, Junction-to-Case
(Note 1)
75
°C/W
© 1998 Semiconductor Components Industries, LLC.
October-2017, Rev. 3
Publication Order Number:
FDN357N /D
Electrical Characteristics (TA = 25 OC unless otherwise noted )
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = 250 µA
∆BVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
ID = 250 µA, Referenced to 25 oC
30
V
IDSS
Zero Gate Voltage Drain Current
VDS = 24 V, VGS = 0 V
IGSSF
Gate - Body Leakage, Forward
VGS = 20 V,VDS = 0 V
IGSSR
Gate - Body Leakage, Reverse
VGS = -20 V, VDS = 0 V
-100
nA
TJ = 55°C
ON CHARACTERISTICS
mV/ oC
36
1
µA
10
µA
100
nA
(Note)
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
∆VGS(th)/∆TJ
Gate Threshold Voltage Temp. Coefficient
ID = 250 µA, Referenced to 25 oC
1
RDS(ON)
Static Drain-Source On-Resistance
VGS = 4.5 V, ID = 1.9 A
TJ =125°C
VGS = 10 V, ID = 2.2 A
ID(ON)
On-State Drain Current
VGS = 4.5 V, VDS = 5 V
gFS
Forward Transconductance
VDS = 5 V, ID = 1.9 A
1.6
2
V
mV/ oC
-3.6
0.081
0.09
0.11
0.14
0.053
0.06
5
Ω
A
5
S
235
pF
145
pF
50
pF
DYNAMIC CHARACTERISTICS
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS
tD(on)
Turn - On Delay Time
tr
Turn - On Rise Time
tD(off)
Turn - Off Delay Time
tf
Turn - Off Fall Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
VDS = 10 V, VGS = 0 V,
f = 1.0 MHz
(Note)
VDD = 10 V, ID = 1 A,
VGS = 10 V, RGEN = 6 Ω
VDS = 10 V, ID = 1.9 A,
VGS = 5 V
5
10
ns
12
22
ns
12
22
ns
3
8
ns
4.2
5.9
nC
1.3
nC
1.7
nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
IS
Maximum Continuous Drain-Source Diode Forward Current
VSD
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = 0.42 A
(Note)
0.71
0.42
A
1.2
V
Note:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by
design while RθCA is determined by the user's board design.
Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment :
a. 250oC/W when mounted on
a 0.02 in2 pad of 2oz Cu.
b. 270oC/W when mounted on
a 0.001 in2 pad of 2oz Cu.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
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2
Typical Electrical Characteristics
VGS = 10V
1.8
5.0
4.5
6.0
RDS(ON) , NORMALIZED
4.0
8
6
3.5
4
3.0
2
0
0
0.5
1
1.5
2
2.5
DRAIN-SOURCE ON-RESISTANCE
I D , DRAIN-SOURCE CURRENT (A)
10
1.6
4.0
1.2
4.5
1
5.0
6.0
0.8
7.0
0
2
VDS , DRAIN-SOURCE VOLTAGE (V)
VGS = 4.5V
1.2
1
0.8
0
25
50
75
100
T , JUNCTION TEMPERATURE (°C)
125
150
RDS(ON) , DRAIN-SOURCE ON-RESISTANCE
R DS(ON) , NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
I D = 1.9A
-25
I D =0.95A
0.2
0.15
0.1
TA = 125°C
TA = 25°C
0.05
0
2
4
I D , DRAIN CURRENT (A)
8
6
4
2
1
2
3
8
10
10
25°C
125°C
10
0
6
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
I S , REVERSE DRAIN CURRENT (A)
TA = -55°C
VDS = 10V
10
V GS ,GATE TO SOURCE VOLTAGE (V)
Figure 3. On-Resistance Variation
with Temperature.
12
8
0.25
J
14
6
Figure 2. On-Resistance Variation with
Drain Current and Gate
1.6
0.6
-50
4
I D , DRAIN CURRENT (A)
Figure 1. On-Region Characteristics.
1.4
10
0.6
0.4
3
V GS =3.5V
1.4
4
5
6
VGS = 0V
1
TJ = 125°C
0.1
25°C
-55°C
0.01
0.001
0.0001
VGS , GATE TO SOURCE VOLTAGE (V)
0
0.2
0.4
0.6
0.8
1
1.2
VSD , BODY DIODE FORWARD VOLTAGE (V)
Figure 6. Body Diode Forward Voltage
Variation with Source Current
and Temperature.
Figure 5. Transfer Characteristics.
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Typical Electrical And Thermal Characteristics
600
I D = 1.9A
VDS = 5V
10V
15V
8
300
CAPACITANCE (pF)
V GS , GATE-SOURCE VOLTAGE (V)
10
6
4
Coss
100
50
f = 1 MHz
V GS = 0 V
2
0
Ciss
200
20
0.1
0
2
4
6
0.2
8
Crss
0.5
1
2
5
10
30
VDS , DRAIN TO SOURCE VOLTAGE (V)
Q g , GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics.
Figure 8. Capacitance Characteristics.
50
20
IT
LIM
N)
(O
S
RD
1m
s
10m
100
1
0.5
ms
1s
10s
0.1
0.01
0.1
0.2
0.5
30
20
DC
V GS = 10V
SINGLE PULSE
R θJA= 250°C/W
T
A A = 25°C
0.05
SINGLE PULSE
R θJA =250° C/W
TA = 25°C
40
s
POWER (W)
5
10
0
0.0001
1
2
5
10
20
0.001
50
0.01
0.1
1
10
100 300
SINGLE PULSE TIME (SEC)
V DS , DRAIN-SOURCE VOLTAGE (V)
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum Power
Dissipation.
1
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
I D , DRAIN CURRENT (A)
10
0.5
D = 0.5
0.2
0.1
0.05
0.02
0.01
R θJA (t) = r(t) * RθJA
R θJA = 250 °C/W
0.2
0.1
0.05
P(pk)
0.02
0.01
t1
Single Pulse
Duty Cycle, D = t1 /t2
0.002
0.001
0.0001
t2
TJ - TA = P * RθJA (t)
0.005
0.001
0.01
0.1
1
10
t1 , TIME (sec)
Figure 11. Transient Thermal Response Curve.
Note: Thermal characterization performed using the conditions described in note 1a.
Transient thermal response will change depending on the circuit board design.
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100
300
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