FDN360P
FDN360P
Single P-Channel, PowerTrench MOSFET
Features
General Description
• –2 A, –30 V.
This
P-Channel
Logic
Level
MOSFET
is
produced using ON Semiconductor advanced Power
Trench process that has been especially tailored to
minimize the on-state resistance and yet maintain
low gate charge for superior switching performance.
RDS(ON) = 80 mΩ @ VGS = –10 V
RDS(ON) = 125 mΩ @ VGS = –4.5 V
• Low gate charge (6.2 nC typical)
• High performance trench technology for extremely
low RDS(ON) .
These devices are well suited for low voltage and
battery powered applications where low in-line power
loss and fast switching are required.
• High power version of industry Standard SOT-23
package. Identical pin-out to SOT-23 with 30%
higher power handling capability.
• These Devices are Pb-Free and are RoHS Compliant
D
D
S
G
TM
SuperSOT -3
Absolute Maximum Ratings
Symbol
S
G
TA=25oC unless otherwise noted
Ratings
Units
VDSS
Drain-Source Voltage
Parameter
–30
V
VGSS
Gate-Source Voltage
±20
V
ID
Drain Current
–2
A
PD
Power Dissipation for Single Operation
– Continuous
(Note 1a)
– Pulsed
TJ, TSTG
–10
(Note 1a)
0.5
(Note 1b)
0.46
W
–55 to +150
°C
(Note 1a)
250
°C/W
(Note 1)
75
°C/W
Operating and Storage Junction Temperature Range
Thermal Characteristics
RθJA
Thermal Resistance, Junction-to-Ambient
RθJC
Thermal Resistance, Junction-to-Case
Package Marking and Ordering Information
Device Marking
Device
Reel Size
Tape width
Quantity
360
FDN360P
7’’
8mm
3000 units
2003 Semiconductor Components Industries, LLC.
November-2018, Rev. 7
Publication Order Number:
FDN360P /D
Symbol
Parameter
TA = 25°C unless otherwise noted
Test Conditions
Min
Typ
Max Units
Off Characteristics
VGS = 0 V, ID = –250 µA
BVDSS
∆BVDSS
∆TJ
Drain–Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
IDSS
Zero Gate Voltage Drain Current
IGSSF
Gate–Body Leakage, Forward
VGS = 20 V,
VDS = 0 V
100
nA
IGSSR
Gate–Body Leakage, Reverse
VGS = –20 V,
VDS = 0 V
–100
nA
–3
V
On Characteristics
–30
ID = –250 µA, Referenced to 25°C
VDS = –24V,
V
–22
VGS = 0 V
mV/°C
–1
µA
–10
VDS = –24V, VGS = 0 V, TJ=55°C
(Note 2)
VGS(th)
∆VGS(th)
∆TJ
RDS(on)
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
VDS = VGS, ID = –250 µA
ID = –250 µA, Referenced to 25°C
ID(on)
On–State Drain Current
VGS = –10 V,
VDS = –5 V
gFS
Forward Transconductance
VDS = –5 V,
ID = –2 A
5
S
VDS = –15 V,
f = 1.0 MHz
V GS = 0 V,
298
pF
83
pF
39
pF
–1
–1.9
4
VGS = –10 V,
ID = –2 A
VGS = –10 V, ID = –2 A, TJ=125°C
VGS= –4.5 V,
ID = –1.5A
63
90
100
mV/°C
80
136
125
–10
mΩ
A
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Switching Characteristics
td(on)
Turn–On Delay Time
tr
Turn–On Rise Time
td(off)
tf
Qg
Total Gate Charge
(Note 2)
6
12
ns
13
23
ns
Turn–Off Delay Time
11
20
ns
Turn–Off Fall Time
6
12
ns
6.2
9
nC
Qgs
Gate–Source Charge
Qgd
Gate–Drain Charge
VDD = –15 V,
VGS = –10 V,
VDS = –15V,
VGS = –10 V
ID = –1 A,
RGEN = 6 Ω
ID = –3.6 A,
1
nC
1.2
nC
Drain–Source Diode Characteristics and Maximum Ratings
IS
VSD
Maximum Continuous Drain–Source Diode Forward Current
Drain–Source Diode Forward
VGS = 0 V, IS = –0.42 A
Voltage
(Note 2)
–0.8
–0.42
A
–1.2
V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.
a) 250°C/W when mounted on a
0.02 in2 pad of 2 oz. copper.
b) 270°C/W when mounted on a
minimum pad.
Scale 1 : 1 on letter size paper
2.
Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
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2
FDN360P
Electrical Characteristics
FDN360P
Typical Characteristics
15
2
-6.0V
-5.0V
V
RDS(ON), NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
-ID, DRAIN CURRENT (A)
VGS = -10V
-4.5V
12
9
-4.0V
6
-3.5V
3
-3.0V
1.8
VGS = -3.5V
1.6
1.4
-4.0V
1.2
-4.5V
1
-5.0V
-6.0V
0.8
-7.0V
-10V
0.6
0
0
1
2
3
4
0.4
5
0
-VDS, DRAIN TO SOURCE VOLTAGE (V)
3
6
9
12
15
-ID, DRAIN CURRENT (A)
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.3
ID = -2A
VGS = -10V
RDS(ON), ON-RESISTANCE (OHM)
RDS(ON), NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
1.6
1.4
1.2
1
0.8
0.6
ID = -1A
0.25
0.2
TA = 125oC
0.15
0.1
TA = 25oC
0.05
-50
-25
0
25
50
75
100
125
150
2
4
TJ, JUNCTION TEMPERATURE (oC)
Figure 3. On-Resistance Variation with
Temperature.
8
10
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
10
10
-IS, REVERSE DRAIN CURRENT (A)
25oC
TA = -55oC
VDS = -5.0V
-ID, DRAIN CURRENT (A)
6
-VGS, GATE TO SOURCE VOLTAGE (V)
8
125oC
6
4
2
0
VGS = 0V
1
TA = 125oC
0.1
25oC
-55oC
0.01
0.001
0.0001
1
2
3
4
5
0
-VGS, GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics.
0.2
0.4
0.6
0.8
1
1.2
-VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
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3
FDN360P
Typical Characteristics
400
VDS = -5V
ID = -3.6A
f = 1 MHz
VGS = 0 V
-10V
CISS
8
-15V
CAPACITANCE (pF)
-VGS, GATE-SOURCE VOLTAGE (V)
10
6
4
2
300
200
COSS
100
CRSS
0
0
0
1
2
3
4
5
6
7
0
6
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics.
24
20
P(pk), PEAK TRANSIENT POWER (W)
RDS(ON) LIMIT
10µs
10
100µs
1ms
10ms
100ms
1s
1
VGS = -10V
SINGLE PULSE
RθJA =270oC/W
0.1
DC
TA = 25oC
0.1
1
30
10
SINGLE PULSE
RθJA = 270°C/W
TA = 25°C
15
10
5
0
0.001
0.01
100
0.01
0.1
1
-VDS, DRAIN-SOURCE VOLTAGE (V)
10
100
1000
t1, TIME (sec)
Figure 9. Maximum Safe Operating Area.
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
18
Figure 8. Capacitance Characteristics.
100
-ID, DRAIN CURRENT (A)
12
-VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 10. Single Pulse Maximum
Power Dissipation.
1
D = 0.5
RθJA(t) = r(t) + RθJA
RθJA = 270 °C/W
0.2
0.1
0.1
0.05
P(pk)
0.02
0.01
t1
0.01
t2
TJ - TA = P * RθJA(t)
Duty Cycle, D = t1 / t2
SINGLE PULSE
0.001
0.0001
0.001
0.01
0.1
1
10
t1, TIME (sec)
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b.
Transient thermal response will change depending on the circuit board design.
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4
100
1000
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−23, 3 Lead
CASE 527AG−01
ISSUE O
D
DATE 19 DEC 2008
SYMBOL
MIN
A
0.89
1.12
A1
0.013
0.10
b
0.37
0.50
c
0.085
0.18
D
2.80
3.04
E
2.10
2.64
E1
1.20
3
E1
E
NOM
MAX
1.40
e
0.95 BSC
e1
1.90 BSC
L
0.40 REF
e1
L1
0.54 REF
TOP VIEW
θ
1
2
e
A
0º
8º
q
b
L1
A1
SIDE VIEW
L
c
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC TO-236.
DOCUMENT NUMBER:
STATUS:
98AON34319E
ON SEMICONDUCTOR STANDARD
REFERENCE:
© Semiconductor Components Industries, LLC, 2002
October, DESCRIPTION:
2002 − Rev. 0
SOT−23, 3 LEAD
http://onsemi.com
1
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
Case Outline Number:
PAGE 1 OFXXX
2
DOCUMENT NUMBER:
98AON34319E
PAGE 2 OF 2
ISSUE
O
REVISION
RELEASED FOR PRODUCTION FROM POD #SOT233−007−01 TO ON
SEMICONDUCTOR. REQ. BY B. BERGMAN.
DATE
19 DEC 2008
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© Semiconductor Components Industries, LLC, 2008
December, 2008 − Rev. 01O
Case Outline Number:
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