DATA SHEET
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MOSFET – N-Channel,
POWERTRENCH)
VDSS
RDS(ON) MAX
ID MAX
150 V
7.5 mW @ 10 V
130 A
*Package limitation current is 120 A.
150 V, 130 A, 7.5 mW
FDP075N15A, FDB075N15A
TO−220
CASE 221A−09
Description
This N−Channel MOSFET is produced using onsemi advanced
POWERTRENCH process that has been tailored to minimize the
on−state resistance while maintaining superior switching
performance.
G
D
S
D
Features
•
•
•
•
•
•
RDS(on) = 6.25 mW (Typ.) @ VGS = 10 V, ID = 100 A
Fast Switching
Low Gate Charge
High Performance Trench Technology for Extremely Low RDS(on)
High Power and Current Handling Capability
RoHS Compliant
G
D2PAK−3 (TO−263, 3−LEAD)
CASE 418AJ
S
MARKING DIAGRAM
Applications
•
•
•
•
Synchronous Rectification for ATX / Server / Telecom PSU
Battery Protection Circuit
Motor Drives and Uninterruptible Power Supplies
Micro Solar Inverter
$Y&Z&3&K
FDB
075N15A
$Y&Z&3&K
FDP
075N15A
$Y
FDP075N15A
FDB075N15A
&Z
&3
&K
= onsemi logo
= Device Code
= Assembly Plant Code
= 3−Digit Date Code Format
= 2−Digits Lot Run Traceability Code
D
G
S
N−Channel
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
© Semiconductor Components Industries, LLC, 2017
September, 2021 − Rev. 3
1
Publication Order Number:
FDP075N15A/D
FDP075N15A, FDB075N15A
MOSFET MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
Parameter
VDSS
Drain to Source Voltage
VGSS
Gate to Source Voltage
ID
− DC
Drain Current
FDP075N15A−F102
FDB075N15A
Unit
150
V
±20
V
− AC (f > 1 Hz)
±30
− Continuous (TC = 25°C)
130*
− Continuous (TC = 100°C)
92
− Pulsed (Note 1)
522
A
A
IDM
Drain Current
EAS
Single Pulsed Avalanche Energy (Note 2)
588
mJ
dv/dt
Peak Diode Recovery dv/dt (Note 3)
6.0
V/ns
333
W
PD
Power Dissipation
(TC = 25°C)
− Derate Above 25°C
TJ, TSTG
TL
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering, 1/8” from Case for 5 Seconds
2.22
W/°C
−55 to +175
°C
300
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
*Package limitation current is 120 A.
1. Repetitive rating: pulse−width limited by maximum junction temperature.
2. Starting TJ = 25°C, L = 3 mH, IAS = 19.8 A.
3. ISD ≤ 100 A, di/dt ≤ 200 A/ms, VDD ≤ BVDSS, starting TJ = 25°C.
THERMAL CHARACTERISTICS
Symbol
Parameter
FDP075N15A−F102
FDB075N15A
Unit
°C/W
RqJC
Thermal Resistance, Junction to Case, Max.
0.45
RqJA
Thermal Resistance, Junction to Ambient (Minimum Pad of 2−oz Copper), Max.
62.5
Thermal Resistance, Junction to Ambient, D2−PAK (1 in2 Pad of 2−oz Copper), Max.
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2
40
FDP075N15A, FDB075N15A
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
150
−
−
V
OFF CHARACTERISTICS
Drain to Source Breakdown Voltage
ID = 250 mA, VGS = 0 V
DBVDSS /
DTJ
Breakdown Voltage Temperature
Coefficient
ID = 250 mA, Referenced to 25°C
−
0.1
−
V/°C
IDSS
Zero Gate Voltage Drain Current
VDS = 120 V, VGS = 0 V
−
−
1
mA
VDS = 120 V, TC = 150°C
−
−
500
VGS = ±20 V, VDS = 0 V
−
−
±100
BVDSS
IGSS
Gate to Body Leakage Current
nA
ON CHARACTERISTICS
VGS(th)
Gate Threshold Voltage
VGS = VDS, ID = 250 mA
2.0
−
4.0
V
RDS(on)
Static Drain to Source On Resistance
VGS = 10 V, ID = 100 A
−
6.25
7.5
mW
Forward Transconductance
VDS = 10 V, ID = 100 A
−
164
−
S
VDS = 75 V, VGS = 0 V, f = 1 MHz
−
5525
7350
pF
−
516
685
pF
gFS
DYNAMIC CHARACTERISTICS
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
−
21
−
pF
Coss(er)
Energy Related Output Capacitance
VDS = 75 V, VGS = 0 V
−
909
−
pF
Qg(tot)
Total Gate Charge at 10 V
VDS = 75 V, ID = 100 A, VGS = 10 V
(Note 4)
−
77
100
nC
−
26
−
nC
Qgs
Gate to Source Gate Charge
Qgs2
Gate Charge Threshold to Plateau
−
11
−
nC
Qgd
Gate to Drain “Miller” Charge
−
16
−
nC
ESR
Equivalent Series Resistance (G−S)
f = 1 MHz
−
2.29
−
W
VDD = 75 V, ID = 100 A, VGS = 10 V,
RG = 4.7 W
(Note 4)
−
28
66
ns
−
37
84
ns
SWITCHING CHARACTERISTICS
td(on)
Turn−On Delay Time
tr
Turn−On Rise Time
td(off)
Turn−Off Delay Time
−
62
134
ns
Turn−Off Fall Time
−
21
52
ns
tf
DRAIN−SOURCE DIODE CHARACTERISTICS
Maximum Continuous Drain to Source Diode Forward Current
−
−
130*
A
ISM
Maximum Pulsed Drain to Source Diode Forward Current
−
−
520
A
VSD
Drain to Source Diode Forward Voltage
VGS = 0 V, ISD = 100 A
−
−
1.25
V
trr
Reverse Recovery Time
−
97
−
ns
Qrr
Reverse Recovery Charge
VGS = 0 V, VDD = 75 V, ISD = 100 A,
dIF/dt = 100 A/ms
−
264
−
nC
IS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Essentially independent of operating temperature typical characteristics.
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3
FDP075N15A, FDB075N15A
TYPICAL PERFORMANCE CHARACTERISTICS
400
VGS =15.0 V
10.0 V
8.0 V
7.0 V
6.5 V
100
6.0 V
5.5 V
5.0 V
ID, Drain Current (A)
ID, Drain Current (A)
400
*Notes:
1. 250 ms Pulse Test
2. TC = 25°C
10
7
0.1
1
100
175°C
25°C
VDS, Drain−Source Voltage (V)
IS, Reverse Drain Current (A)
RDS(ON), Drain−Source On−Resistance (mW)
5
6
400
8
VGS = 10 V
VGS = 20 V
6
*Note: TC = 25°C
100
200
300
100
175°C
25°C
10
1
0.0
400
ID, Drain Current (A)
*Notes:
1. VGS = 0 V
2. 250 ms Pulse Test
0.5
1.0
1.5
VSD, Body Diode Forward Voltage (V)
Figure 3. On−Resistance Variation vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current and Temperature
10000
10
1000
VGS, Gate−Source Voltage (V)
Ciss
Capacitance (pF)
4
Figure 2. Transfer Characteristics
10
Coss
*Notes:
100 1. VGS = 0 V
2. f = 1 MHz
10
0.1
3
VGS, Gate−Source Voltage (V)
Figure 1. On−Region Characteristics
4
0
−55°C
10
1
2
3
*Notes:
1. VDS = 10 V
2. 250 ms Pulse Test
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
1
Crss
10
8
6
4
2
0
0
100 200
VDS, Drain−Source Voltage (V)
VDS = 30 V
VDS = 75 V
VDS = 120 V
*Note: ID = 100 A
30
60
Qg, Total Gate Charge (nC)
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
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4
90
FDP075N15A, FDB075N15A
1.10
1.05
1.00
0.95
0.90
−100
*Notes:
1. VGS = 0 V
2. ID = 250 mA
−50
0
50
100
150
2.5
2.0
1.5
1.0
0.0
−100
200
150
200
1 ms
10
10 ms
100 ms
Operation in This Area
is Limited by RDS(on)
*Notes:
1. TC = 25°C
2. TJ = 175°C
3. Single Pulse
VGS = 10 V
100
ID, Drain Current (A)
ID, Drain Current (A)
100
120
100
DC
80
Limited by package
60
40
20
1
10
100
0
25
300
VDS, Drain−Source Voltage (V)
50
IAS, Avalanche Current (A)
6
5
4
3
2
1
50
75
100
125
50
75
100
125
150
175
Figure 10. Maximum Drain Current vs.
Case Temperature
7
25
RqJC = 0.45°C/W
TC, Case Temperature (°C)
Figure 9. Maximum Safe Operating Area
EOSS (mJ)
50
140
100 ms
0
0
0
Figure 8. On−Resistance Variation vs.
Temperature
1000
0.01
0.1
−50
TJ, Junction Temperature (°C)
Figure 7. Breakdown Voltage Variation vs.
Temperature
0.1
*Notes:
1. VGS = 10 V
2. ID = 100 A
0.5
TJ, Junction Temperature (°C)
1
(Continued)
3.0
RDS(ON), Drain−Source On−Resistance
(Normalized)
BVDSS, Drain−Source Breakdown Voltage
(Normalized)
TYPICAL PERFORMANCE CHARACTERISTICS
VDS, Drain to Source Voltage (V)
Starting TJ = 25°C
10
Starting TJ = 150°C
1
0.01
150
If R = 0
tAV = (L)(IAS)/(1.3*Rated BVDSS−VDD)
If R = 0
tAV = (L/R)In[(IAS*R)/(1.3*Rated BVDSS−VDD)+1]
0.1
1
10
100
TAV, Time in Avalanche (ms)
Figure 11. Eoss vs. Drain to Source Voltage
Figure 12. Unclamped Inductive
Switching Capability
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5
500
FDP075N15A, FDB075N15A
ZqJC(t), Thermal Response (°C/W)
TYPICAL PERFORMANCE CHARACTERISTICS
(Continued)
1
0.1
PDM
t1
t2
*Notes:
1. ZqJC(t) = 0.45°C/W Max.
2. Duty Factor, D= t1 / t2
3. TJM − TC = PDM * ZqJC(t)
0.01
0.001
−5
10
−4
10
−3
10
−2
10
t1, Rectangular Pulse Duration (s)
Figure 13. Transient Thermal Response Curve
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6
−1
10
1
FDP075N15A, FDB075N15A
IG = const.
Figure 14. Gate Charge Test Circuit & Waveform
V DS
RG
VGS
10V
RL
V DS
90%
V DD
V GS
V GS
DUT
10%
tr
td(on)
t on
Figure 15. Resistive Switching Test Circuit & Waveforms
VGS
Figure 16. Unclamped Inductive Switching Test Circuit & Waveforms
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7
td(off)f)
t off
tf
FDP075N15A, FDB075N15A
DUT
+
V DS
_
ISD
L
Driver
RG
Same Type
as DUT
V GS
V GS
(Driver)
V DD
• dv/dt controlled by RG
• ISD controlled by pulse period
D=
Gate Pulse Width
Gate Pulse Period
10 V
I FM , Body Diode Forward Current
I SD
di/dt
(DUT)
I RM
Body Diode Reverse Current
V DS
(DUT)
Body Diode Recovery dv/dt
V SD
Body Diode
Forward Voltage Drop
Figure 17. Peak Diode Recovery dv/dt Test Circuit & Waveforms
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8
V DD
FDP075N15A, FDB075N15A
PACKAGE MARKING AND ORDERING INFORMATION
Top Mark
Package
Reel Size
Tape Width
Shipping†
FDP075N15A−F102
FDP075N15A
TO−220
N/A
N/A
50 units / Tube
FDB075N15A
FDB075N15A
D2−PAK
330 mm
24 mm
800 units / Tape & Reel
Part Number
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United
States and/or other countries.
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9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−220
CASE 221A
ISSUE AK
DATE 13 JAN 2022
SCALE 1:1
STYLE 1:
PIN 1.
2.
3.
4.
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
BASE
EMITTER
COLLECTOR
EMITTER
STYLE 3:
PIN 1.
2.
3.
4.
CATHODE
ANODE
GATE
ANODE
STYLE 4:
PIN 1.
2.
3.
4.
MAIN TERMINAL 1
MAIN TERMINAL 2
GATE
MAIN TERMINAL 2
STYLE 5:
PIN 1.
2.
3.
4.
GATE
DRAIN
SOURCE
DRAIN
STYLE 6:
PIN 1.
2.
3.
4.
ANODE
CATHODE
ANODE
CATHODE
STYLE 7:
PIN 1.
2.
3.
4.
CATHODE
ANODE
CATHODE
ANODE
STYLE 8:
PIN 1.
2.
3.
4.
CATHODE
ANODE
EXTERNAL TRIP/DELAY
ANODE
STYLE 9:
PIN 1.
2.
3.
4.
GATE
COLLECTOR
EMITTER
COLLECTOR
STYLE 10:
PIN 1.
2.
3.
4.
GATE
SOURCE
DRAIN
SOURCE
STYLE 11:
PIN 1.
2.
3.
4.
DRAIN
SOURCE
GATE
SOURCE
STYLE 12:
PIN 1.
2.
3.
4.
MAIN TERMINAL 1
MAIN TERMINAL 2
GATE
NOT CONNECTED
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42148B
TO−220
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
D2PAK−3 (TO−263, 3−LEAD)
CASE 418AJ
ISSUE F
SCALE 1:1
GENERIC MARKING DIAGRAMS*
XX
XXXXXXXXX
AWLYWWG
IC
DOCUMENT NUMBER:
DESCRIPTION:
XXXXXXXXG
AYWW
Standard
98AON56370E
AYWW
XXXXXXXXG
AKA
Rectifier
XXXXXX
XXYMW
SSG
DATE 11 MAR 2021
XXXXXX = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
Y
= Year
WW
= Work Week
W
= Week Code (SSG)
M
= Month Code (SSG)
G
= Pb−Free Package
AKA
= Polarity Indicator
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
D2PAK−3 (TO−263, 3−LEAD)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
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vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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