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FDPC8011S
PowerTrench® Power Clip
25V Asymmetric Dual N-Channel MOSFET
Features
General Description
Q1: N-Channel
This device includes two specialized N-Channel MOSFETs in a
Max rDS(on) = 7.3 mΩ at VGS = 4.5 V, ID = 12 A
dual package. The switch node has been internally connected to
Q2: N-Channel
enable easy placement and routing of synchronous buck
Max rDS(on) = 2.1 mΩ at VGS = 4.5 V, ID = 24 A
converters. The control MOSFET (Q1) and synchronous
SyncFETTM (Q2) have been designed to provide optimal power
Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
efficiency.
MOSFET integration enables optimum layout for lower circuit
inductance and reduced switch node ringing
Applications
RoHS Compliant
Communications
Computing
General Purpose Point of Load
Pin 1
V+
Pin 1
LS
GND
GND
GND
(LSS
V+
(HSD
SW
HSG
SW
SW
HSG
PAD9
V+(HSD)
V+
LSG SW
SW
SW
PAD10
GND(LSS)
SW
Top
3.3 mm x 3.3 mm
V+
HSG
LSG
SW
GND SW
GND
GND
GND SW
Bottom
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
Drain to Source Voltage
Parameter
VGS
Gate to Source Voltage
Drain Current
ID
Q1
25
TJ, TSTG
V
12
12
TC = 25 °C
20
60
-Continuous
TA = 25 °C
131a
271b
40
120
Single Pulse Avalanche Energy
PD
Units
V
-Continuous (Package limited)
-Pulsed
EAS
Q2
25
21
97
Power Dissipation for Single Operation
TA = 25 °C
(Note 3)
1.61a
2.01b
Power Dissipation for Single Operation
TA = 25 °C
0.81c
0.91d
Operating and Storage Junction Temperature Range
A
mJ
-55 to +150
W
°C
Thermal Characteristics
RθJA
Thermal Resistance, Junction to Ambient
771a
631b
RθJA
Thermal Resistance, Junction to Ambient
1511c
1351d
RθJC
Thermal Resistance, Junction to Case
5.0
3.5
°C/W
Package Marking and Ordering Information
Device Marking
13OD/15OD
Device
FDPC8011S
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
Package
Power Clip 33
1
Reel Size
13 ”
Tape Width
12 mm
Quantity
3000 units
www.fairchildsemi.com
FDPC8011S PowerTrench® Power Clip
October 2014
Symbol
Parameter
Test Conditions
Type
Min
25
25
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 250 μA, VGS = 0 V
ID = 1 mA, VGS = 0 V
Q1
Q2
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID = 250 μA, referenced to 25 °C
ID = 10 mA, referenced to 25 °C
Q1
Q2
IDSS
Zero Gate Voltage Drain Current
VDS = 20 V, VGS = 0 V
VDS = 20 V, VGS = 0 V
Q1
Q2
1
500
μA
μA
IGSS
Gate to Source Leakage Current,
Forward
VGS = 12 V/-8 V, VDS= 0 V
VGS = 12 V/-8 V, VDS= 0 V
Q1
Q2
±100
±100
nA
nA
2.2
2.2
V
V
14
24
mV/°C
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 μA
VGS = VDS, ID = 1 mA
Q1
Q2
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250 μA, referenced to 25 °C
ID = 10 mA, referenced to 25 °C
Q1
Q2
-4
-3
VGS = 10 V, ID = 13 A
VGS = 4.5 V, ID = 12 A
VGS = 10 V, ID = 13 A,TJ =125 °C
Q1
4.6
5.4
5.6
6.0
7.3
7.3
VGS = 10 V, ID = 27 A
VGS = 4.5 V, ID = 24 A
VGS = 10 V, ID = 27 A ,TJ =125 °C
Q2
1.2
1.4
1.7
1.8
2.1
2.4
VDS = 5 V, ID = 13 A
VDS = 5 V, ID = 27 A
Q1
Q2
97
231
S
Q1:
VDS = 13 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
1240
4335
pF
Q1
Q2
332
1126
pF
Q1
Q2
49
143
pF
Q1
Q2
0.4
0.5
Ω
rDS(on)
gFS
Drain to Source On Resistance
Forward Transconductance
0.8
1.1
1.2
1.4
mV/°C
mΩ
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Rg
Gate Resistance
Q2:
VDS = 13 V, VGS = 0 V, f = 1 MHZ
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Rise Time
td(off)
Turn-Off Delay Time
tf
Fall Time
Qg
Total Gate Charge
Qg
Total Gate Charge
Qgs
Gate to Source Gate Charge
Qgd
Gate to Drain “Miller” Charge
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
Q1:
VDD = 13 V, ID = 13 A, RGEN = 6 Ω
Q2:
VDD = 13 V, ID = 27 A, RGEN = 6 Ω
VGS = 0 V to 10 V Q1
VDD = 13 V,
VGS = 0 V to 4.5 V ID = 13 A
Q2
VDD = 13 V,
ID = 27 A
2
Q1
Q2
7
13
ns
Q1
Q2
2
5
ns
Q1
Q2
20
38
ns
Q1
Q2
2
4
ns
Q1
Q2
19
64
nC
Q1
Q2
9
30
nC
Q1
Q2
2.6
9.3
nC
Q1
Q2
2.3
7.7
nC
www.fairchildsemi.com
FDPC8011S PowerTrench® Power Clip
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Q1
Q2
0.8
0.8
1.2
1.2
V
Q1
Q2
22
30
ns
Q1
Q2
8
32
nC
Drain-Source Diode Characteristics
VSD
Source to Drain Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
VGS = 0 V, IS = 13 A
VGS = 0 V, IS = 27 A
(Note 2)
(Note 2)
Q1
IF = 13 A, di/dt = 100 A/μs
Q2
IF = 27 A, di/dt = 300 A/μs
Notes:
1.RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by
the user's board design.
b. 63 °C/W when mounted on
a 1 in2 pad of 2 oz copper
a. 77 °C/W when mounted on
a 1 in2 pad of 2 oz copper
SS
SF
DS
DF
G
SS
SF
DS
DF
G
d. 135 °C/W when mounted on a
minimum pad of 2 oz copper
c. 151 °C/W when mounted on a
minimum pad of 2 oz copper
SS
SF
DS
DF
G
SS
SF
DS
DF
G
2 Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. Q1 :EAS of 21 mJ is based on starting TJ = 25 oC; N-ch: L = 1.2 mH, IAS = 6 A, VDD = 23 V, VGS = 10 V. 100% test at L= 0.1 mH, IAS = 14.5 A.
Q2: EAS of 97 mJ is based on starting TJ = 25 oC; N-ch: L = 0.6 mH, IAS = 18 A, VDD = 23 V, VGS = 10 V. 100% test at L= 0.1 mH, IAS = 32.9 A.
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
3
www.fairchildsemi.com
FDPC8011S PowerTrench® Power Clip
Electrical Characteristics TJ = 25 °C unless otherwise noted
4.0
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
40
VGS = 10 V
ID, DRAIN CURRENT (A)
VGS = 4.5 V
VGS = 3.5 V
30
VGS = 3 V
VGS = 2.5 V
20
10
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
0.0
0.3
0.6
0.9
1.2
3.0
2.5
VGS = 3 V
2.0
VGS = 3.5 V
1.5
1.0
0
10
20
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
rDS(on), DRAIN TO
1.0
0.8
0.6
-75
SOURCE ON-RESISTANCE (mΩ)
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
1.2
12
4
TJ = 25 oC
20
TJ = 25 oC
10
TJ = -55 oC
2.5
4
5
6
7
8
9
10
VGS = 0 V
10
1
TJ = 150 oC
TJ = 25 oC
0.1
TJ = -55 oC
0.01
0.0
3.0
VGS, GATE TO SOURCE VOLTAGE (V)
0.2
0.4
0.6
0.8
1.0
1.2
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
3
40
VDS = 5 V
2.0
2
Figure 4. On-Resistance vs Gate to
Source Voltage
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
1.5
TJ = 125 oC
8
VGS, GATE TO SOURCE VOLTAGE (V)
IS, REVERSE DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
16
-25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
TJ = 150 oC
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
ID = 13 A
0
-50
Figure 3. Normalized On Resistance
vs Junction Temperature
0
1.0
40
20
ID = 13 A
VGS = 10 V
1.4
30
30
Figure 2. Normalized On-Resistance
vs Drain Current and Gate Voltage
1.6
40
VGS = 10 V
VGS = 4.5 V
0.5
1.5
Figure 1. On Region Characteristics
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 2.5 V
3.5
Figure 6. Source to Drain Diode
Forward Voltage vs Source Current
4
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FDPC8011S PowerTrench® Power Clip
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
2000
ID = 13 A
1000
Ciss
8
CAPACITANCE (pF)
VGS, GATE TO SOURCE VOLTAGE (V)
10
6
VDD = 10 V
VDD = 15 V
4
VDD = 13 V
Coss
100
Crss
2
f = 1 MHz
VGS = 0 V
10
0.1
0
0
4
8
12
16
20
1
Figure 7. Gate Charge Characteristics
60
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
30
Figure 8. Capacitance vs Drain
to Source Voltage
50
TJ = 25 oC
10
TJ = 100 oC
TJ = 125 oC
VGS = 10 V
50
40
30
VGS = 4.5 V
20
Limited by Package
10
o
RθJC = 5.0 C/W
1
0.001
0.01
0.1
1
10
0
25
50
50
125
150
Figure 10. Maximum Continuous Drain
Current vs. Ambient Temperature
1000
P(PK), PEAK TRANSIENT POWER (W)
100
100 μs
10
0.1
100
TC, CASE TEMPERATURE ( C)
Figure 9. Unclamped Inductive
Switching Capability
1
75
o
tAV, TIME IN AVALANCHE (ms)
ID, DRAIN CURRENT (A)
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
1 ms
THIS AREA IS
LIMITED BY rDS(on)
10 ms
SINGLE PULSE
TJ = MAX RATED
100 ms
1s
RθJA = 151 oC/W
10s
TA = 25 oC
DC
0.01
0.01
0.1
1
10
100
VDS, DRAIN to SOURCE VOLTAGE (V)
o
RθJA = 151 C/W
100
10
1
0.5
-4
10
-3
10
-2
10
-1
10
0
10
1
100
10
1000
t, PULSE WIDTH (sec)
Figure 11. Forward Bias Safe
Operating Area
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
SINGLE PULSE
Figure 12. Single Pulse Maximum
Power Dissipation
5
www.fairchildsemi.com
FDPC8011S PowerTrench® Power Clip
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
NORMALIZED THERMAL
IMPEDANCE, ZθJA
1
0.1
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
t2
SINGLE PULSE
0.01
o
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
RθJA = 151 C/W
(Note 1b)
0.001 -4
10
-3
10
-2
10
-1
0
10
10
1
10
100
1000
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Junction-to-Ambient Transient Thermal Response Curve
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
6
www.fairchildsemi.com
FDPC8011S PowerTrench® Power Clip
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
25 oC unlenss otherwise noted
120
6
VGS = 4.5 V
100
ID, DRAIN CURRENT (A)
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
VGS = 10 V
VGS = 3.5 V
80
VGS = 3 V
60
VGS = 2.5 V
40
20
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
0.0
0.2
0.4
0.6
0.8
4
3
VGS = 3 V
2
VGS = 3.5 V
1
VGS = 4.5 V
0
1.0
0
20
Figure 14. On-Region Characteristics
60
80
100
120
Figure 15. Normalized on-Resistance vs Drain
Current and Gate Voltage
7
ID = 27 A
VGS = 10 V
rDS(on), DRAIN TO
1.4
1.2
1.0
0.8
0.6
-75
SOURCE ON-RESISTANCE (mΩ)
1.6
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
40
VGS = 10 V
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
6
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
5
ID = 27 A
4
3
1
TJ = 25 oC
0
-50
-25
0
25
50
75
TJ = 125 oC
2
100 125 150
2
TJ, JUNCTION TEMPERATURE (oC)
120
IS, REVERSE DRAIN CURRENT (A)
VDS = 5 V
80
60
TJ = 125 oC
40
TJ = 25 oC
20
TJ = -55 oC
0
1.0
1.5
2.0
2.5
200
100
8
10
VGS = 0 V
10
TJ = 125 oC
1
TJ = 25 oC
0.1
TJ = -55 oC
0.01
1E-3
0.0
3.0
VGS, GATE TO SOURCE VOLTAGE (V)
0.2
0.4
0.6
0.8
1.0
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 19. Source to Drain Diode
Forward Voltage vs Source Current
Figure 18. Transfer Characteristics
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
6
Figure 17. On-Resistance vs Gate to
Source Voltage
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
100
4
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 16. Normalized On-Resistance
vs Junction Temperature
ID, DRAIN CURRENT (A)
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 2.5 V
5
7
www.fairchildsemi.com
FDPC8011S PowerTrench® Power Clip
Typical Characteristics (Q2 N-Channel) TJ =
25 oC unlenss otherwise noted
10000
VGS, GATE TO SOURCE VOLTAGE (V)
10
Ciss
ID = 27 A
CAPACITANCE (pF)
8
VDD = 10 V
6
VDD = 13 V
4
VDD = 15 V
Coss
1000
Crss
2
f = 1 MHz
VGS = 0 V
100
50
0.1
0
0
10
20
30
40
50
60
70
1
120
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
100
TJ = 25 oC
TJ = 100 oC
10
TJ = 125 oC
100
VGS = 10 V
80
VGS = 4.5 V
60
40
Limited by Package
o
RθJC = 3.5 C/W
20
1
0.001
0.01
0.1
1
10
100
0
25
1000
50
100
125
150
TC, CASE TEMPERATURE ( C)
Figure 23. Maximum Continouns Drain
Current vs Ambient Temperature
Figure 22. Unclamped Inductive
Switching Capability
3000
P(PK), PEAK TRANSIENT POWER (W)
200
100
100 μs
ID, DRAIN CURRENT (A)
75
o
tAV, TIME IN AVALANCHE (ms)
10
0.1
30
Figure 21. Capacitance vs Drain
to Source Voltage
Figure 20. Gate Charge Characteristics
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
1 ms
10 ms
THIS AREA IS
LIMITED BY rDS(on)
100 ms
SINGLE PULSE
TJ = MAX RATED
1s
RθJA = 135 oC/W
10s
TA = 25 oC
DC
0.01
0.01
0.1
1
10
100
VDS, DRAIN to SOURCE VOLTAGE (V)
o
RθJA = 135 C/W
100
10
1
0.5
-4
10
-3
10
-2
10
-1
10
0
10
1
10
100
1000
t, PULSE WIDTH (sec)
Figure 25. Single Pulse Maximum
Power Dissipation
Figure 24. Forward Bias Safe
Operating Area
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
SINGLE PULSE
1000
8
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FDPC8011S PowerTrench® Power Clip
Typical Characteristics (Q2 N-Channel) TJ =
NORMALIZED THERMAL
IMPEDANCE, ZθJA
2
1
0.1
0.01
TJ = 25 oC unlenss otherwise noted
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
SINGLE PULSE
t2
o
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
RθJA = 135 C/W
1E-3
(Note 1b)
1E-4 -4
10
-3
10
-2
10
-1
0
10
10
1
10
100
1000
t, RECTANGULAR PULSE DURATION (sec)
Figure 26. Junction-to-Ambient Transient Thermal Response Curve
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
9
www.fairchildsemi.com
FDPC8011S PowerTrench® Power Clip
Typical Characteristics (Q2 N-Channel)
SyncFETTM Schottky body diode
Characteristics
Fairchild’s SyncFETTM process embeds a Schottky diode in
parallel with PowerTrench MOSFET. This diode exhibits similar
characteristics to a discrete external Schottky diode in parallel
with a MOSFET. Figure 27 shows the reverse recovery
characteristic of the FDPC8011S.
Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power
in the device.
35
IDSS, REVERSE LEAKAGE CURRENT (A)
-2
30
CURRENT (A)
25
20
di/dt = 300 A/μs
15
10
5
0
-5
100
150
200
250
300
350
400
TIME (ns)
TJ = 125 oC
-3
10
TJ = 100 oC
-4
10
-5
10
TJ = 25 oC
-6
10
0
5
10
15
20
25
VDS, REVERSE VOLTAGE (V)
Figure 28. SyncFETTM body diode reverse
leakage versus drain-source voltage
Figure 27. FDPC8011S SyncFETTM body
diode reverse recovery characteristic
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
10
10
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FDPC8011S PowerTrench® Power Clip
Typical Characteristics (continued)
Typical Application Diagram (Synchronous Rectifier Buck Converter)
Figure 1.Power Clip in Buck Converter Topology
As shown in Figure 1, in the Power Clip package Q1 is the High Side MOSFET (Control MOSFET) and Q2 is the Low Side MOSFET
(Synchronous MOSFET). Figure 2 below shows the package pin out. The blue overlay on the drawing indicates a typical PCB land
pattern for the part.
Figure 2.Top View of Power Clip
Table 1 Pin Information shows the name and description of each pin.
PIN
Number
Description
Name
1
HSG
2,3,4
SW
Switch or Phase node, Source of Q1 and Drain of Q2
5,6,PAD 10
GND,GND(LSS) PAD
Ground, Source of Q2
7
LSG
Gate signal input of Q2 Gate
8,PAD 9
V+, V+(HSD) PAD
Table 1. Pin Information
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
Gate signal input of Q1 Gate
Input voltage of SR Buck converter, Drain of Q1
11
www.fairchildsemi.com
FDPC8011S PowerTrench® Power Clip
Application Information
As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power
train. Power Clip is a high power density solution and all high current flow paths, such as V+(HSD), SW and GND(LSS) should be
short and wide for minimal resistance and inductance. V+(HSD) and GND(LSS) are the primary heat flow paths for the Power Clip.
A recommended layout procedure is discussed below to maximize the electrical and thermal performance of the part.
Figure 3.Top/Component (green) View and Bottom (red) PCB View
Following is a guideline, not a requirement which the PCB designer should consider.
Figure 3 shows an example of a well designed layout. The discussion that follows summarizes the key features of this layout.
"The input ceramic bypass capacitor between VIN and GND should be placed as close as possible to the pins V+ / V+(HSD) PAD
and GND / GND(LSS) PAD to help reduce parasitic inductance and high frequency ringing. Several capacitors may be placed in
parallel, and capacitors may be placed on both the top and bottom side of the board. The capacitor located immediately adjacent
to the Power Clip will be the most effective at reducing HF parasitic. Caps located farther away, or on the opposite side of the board
will also assist, but will be less effective due to increased trace inductance.
"The Power Clip package design, with very short distance between pins V+ and GND, allows for a short connect distance to the
input cap. This is a factor that enables the Power Clip switch loop to have very low parasitic inductance.
"Use large copper areas on the component side to connect the V+ pin and V+ (HSD) pad, and the GND and GND(LSS) PAD.
"The SW to inductor copper trace is a high current path. It will also be a high noise region due to switching voltage transients. The
trace should be short and wide to enable a low resistance path and to minimize the size of the noise region. Care should be taken
to minimize coupling of this trace to adjacent traces. The layout in Figure 3 shows a good example of this short, wide path.
"The Power Trench® Technology MOSFETs used in the Power Clip are effective at minimizing SW node ringing. They incorporate
a proprietary design1 that minimizes the peak overshoot ring voltage on the switch node (SW). They allow the part to operate well
within the breakdown voltage limits. For most layouts, this eliminates the need to add an external snubber circuit. If the designer
chooses to use an RC snubber, it should be placed close to the part between the SW pins and GND / GND (LSS) PAD to dampen
the high frequency ringing.
"The Driver IC should be placed relatively closed to HSG pin and LSG pin to minimize G drive trace inductance. Excessive G trace
length may slow the switching speed of the HS drive. And it may lead to excessive ringing on the LS G. If the designer must place
the driver a significant distance away from the Power Clip, it would be a good practice to include a 0 Ohm resistor in the LS G path
as a place holder. In the final design, if the LS G exhibits excessive LF ringing, efficiency can often be improved by changing this
resistor to a few Ohms to dampen the LS G LF ringing.
"The Power Clip has very good Junction-PCB heat transfer from all power pins. It has much better heat transfer Junction-GND (LSS)
than traditional dual FET packages. In most cases, board ground will be the most effective heat transfer path on the PCB. Use a
large copper area between GND / GND(LSS)PAD pins and board ground. To ensure the best thermal and electrical connection to
ground, we recommend using multiple vias to interconnect ground plane layers as shown in Figure 3.
1.Patent Pending
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
12
www.fairchildsemi.com
FDPC8011S PowerTrench® Power Clip
Recommended PCB Layout Guidelines
"Avoid using narrow thermal relief traces on the V+ / V+(HSD) PAD and GND / GND(LSS)PAD pins. These will increase HF switch
loop inductance. And these will increase ringing of the HF power loop and the SW node.
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
13
www.fairchildsemi.com
FDPC8011S PowerTrench® Power Clip
"Use multiple vias in parallel on each copper region to interconnect top, inner and bottom layers. This will reduce resistance and
inductance of the vias and will improve thermal conductivity. Vias should be relatively large, around 8 mils to 10 mils.
FDPC8011S PowerTrench® Power Clip
Dimensional Outline and Pad Layout
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
https://www.fairchildsemi.com/evaluate/package-specifications/packageDetails.html?id=PN_PQDEU-X08.
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
14
www.fairchildsemi.com
tm
*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE
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WEBSITE AT HTTP://WWW.FAIRCHILDSEMI.COM. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF
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WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE
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As used here in:
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intended for surgical implant into the body or (b) support or sustain life,
and (c) whose failure to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury of the user.
2.
A critical component in any component of a life support, device, or
system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or
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Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website,
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Counterfeiting of semiconductor parts is a growing problem in the industry. All manufactures of semiconductor products are experiencing counterfeiting of their
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proliferation of counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative / In Design
Datasheet contains the design specifications for product development. Specifications
may change in any manner without notice.
Preliminary
First Production
Datasheet contains preliminary data; supplementary data will be published at a later
date. Fairchild Semiconductor reserves the right to make changes at any time without
notice to improve design.
No Identification Needed
Full Production
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve the design.
Obsolete
Not In Production
Datasheet contains specifications on a product that is discontinued by Fairchild
Semiconductor. The datasheet is for reference information only.
Rev. I71
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
15
www.fairchildsemi.com
FDPC8011S PowerTrench® Power Clip
TRADEMARKS
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not
intended to be an exhaustive list of all such trademarks.
F-PFS™
AccuPower™
®*
®
FRFET®
Awinda®
®
PowerTrench®
AX-CAP *
Global Power ResourceSM
®
TinyBoost
GreenBridge™
PowerXS™
BitSiC™
TinyBuck®
Green FPS™
Programmable Active Droop™
Build it Now™
TinyCalc™
®
Green FPS™ e-Series™
QFET
CorePLUS™
TinyLogic®
QS™
Gmax™
CorePOWER™
TINYOPTO™
CROSSVOLT™
Quiet Series™
GTO™
TinyPower™
CTL™
RapidConfigure™
IntelliMAX™
TinyPWM™
Current Transfer Logic™
ISOPLANAR™
™
TinyWire™
DEUXPEED®
Marking Small Speakers Sound Louder
TranSiC™
Dual Cool™
Saving our world, 1mW/W/kW at a time™
and Better™
TriFault Detect™
SignalWise™
EcoSPARK®
MegaBuck™
TRUECURRENT®*
SmartMax™
EfficentMax™
MICROCOUPLER™
μSerDes™
SMART START™
ESBC™
MicroFET™
Solutions
for
Your
Success™
MicroPak™
®
SPM®
MicroPak2™
®
UHC®
STEALTH™
MillerDrive™
Fairchild
®
®
SuperFET
Ultra
FRFET™
MotionMax™
Fairchild Semiconductor
SuperSOT™-3
UniFET™
MotionGrid®
FACT Quiet Series™
®
MTi
SuperSOT™-6
VCX™
FACT®
SuperSOT™-8
MTx®
VisualMax™
FAST®
®
®
SupreMOS
VoltagePlus™
MVN
FastvCore™
®
mWSaver
SyncFET™
XS™
FETBench™
Sync-Lock™
OptoHiT™
Xsens™
FPS™
仙童 ™
2X
KEEP-OUT
AREA
A
8
5
(3.70)
5
(0.80)
(1.60)
(0.79) 8X
0.05 C
4
1
(0.25)
8
3.30
PIN # 1
INDICATOR
(3.40)
(2.80)
(2.37)
B
3.30
0.05 C
2X (0.26)
2X
1
4
(0.42) 8X
(0.85)
TOP VIEW
0.65
(1.65)
LAND PATTERN RECOMMENDATION
SEE
DETAIL A
0.10 C
FRONT VIEW
0.75±0.05
0.025±0.025
0.08 C
C
3.30±0.05
0.18±0.05
1.85±0.10
0.65
0.79±0.10
DETAIL 'A'
0.32±0.05
8X
1.05±0.10
1
4
0.10
0.05
3.30±0.05
1.50±0.10 2X
(0.75)
0.54±0.10 8X
8
SCALE 2:1
(0.30)
4X
2X (0.36)
C A B
C
SEATING
PLANE
5
(0.20)
(0.40)
1.55±0.10
BOTTOM VIEW
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE IS REFERENCED FROM
JEDEC MO-240, VARIATION BA.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-2009.
E) IT IS RECOMMENDED TO HAVE NO TRACES
OR VIAS WITHIN THE KEEP OUT AREA.
F) DRAWING FILE NAME: MKT-PQFN08GREV4
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