FDPF12N60NZ

FDP12N60NZ / FDPF12N60NZ N-Channel UniFETTM II MOSFET 600 V, 12 A, 650 mΩ Features Description • RDS(on) = 530 mΩ (Typ.) @ VGS = 10 V, ID = 6 A UniFETTM II MOSFET is Fairchild Semiconductor’s high voltage MOSFET family based on advanced planar stripe and DMOS technology. This advanced MOSFET family has the smallest on-state resistance among the planar MOSFET, and also provides superior switching performance and higher avalanche energy strength. In addition, internal gate-source ESD diode allows UniFET II MOSFET to withstand over 2kV HBM surge stress. This device family is suitable for switching power converter applications such as power factor correction (PFC), flat panel display (FPD) TV power, ATX and electronic lamp ballasts. • Low Gate Charge (Typ. 26 nC) • Low Crss (Typ. 12 pF) • 100% Avalanche Tested • Improved dv/dt Capability • ESD Improved Capability • RoHS Compliant Applications • LCD/ LED/ PDP TV • Lighting • Uninterruptible Power Supply D GD S G G D S TO-220 TO-220F S MOSFET Maximum Ratings TC = 25oC unless otherwise noted. Symbol VDSS Drain to Source Voltage Parameter VGSS Gate to Source Voltage ID Drain Current - Continuous (TC = 25oC) - Continuous (TC = 100oC) (Note 1) Unit V ±30 V 12 12* 7.2 7.2* IDM Drain Current Single Pulsed Avalanche Energy IAR Avalanche Current (Note 1) 12 A EAR Repetitive Avalanche Energy (Note 1) 24 mJ 20 V/ns (Note 2) Peak Diode Recovery dv/dt (Note 3) (TC = 25oC) Power Dissipation TJ, TSTG Operating and Storage Temperature Range Maximum Lead Temperature for Soldering, 1/8” from Case for 5 Seconds - Derate Above 25oC 48* A 565 MOSFET dv/dt Ruggedness PD TL 48 A EAS dv/dt - Pulsed FDP12N60NZ FDPF12N60NZ 600 mJ 10 V/ns 240 39 W 2.0 0.3 W/oC -55 to +150 o C 300 o C *Drain current limited by maximum junction temperature Thermal Characteristics Symbol Parameter FDP12N60NZ FDPF12N60NZ RθJC Thermal Resistance, Junction to Case, Max. 0.52 3.2 RθJA Thermal Resistance, Junction to Ambient, Max. 62.5 62.5 ©2010 Fairchild Semiconductor Corporation FDP12N60NZ / FDPF12N60NZ Rev. C2 1 Unit o C/W www.fairchildsemi.com FDP12N60NZ / FDPF12N60NZ — N-Channel UniFETTM II MOSFET November 2013 Part Number Top Mark FDP12N60NZ FDP12N60NZ Package TO-220 Packing Method Tube Reel Size N/A Tape Width N/A Quantity 50 units FDPF12N60NZ FDPF12N60NZ TO-220F Tube N/A N/A 50 units Electrical Characteristics Symbol TC = 25oC unless otherwise noted. Parameter Test Conditions Min. Typ. Max. Unit 600 - - V - 0.6 - V/oC Off Characteristics BVDSS ΔBVDSS / ΔTJ Drain to Source Breakdown Voltage Breakdown Voltage Temperature Coefficient IDSS Zero Gate Voltage Drain Current IGSS Gate to Body Leakage Current ID = 250 μA, VGS = 0 V, TJ = 25oC ID = 250 μA, Referenced to 25oC VDS = 600 V, VGS = 0 V - - 1 VDS = 480 V, TC = 125oC - - 10 VGS = ±30 V, VDS = 0 V - - ±10 μA μA On Characteristics VGS(th) RDS(on) Gate Threshold Voltage VGS = VDS, ID = 250 μA 3 - 5 V Static Drain to Source On Resistance VGS = 10 V, ID = 6 A - 0.53 0.65 Ω gFS Forward Transconductance VDS = 20 V, ID = 6 A - 13.5 - S VDS = 25 V, VGS = 0 V, f = 1 MHz - 1260 1676 pF - 150 200 pF - 12 18 pF - 26 34 nC - 6 - nC - 10 - nC Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Qg(tot) Total Gate Charge at 10V Qgs Gate to Source Gate Charge Qgd Gate to Drain “Miller” Charge VDS = 480 V, ID = 12 A, VGS = 10 V (Note 4) Switching Characteristics td(on) Turn-On Delay Time tr Turn-On Rise Time td(off) Turn-Off Delay Time tf Turn-Off Fall Time VDD = 300 V, ID = 12 A, VGS = 10 V, RG = 25 Ω (Note 4) - 25 60 ns - 50 110 ns - 80 170 ns - 60 130 ns Drain-Source Diode Characteristics IS Maximum Continuous Drain to Source Diode Forward Current - - 12 A ISM Maximum Pulsed Drain to Source Diode Forward Current - - 48 A VSD Drain to Source Diode Forward Voltage VGS = 0 V, ISD = 12 A - - 1.4 V trr Reverse Recovery Time - 350 - ns Qrr Reverse Recovery Charge VGS = 0 V, ISD = 12 A, dIF/dt = 100 A/μs - 2.2 - μC Notes: 1: Repetitive rating: pulse-width limited by maximum junction temperature. 2: L = 7.85 mH, IAS = 12 A, VDD = 50 V, RG = 25 Ω, starting TJ = 25°C. 3: ISD ≤ 12 A, di/dt ≤ 200 A/μs, VDD ≤ BVDSS, starting TJ = 25°C. 4: Essentially independent of operating temperature typical characteristics. ©2010 Fairchild Semiconductor Corporation FDP12N60NZ / FDPF12N60NZ Rev. C2 2 www.fairchildsemi.com FDP12N60NZ / FDPF12N60NZ — N-Channel UniFETTM II MOSFET Package Marking and Ordering Information Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 100 30 ID, Drain Current[A] 10 ID, Drain Current[A] VGS = 15.0 V 10.0 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V 1 o 10 150 C o 25 C o -55 C 1 *Notes: 1. 250μs Pulse Test * Notes : 1. VDS = 20V 2. 250μs Pulse Test o 2. TC = 25 C 0.1 0.1 0.1 1 VDS, Drain-Source Voltage[V] 10 20 3 4 5 6 7 VGS, Gate-Source Voltage[V] Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature 1.0 100 0.9 IS, Reverse Drain Current [A] RDS(on) [Ω], Drain-Source On-Resistance Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage 0.8 VGS = 10V 0.7 VGS = 20V 0.6 o 150 C 10 o 25 C Notes: 1. VGS = 0V o 0.5 2. 250μs Pulse Test * Note : TJ = 25 C 0 5 10 15 20 ID, Drain Current [A] 25 1 0.4 30 Figure 5. Capacitance Characteristics VGS, Gate-Source Voltage [V] 1000 Coss 10 0.1 1.4 10 Ciss 100 0.6 0.8 1.0 1.2 VSD, Body Diode Forward Voltage [V] Figure 6. Gate Charge Characteristics 5000 Capacitances [pF] 8 Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd * Note: 1. VGS = 0V 2. f = 1MHz 1 10 VDS, Drain-Source Voltage [V] ©2010 Fairchild Semiconductor Corporation FDP12N60NZ / FDPF12N60NZ Rev. C2 Crss VDS = 120V VDS = 300V VDS = 480V 8 6 4 2 * Note : ID = 12A 0 30 3 0 6 12 18 24 Qg, Total Gate Charge [nC] 30 www.fairchildsemi.com FDP12N60NZ / FDPF12N60NZ — N-Channel UniFETTM II MOSFET Typical Performance Characteristics Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs Temperature 3.0 RDS(on), [Normalized] Drain-Source On-Resistance BVDSS, [Normalized] Drain-Source Breakdown Voltage 1.2 1.1 1.0 0.9 * Notes : 1. VGS = 0V 2. ID = 250uA 0.8 -80 -40 0 40 80 120 o TJ, Junction Temperature [ C] 2.5 2.0 1.5 1.0 * Notes : 1. VGS = 10V 2. ID = 6A 0.5 0 -80 160 Figure 9. Maximum Safe Operating Area - FDPF12N60NZ -40 0 40 80 120 o TJ, Junction Temperature [ C] Figure 10. Maximum Safe Operating Area - FDP12N60NZ 100 100 10μs 30μs 100μs ID, Drain Current [A] ID, Drain Current [A] 100μs 10 1ms 10ms 1 Operation in This Area is Limited by R DS(on) DC * Notes : 0.1 10 1ms 10ms DC 1 Operation in This Area is Limited by R DS(on) * Notes : 0.1 o o 1. TC = 25 C 1. TC = 25 C o 0.01 160 o 2. TJ = 150 C 3. Single Pulse 1 10 100 VDS, Drain-Source Voltage [V] 0.01 1000 2. TJ = 150 C 3. Single Pulse 1 10 100 VDS, Drain-Source Voltage [V] 1000 Figure 11. Maximum Drain Current vs. Case Temperature 15 ID, Drain Current [A] 12 9 6 3 0 25 50 75 100 125 o TC, Case Temperature [ C] ©2010 Fairchild Semiconductor Corporation FDP12N60NZ / FDPF12N60NZ Rev. C2 150 4 www.fairchildsemi.com FDP12N60NZ / FDPF12N60NZ — N-Channel UniFETTM II MOSFET Typical Performance Characteristics (Continued) FDP12N60NZ / FDPF12N60NZ — N-Channel UniFETTM II MOSFET Typical Performance Characteristics (Continued) o Z Response θJC(t), Thermal Thermal Response [ZθJC[] C/W] Figure 12. Transient Thermal Response Curve - FDPF12N60NZ 5 0.5 1 0.2 0.1 0.05 0.1 P 0.02 DM 0.01 0.01 t 1 t 2 * Notes : Single pulse o 1. ZθJC(t) = 3.2 C/W Max. 2. Duty Factor, D=t1/t2 3. TJM - TC = PDM * ZθJC(t) 0.001 -5 10 -4 10 -3 10 -2 -1 10 10 1 2 10 10 3 10 tRectangular PulseDuration Duration [sec] [sec] Pulse 1, Rectangular 1 0.5 θ JC o ZThermal Response θJC(t), Thermal Response [Z []C/W] Figure 13. Transient Thermal Response Curve - FDP12N60NZ 0.2 0.1 0.1 0.05 0.02 P DM t 0.01 0.01 t 2 * Notes : Single pulse 0.001 -5 10 1 o 1. ZθJC(t) = 0.52 C/W Max. 2. Duty Factor, D=t1/t2 3. TJM - TC = PDM * ZθJC(t) -4 10 -3 10 -2 -1 10 10 1 10 2 10 3 10 [sec] tRectangular Pulse Duration Duration [sec] 1, RectangularPulse ©2010 Fairchild Semiconductor Corporation FDP12N60NZ / FDPF12N60NZ Rev. C2 5 www.fairchildsemi.com FDP12N60NZ / FDPF12N60NZ — N-Channel UniFETTM II MOSFET IG = const. Figure 14. Gate Charge Test Circuit & Waveform VDS RG RL VDS VDD VGS VGS DUT V 10V GS 90% 10% td(on) tr t on td(off) tf t off Figure 15. Resistive Switching Test Circuit & Waveforms VGS Figure 16. Unclamped Inductive Switching Test Circuit & Waveforms ©2010 Fairchild Semiconductor Corporation FDP12N60NZ / FDPF12N60NZ Rev. C2 6 www.fairchildsemi.com FDP12N60NZ / FDPF12N60NZ — N-Channel UniFETTM II MOSFET DUT + VDS _ I SD L Driver RG VGS VGS ( Driver ) Same Type as DUT VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop Figure 17. Peak Diode Recovery dv/dt Test Circuit & Waveforms ©2010 Fairchild Semiconductor Corporation FDP12N60NZ / FDPF12N60NZ Rev. C2 7 www.fairchildsemi.com FDP12N60NZ / FDPF12N60NZ — N-Channel UniFETTM II MOSFET Mechanical Dimensions Figure 18. TO-220, Molded, 3-Lead, Jedec Variation AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/package/packageDetails.html?id=PN_TT220-003 ©2010 Fairchild Semiconductor Corporation FDP12N60NZ / FDPF12N60NZ Rev. C2 8 www.fairchildsemi.com FDP12N60NZ / FDPF12N60NZ — N-Channel UniFETTM II MOSFET Mechanical Dimensions Figure 19. TO220, Molded, 3-Lead, Full Pack, EIAJ SC91, Straight Lead Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/package/packageDetails.html?id=PN_TF22S-003 ©2010 Fairchild Semiconductor Corporation FDP12N60NZ / FDPF12N60NZ Rev. C2 9 www.fairchildsemi.com tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative / In Design Datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I66 ©2010 Fairchild Semiconductor Corporation FDP12N60NZ / FDPF12N60NZ Rev. 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