FDT461N
N-Channel Logic Level PowerTrench® MOSFET
100V, 0.4A, 2.5Ω
Features
Applications
• rDS(ON) = 1.45Ω (Typ.), VGS = 4.5V, ID = 0.4A
• Servo Motor Load Control
• Qg(tot) = 2.36nC (Typ.), VGS = 10V
• DC-DC converters
• Low Miller Charge
• Low QRR Body Diode
DRAIN
(FLANGE)
D
GATE
DRAIN
SOURCE
G
SOT-223
S
D
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Symbol
VDSS
Drain to Source Voltage
Parameter
Ratings
100
Units
V
VGS
Gate to Source Voltage
±20
V
Continuous (TA = 25oC, VGS = 10V, RθJA= 110oC/W)
0.54
A
Continuous (TA = 25oC, VGS = 4.5V, RθJA= 110oC/W)
0.4
A
Drain Current
ID
Pulsed
EAS
PD
Figure 4
A
Single Pulse Avalanche Energy (Note 1)
6.3
mJ
Power dissipation
1.13
W
9
mW/oC
-55 to 150
oC
Derate above 25oC
TJ, TSTG
Operating and Storage Temperature
Thermal Characteristics
RθJA
Thermal Resistance Junction to Ambient SOT-223, Pad area = 0.171 in2
110
o
C/W
RθJA
Thermal Resistance Junction to Ambient SOT-223, Pad area = 0.068 in
2
128
o
C/W
RθJA
Thermal Resistance Junction to Ambient SOT-223, Pad area = 0.026 in2
147
oC/W
Package Marking and Ordering Information
Device Marking
461
©2004 Fairchild Semiconductor Corporation
Device
FDT461N
Package
SOT-223
Reel Size
13”
Tape Width
12mm
Quantity
2500 units
FDT461N Rev. A1
FDT461N
April 2004
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
100
-
-
-
V
-
1
-
-
250
µA
-
-
±100
nA
V
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
VDS = 80V
VGS = 0V
TC = 125oC
VGS = ±20V
On Characteristics
VGS(TH)
rDS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
VGS = VDS, ID = 250µA
0.8
-
2
ID = 0.54A, VGS = 10V
-
1.40
2.0
ID = 0.4A, VGS = 4.5V
-
1.45
2.5
ID = 0.54A, VGS = 10V,
TJ = 150oC
-
2.80
4.0
VDS = 25V, VGS = 0V,
f = 1MHz
-
74
-
pF
-
11
-
pF
Ω
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
Qg(TOT)
Total Gate Charge at 10V
Qg(4.5)
Total Gate Charge at 4.5V
VGS = 0V to 4.5V
Qg(TH)
Threshold Gate Charge
VGS = 0V to 1V
Qgs
Gate to Source Gate Charge
Qgs2
Gate Charge Threshold to Plateau
Qgd
Gate to Drain “Miller” Charge
Switching Characteristics
-
VGS = 0V to 10V
VDD = 50V
ID = 0.54A
Ig = 1.0mA
2.5
-
pF
2.36
4.0
nC
1.27
2.0
nC
0.1
0.15
nC
-
0.37
-
nC
-
0.27
-
nC
-
0.25
-
nC
(VGS = 10V)
tON
Turn-On Time
-
-
6.5
ns
td(ON)
Turn-On Delay Time
-
3
-
ns
tr
Rise Time
-
1.3
-
ns
td(OFF)
Turn-Off Delay Time
-
63
-
ns
tf
Fall Time
-
12
-
ns
tOFF
Turn-Off Time
-
-
113
ns
ISD = 0.54A
-
-
1.25
V
ISD = 0.3A
-
-
1.0
V
VDD = 50V, ID = 0.54A
VGS = 10V, RGS = 120Ω
Drain-Source Diode Characteristics
VSD
Source to Drain Diode Voltage
trr
Reverse Recovery Time
ISD = 0.54A, dISD/dt = 100A/µs
-
-
22
ns
QRR
Reverse Recovered Charge
ISD = 0.54A, dISD/dt = 100A/µs
-
-
18
nC
Notes:
1: Starting TJ = 25°C, L = 67mH, IAS = 0.43A.
©2004 Fairchild Semiconductor Corporation
FDT461N Rev. A1
FDT461N
Electrical Characteristics TA = 25°C unless otherwise noted
FDT461N
Typical Characteristics TA = 25°C unless otherwise noted
0.6
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
VGS = 10V
0.4
VGS = 4.5V
0.2
0.2
0
0
0
25
50
75
100
125
150
25
50
TA , AMBIENT TEMPERATURE (oC)
75
100
125
150
TA, CASE TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
THERMAL IMPEDANCE
ZθJA, NORMALIZED
1
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
102
103
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
10
TA = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
IDM, PEAK CURRENT (A)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
I = I25
150 - TA
125
VGS = 4.5V
1
0.4
10-5
10-4
10-3
10-2
10-1
100
101
102
103
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
©2004 Fairchild Semiconductor Corporation
FDT461N Rev. A1
FDT461N
Typical Characteristics TA = 25°C unless otherwise noted
1.6
100µs
1
ID , DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
4
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
0.1
10ms
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
1.2
0.8
TJ = 175oC
TJ = 25oC
0.4
TJ = -55oC
SINGLE PULSE
TJ = MAX RATED
TA = 25oC
0.01
0
1
10
120
1.5
2.0
VDS, DRAIN TO SOURCE VOLTAGE (V)
2.5
Figure 5. Forward Bias Safe Operating Area
3.0
PULSE DURATION = 80ms
DUTY CYCLE = 0.5% MAX
VGS = 4.5V
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (Ω)
VGS = 3V
ID, DRAIN CURRENT (A)
3.5
Figure 6. Transfer Characteristics
1.6
1.2
0.8
VGS = 2.5V
0.4
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
2.5
ID = 0.54A
2.0
1.5
ID = 0.2A
TA = 25oC
0
1.0
0
0.5
1.0
1.5
2.0
2.5
VDS , DRAIN TO SOURCE VOLTAGE (V)
2
3.0
Figure 7. Saturation Characteristics
3
4
5
6
7
8
VGS, GATE TO SOURCE VOLTAGE (V)
9
10
Figure 8. Drain to Source On Resistance vs Gate
Voltage and Drain Current
1.2
2.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = VDS, ID = 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
3.0
VGS , GATE TO SOURCE VOLTAGE (V)
1.5
1.0
1.0
0.8
VGS = 10V, ID = 0.54A
0.5
0.6
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
Figure 9. Normalized Drain to Source On
Resistance vs Junction Temperature
©2004 Fairchild Semiconductor Corporation
160
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
Figure 10. Normalized Gate Threshold Voltage vs
Junction Temperature
FDT461N Rev. A1
FDT461N
Typical Characteristics TA = 25°C unless otherwise noted
200
CISS = CGS + CGD
100
ID = 250µA
C, CAPACITANCE (pF)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.2
1.1
1.0
COSS ≅ CDS + CGD
10
CRSS = CGD
VGS = 0V, f = 1MHz
1
0.9
-80
-40
0
40
80
120
0.1
160
1
TJ , JUNCTION TEMPERATURE (oC)
10
100
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 11. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
Figure 12. Capacitance vs Drain to Source
Voltage
VGS , GATE TO SOURCE VOLTAGE (V)
10
VDD = 50V
8
6
ID = 0.54A
4
2
0
0
0.5
1.0
1.5
2.0
2.5
Qg, GATE CHARGE (nC)
Figure 13. Gate Charge Waveforms for Constant Gate Current
Test Circuits and Waveforms
VDS
BVDSS
tP
L
VDS
VARY tP TO OBTAIN
REQUIRED PEAK IAS
IAS
+
RG
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0.01Ω
0
tAV
Figure 14. Unclamped Energy Test Circuit
©2004 Fairchild Semiconductor Corporation
Figure 15. Unclamped Energy Waveforms
FDT461N Rev. A1
FDT461N
Test Circuits and Waveforms (Continued)
VDS
VDD
Qg(TOT)
VDS
L
VGS = 10V
VGS
+
Qg(4.5)
VDD
-
VGS = 4.5V
VGS
DUT
VGS = 1V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 16. Gate Charge Test Circuit
Figure 17. Gate Charge Waveforms
VDS
tON
tOFF
td(ON)
td(OFF)
RL
tf
tr
VDS
90%
90%
+
VGS
VDD
-
10%
10%
0
DUT
90%
RGS
VGS
50%
50%
PULSE WIDTH
VGS
0
Figure 18. Switching Time Test Circuit
©2004 Fairchild Semiconductor Corporation
10%
Figure 19. Switching Time Waveforms
FDT461N Rev. A1
.SUBCKT FDT461N 2 1 3 ; rev January 2004
Ca 12 8 1.5e-10
Cb 15 14 1.1e-10
Cin 6 8 7.0e-11
LDRAIN
DPLCAP
DRAIN
2
5
10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
5
51
ESLC
EVTHRES
+ 19 8
+
LGATE
GATE
1
11
+
17
EBREAK 18
-
50
RDRAIN
6
8
ESG
DBREAK
+
RSLC2
Ebreak 11 7 17 18 109.7
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
RLDRAIN
RSLC1
51
EVTEMP
RGATE + 18 22
9
20
21
16
DBODY
MWEAK
6
MMED
MSTRO
RLGATE
Lgate 1 9 5.29e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 5.71e-9
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
RLSOURCE
RLgate 1 9 52.9
RLdrain 2 5 10
RLsource 3 7 57.1
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
S1A
12
S2A
13
8
14
13
S1B
CA
15
17
18
RVTEMP
S2B
13
CB
19
6
8
VBAT
5
8
EDS
-
IT
14
+
+
EGS
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 0.9
Rgate 9 20 3.94
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 0.5
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
RBREAK
-
+
8
22
RVTHRES
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*15),2.5))}
.MODEL DbodyMOD D (IS=6.4E-11 RS=8.0e-3 IKF=0.9 TRS1=2.5e-3 TRS2=9.5e-6
+ CJO=2.2e-11 M=0.52 TT=2.9e-8 XTI=0.1)
.MODEL DbreakMOD D (RS=0.6 TRS1=1.4e-3 TRS2=-5.0e-5)
.MODEL DplcapMOD D (CJO=3.9e-11 IS=1e-30 N=10 M=0.67)
.MODEL MmedMOD NMOS (VTO=1.75 KP=1.2 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.94 T_ABS=25)
.MODEL MstroMOD NMOS (VTO=2.03 KP=12 IS=1e-30 N=10 TOX=1 L=1u W=1u T_ABS=25)
.MODEL MweakMOD NMOS (VTO=1.46 KP=0.02 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=39.4 RS=0.1 T_ABS=25)
.MODEL RbreakMOD RES (TC1=1.0e-3 TC2=-8.8e-7)
.MODEL RdrainMOD RES (TC1=7.0e-3 TC2=2.0e-5)
.MODEL RSLCMOD RES (TC1=1.0e-3 TC2=9.0e-6)
.MODEL RsourceMOD RES (TC1=4.8e-3 TC2=1.0e-6)
.MODEL RvthresMOD RES (TC1=-9.0e-4 TC2=-7.0e-6)
.MODEL RvtempMOD RES (TC1=-2.1e-3 TC2=1.8e-6)
MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5.0 VOFF=-2.0)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=-5.0)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.4 VOFF=0.3)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.3 VOFF=-0.4)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2004 Fairchild Semiconductor Corporation
FDT461N Rev. A1
FDT461N
PSPICE Electrical Model
FDT461N
SABER Electrical Model
rev January 2004
template FDT461N n2,n1,n3 = m_temp
number m_temp=25
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=6.4e-11,rs=8.0e-3,ikf=0.9,trs1=2.5e-3,trs2=9.5e-6,cjo=2.2e-11,m=0.52,tt=2.9e-8,xti=0.1)
dp..model dbreakmod = (rs=0.6,trs1=1.4e-3,trs2=-5e-5)
dp..model dplcapmod = (cjo=3.9e-11,isl=10e-30,nl=10,m=0.67)
m..model mmedmod = (type=_n,vto=1.75,kp=1.2,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.03,kp=12,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.46,kp=0.02,is=1e-30, tox=1,rs=0.1)
LDRAIN
DPLCAP 5
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-5.0,voff=-2.0)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2.0,voff=-5.0)
10
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.4,voff=0.3)
RLDRAIN
RSLC1
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.3,voff=-0.4)
51
c.ca n12 n8 = 1.5e-10
RSLC2
c.cb n15 n14 = 1.1e-10
ISCL
c.cin n6 n8 = 7.0e-11
spe.ebreak n11 n7 n17 n18 = 109.7 GATE
1
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
LGATE
DBREAK
50
-
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
EVTEMP
RGATE + 18 22
9
20
21
11
DBODY
16
MWEAK
6
EBREAK
+
17
18
-
MMED
MSTRO
RLGATE
CIN
DRAIN
2
8
LSOURCE
7
SOURCE
3
RSOURCE
RLSOURCE
i.it n8 n17 = 1
S1A
12
l.lgate n1 n9 = 5.29e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 5.71e-9
14
13
13
8
S1B
CA
res.rlgate n1 n9 = 52.9
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 57.1
S2A
RBREAK
15
17
18
RVTEMP
S2B
13
19
CB
6
8
EGS
-
IT
14
+
+
VBAT
5
8
EDS
-
m.mmed n16 n6 n8 n8 = model=mmedmod, temp=m_temp, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, temp=m_temp, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, temp=m_temp, l=1u, w=1u
+
8
22
RVTHRES
res.rbreak n17 n18 = 1, tc1=1.0e-3,tc2=-8.8e-7
res.rdrain n50 n16 = 0.9, tc1=7.0e-3,tc2=2.0e-5
res.rgate n9 n20 = 3.94
res.rslc1 n5 n51 = 1e-6, tc1=1.0e-3,tc2=9.0e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 0.5, tc1=4.8e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-9.0e-4,tc2=-7.0e-6
res.rvtemp n18 n19 = 1, tc1=-2.1e-3,tc2=1.8e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/15))** 2.5))
}
}
©2004 Fairchild Semiconductor Corporation
FDT461N Rev. A1
FDT461N
PSPICE Thermal Model
th
REV January 2004
FDT461N_JA Junction Ambient
Copper Area= 1sq.in
CTHERM1 Junction c2 3.0e-5
CTHERM2 c2 c3 3.2e-5
CTHERM3 c3 c4 2.0e-4
CTHERM4 c4 c5 9.6e-2
CTHERM5 c5 c6 8.9e-1
CTHERM6 c6 c7 9.1e-1
CTHERM7 c7 c8 9.3e-1
CTHERM8 c8 Ambient 7
RTHERM1
RTHERM2
RTHERM3
SABER Thermal Model
RTHERM4
rtherm.rtherm1 th c2 = 0.5
rtherm.rtherm2 c2 c3 = 6
rtherm.rtherm3 c3 c4 = 9
rtherm.rtherm4 c4 c5 = 10
rtherm.rtherm5 c5 c6 = 11
rtherm.rtherm6 c6 c7 = 12
rtherm.rtherm7 c7 c8 = 13
rtherm.rtherm8 c8 tl = 16
}
CTHERM1
2
RTHERM1 Junction c2 0.5
RTHERM2 c2 c3 6
RTHERM3 c3 c4 9
RTHERM4 c4 c5 10
RTHERM5 c5 c6 11
RTHERM6 c6 c7 12
RTHERM7 c7 c8 13
RTHERM8 c8 Ambient 16
SABER thermal model FDT461N
Copper Area= 1sq.in
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th c2 = 3.0e-5
ctherm.ctherm2 c2 c3 = 3.2e-5
ctherm.ctherm3 c3 c4 = 2.0e-4
ctherm.ctherm4 c4 c5 = 9.6e-2
ctherm.ctherm5 c5 c6 = 8.9e-1
ctherm.ctherm6 c6 c7 = 9.1e-1
ctherm.ctherm7 c7 c8 = 9.3e-1
ctherm.ctherm8 c8 tl = 7
CTHERM2
3
CTHERM3
4
CTHERM4
5
RTHERM5
CTHERM5
6
RTHERM6
CTHERM6
7
CTHERM7
RTHERM7
8
CTHERM8
RTHERM8
tl
©2004 Fairchild Semiconductor Corporation
JUNCTION
AMBIENT
FDT461N Rev. A1
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SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic
TINYOPTO™
TruTranslation™
UHC™
UltraFET
VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY
ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT
CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
2. A critical component is any component of a life
1. Life support devices or systems are devices or
support device or system whose failure to perform can
systems which, (a) are intended for surgical implant into
be reasonably expected to cause the failure of the life
the body, or (b) support or sustain life, or (c) whose
support device or system, or to affect its safety or
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I10
