FDU5N50NZTU
Power MOSFET, N-Channel,
UniFETt II
500 V, 4 A, 1.5 W
UniFET II MOSFET is ON Semiconductor’s high voltage MOSFET
family based on advanced planar stripe and DMOS technology. This
advanced MOSFET family has the smallest on−state resistance among
the planar MOSFET, and also provides superior switching performance
and higher avalanche energy strength. In addition, internal
gate−source ESD diode allows UniFET II MOSFET to withstand over
2 kV HBM surge stress. This device family is suitable for switching
power converter applications such as power factor correction (PFC),
flat panel display (FPD) TV power, ATX and electronic lamp ballasts.
Features
•
•
•
•
•
•
•
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D
G
S
RDS(on) = 1.38 (Typ.) @ VGS = 10 V, ID = 2 A
Low Gate Charge (Typ. 9 nC)
Low Crss (Typ. 4 pF)
100% Avalanche Tested
Improved dv/dt Capability
ESD Improved Capability
These Devices are Pb−Free and are RoHS Compliant
Applications
IPAK3
CASE 369AR
• LCD / LED TV
• Lighting
• Charger / Adapter
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2018
May, 2019 − Rev. 1
1
Publication Order Number:
FDU5N50NZTU/D
FDU5N50NZTU
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
Parameter
VDSS
Drain−to−Source Voltage
VGSS
Gate−to−Source Voltage
ID
Drain Current
Value
Unit
500
V
±25
V
Continuous (TC = 25°C)
4
A
Continuous (TC = 100°C)
2.4
Pulsed (Note 1)
16
A
304
mJ
4
A
IDM
Drain Current
EAS
Single Pulse Avalanche Energy (Note 2)
IAR
Avalanche Current (Note 1)
EAR
Repetitive Avalanche Energy (Note 1)
6.2
mJ
dv/dt
Peak Diode Recovery (Note 3)
10
V/ns
TC = 25°C
62
W
Derate Above 25°C
0.5
W/°C
−55 to +150
°C
300
°C
PD
TJ, TSTG
TL
Power Dissipation
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering Purposes (1/8″ from case for 5 seconds)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Repetitive Rating: Pulse width limited by maximum junction temperature.
2. IAS = 4 A, VDD = 50 V, L = 38 mH, RG = 25 , starting TJ = 25°C.
3. ISD ≤ 4 A, di/dt ≤ 200 A/s, VDD ≤ BVDSS, Starting TJ = 25°C.
THERMAL CHARACTERISTICS
Symbol
Value
Unit
RJC
Thermal Resistance, Junction−to−Case
Parameter
2.0
°C/W
RJA
Thermal Resistance, Junction−to−Ambient
90
PACKAGE MARKING AND ORDERING INFORMATION
Part Number
FDU5N50NZTU
Top Mark
Package
Packing Method
Reel Size
Tape Width
Quantity
FDU5N50NZ
IPAK
Tube
N/A
N/A
75 units
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2
FDU5N50NZTU
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise specified)
Symbol
Parameter
Test Condition
Min
Typ
Max
Drain−to−Source Breakdown Voltage
ID = 250 A, VGS = 0 V, TJ = 25°C
500
BVDSS/TJ
Breakdown Voltage Temperature
Coefficient
ID = 250 A, Referenced to 25°C
IDSS
Zero Gate Voltage Drain Current
VDS = 500 V, VGS = 0 V
1
VDS = 400 V, TC = 125°C
10
VGS = ±25 V, VDS = 0 V
±10
Unit
OFF CHARACTERISTICS
BVDSS
IGSS
Gate−to−Body Leakage Current
V
0.5
V/°C
A
A
ON CHARACTERISTICS
VGS(th)
Gate Threshold Voltage
RDS(on)
Static Drain−to−Source On Resistance
VGS = 10 V, ID = 2 A
1.38
Forward Transconductance
VDS = 20 V, ID = 2 A
3.54
VDS = 25 V, VGS = 0 V, f = 1 MHz
330
440
50
70
gFS
VGS = VDS, ID = 250 A
3.0
5.0
V
1.5
S
DYNAMIC CHARACTERISTICS
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Qg(tot)
VDS = 400 V, ID = 4 A,
VGS = 10 V (Note 4)
Total Gate Charge at 10 V
Qgs
Gate−to−Source Gate Charge
Qgd
Gate−to−Drain “Miller” Charge
pF
4
6
9
12
nC
12
35
ns
2
4
SWITCHING CHARACTERISTICS
VDD = 250 V, ID = 4 A,
VGS = 10 V, RG = 25 (Note 4)
td(on)
Turn−On Delay Time
tr
Turn−On Rise Time
22
55
td(off)
Turn−Off Delay Time
28
65
Turn−Off Fall Time
21
50
tf
DRAIN−SOURCE DIODE CHARACTERISTICS
Maximum Continuous Drain to Source Diode Forward Current
4
ISM
Maximum Pulsed Drain to Source Diode Forward Current
16
VSD
Drain to Source Diode Forward Voltage
VGS = 0 V, ISD = 4 A
1.4
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
VGS = 0 V, ISD = 4 A,
dIF/dt = 100 A/s
IS
A
V
210
ns
1.1
C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Essentially independent of Operating Temperature Typical Characteristics.
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3
FDU5N50NZTU
TYPICAL CHARACTERISTICS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
Figure 3. On−Resistance Variation vs. Drain
Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current and Temperature
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
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4
FDU5N50NZTU
TYPICAL CHARACTERISTICS
Figure 7. Breakdown Voltage Variation vs.
Temperature
Figure 8. On−Resistance Variation vs.
Temperature
Figure 9. Maximum Safe Operating Area vs.
Case Temperature
Figure 10. Maximum Drain Current
P DM
t1
Figure 11. Transient Thermal Response Curve
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5
t2
FDU5N50NZTU
Figure 12. Gate Charge Test Circuit & Waveform
Figure 13. Resistive Switching Test Circuit & Waveforms
Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms
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6
FDU5N50NZTU
Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
UniFET is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK3 (IPAK)
CASE 369AR
ISSUE O
DOCUMENT NUMBER:
DESCRIPTION:
98AON13815G
DPAK3 (IPAK)
DATE 30 SEP 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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