FDV303N

July 2014 FDV303N Digital FET, N-Channel General Description Features These N-Channel enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is tailored to minimize on-state resistance at low gate drive conditions. This device is designed especially for application in battery circuits using either one lithium or three cadmium or NMH cells. It can be used as an inverter or for high-efficiency miniature discrete DC/DC conversion in compact portable electronic devices like cellular phones and pagers. This device has excellent on-state resistance even at gate drive voltages as low as 2.5 volts. 25 V, 0.68 A continuous, 2 A Peak. RDS(ON) = 0.45 Ω @ VGS = 4.5 V RDS(ON) = 0.6 Ω @ VGS= 2.7 V. Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) < 1V. Gate-Source Zener for ESD ruggedness.>6kV Human Body Model Compact industry standard SOT-23 surface mount package. Alternative to TN0200T and TN0201T. SOT-23 SuperSOTTM-8 SuperSOTTM-6 SO-8 SOIC-16 SOT-223 Mark:303 D S G Absolute Maximum Ratings Symbol Parameter VDSS VGSS ID Drain/Output Current TA = 25oC unless other wise noted FDV303N Units Drain-Source Voltage, Power Supply Voltage 25 V Gate-Source Voltage, VIN 8 V 0.68 A - Continuous - Pulsed PD Maximum Power Dissipation TJ,TSTG Operating and Storage Temperature Range ESD Electrostatic Discharge Rating MIL-STD-883D Human Body Model (100pf / 1500 Ohm) 2 0.35 W -55 to 150 °C 6.0 kV 357 °C/W THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient © 1997 Fairchild Semiconductor Corporation FDV303N Rev.D2 Electrical Characteristics (TA = 25 OC unless otherwise noted ) Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA ∆BVDSS/∆TJ Breakdown Voltage Temp. Coefficient ID = 250 µA, Referenced to 25 o C 25 IDSS Zero Gate Voltage Drain Current VDS = 20 V, VGS = 0 V IGSS Gate - Body Leakage Current VGS = 8 V, VDS= 0 V V TJ = 55°C ON CHARACTERISTICS mV / oC 26 1 µA 10 µA 100 nA (Note) ∆VGS(th)/∆TJ Gate Threshold Voltage Temp. Coefficient ID = 250 µA, Referenced to 25 o C VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA RDS(ON) Static Drain-Source On-Resistance VGS = 4.5 V, ID = 0.5 A 0.65 TJ =125°C VGS = 2.7 V, ID = 0.2 A ID(ON) On-State Drain Current VGS = 2.7 V, VDS = 5 V gFS Forward Transconductance VDS = 5 V, ID= 0.5 A mV / oC -2.6 0.8 1 V 0.33 0.45 Ω 0.52 0.8 0.44 0.6 0.5 A 1.45 S 50 pF 28 pF 9 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance SWITCHING CHARACTERISTICS tD(on) Turn - On Delay Time tr Turn - On Rise Time tD(off) Turn - Off Delay Time tf Turn - Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge VDS = 10 V, VGS = 0 V, f = 1.0 MHz (Note) VDD = 6 V, ID = 0.5 A, VGS = 4.5 V, RGEN = 50 Ω VDS = 5 V, ID = 0.5 A, VGS = 4.5 V 3 6 ns 8.5 18 ns 17 30 ns 13 25 ns 1.64 2.3 nC 0.38 nC 0.45 nC DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Drain-Source Diode Forward Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 0.5 A (Note) 0.83 0.3 A 1.2 V Note: Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. FDV303N Rev.D2 Typical Electrical Characteristics 2 VGS = 4.5V 3.5 3.0 2.7 1.2 2.5 R DS(on) , NORMALIZED DRAIN-SOURCE ON-RESISTANCE I D , DRAIN-SOURCE CURRENT (A) 1.5 2.0 0.9 0.6 1.5 0.3 0 VGS = 2.0V 1.5 2.7 0.5 1 1.5 3.5 4.5 2 0 0.2 0.6 0.8 1 1.2 Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. Figure 1. On-Region Characteristics. 1.6 2 ID= 0.5A I D =0.5 A VGS = 4.5 V 1.4 R DS(on) , ON-RESISTANCE (OHM) R DS(ON), NORMALIZED 0.4 I D , DRAIN CURRENT (A) VDS , DRAIN-SOURCE VOLTAGE (V) DRAIN-SOURCE ON-RESISTANCE 3.0 1 0.5 0 2.5 1.2 1 0.8 0.6 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 150 Figure 3. On-Resistance Variation 1.6 1.2 0.8 125°C 25°C 0.4 0 1 1.5 2 2.5 3 3.5 4 VGS , GATE TO SOURCE VOLTAGE (V) 4.5 5 Figure 4. On Resistance Variation with with Temperature. Gate-To- Source Voltage. 1 T = -55°C J 1 25°C IS , REVERSE DRAIN CURRENT (A) ID , DRAIN CURRENT (A) V DS = 5.0V 0.8 125°C 0.6 0.4 0.2 0 0 0.5 1 1.5 2 VGS , GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. 2.5 V GS = 0V TJ = 125°C 0.1 25°C -55°C 0.01 0.001 0.0001 0 0.2 0.4 0.6 0.8 1 1.2 VSD , BODY DIODE FORWARD VOLTAGE (V) Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDV303N Rev.D2 Typical Electrical And Thermal Characteristics 5 V GS , GATE-SOURCE VOLTAGE (V) 150 VDS = 5V I D = 0.5A 100 10V 4 CAPACITANCE (pF) 15V 3 2 Ciss 50 Coss 20 10 f = 1 MHz V GS = 0V C rss 1 0 5 0.1 0 0.4 0.8 1.2 1.6 0.5 2 V DS 1 2 5 10 25 , DRAIN TO SOURCE VOLTAGE (V) Q g , GATE CHARGE (nC) Figure 8. Capacitance Characteristics. Figure 7. Gate Charge Characteristics. 5 5 1m s 10m s 10 0.3 0m s 1s 10 0.1 0.01 0.1 0.2 0.5 s 3 2 DC V GS = 4.5V SINGLE PULSE R θJA =357°C/W TA = 25°C 0.03 SINGLE PULSE R θJA =357° C/W T A = 25°C 4 POWER (W) IT LIM N) (O S RD 1 1 1 2 5 10 20 0 0.001 40 0.01 0.1 1 10 100 300 SINGLE PULSE TIME (SEC) VDS , DRAI N-SOURCE VOLTAGE (V) Figure 9. Maximum Safe Operating Area. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE I D , DRAIN CURRENT (A) 3 Figure 10. Single Pulse Maximum Power Dissipation. 1 0.5 D = 0.5 0.2 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 0.005 R θJA (t) = r(t) * R θJA R θJA = 357 °C/W P(pk) 0.01 t1 Single Pulse 0.002 0.001 0.0001 t2 TJ - TA = P * R θJA(t) Duty Cycle, D = t1 /t2 0.001 0.01 0.1 1 10 100 300 t1 , TIME (sec) Figure 11. Transient Thermal Response Curve. FDV303N Rev.D2 0.95 2.92±0.20 3 1.40 1.30+0.20 -0.15 1 2.20 2 0.60 0.37 (0.29) 0.95 0.20 1.00 A B 1.90 1.90 LAND PATTERN RECOMMENDATION SEE DETAIL A 1.20 MAX 0.10 0.00 (0.93) 0.10 C C 2.40±0.30 NOTES: UNLESS OTHERWISE SPECIFIED GAGE PLANE 0.23 0.08 0.25 0.20 MIN (0.55) SCALE: 2X SEATING PLANE A) REFERENCE JEDEC REGISTRATION TO-236, VARIATION AB, ISSUE H. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE INCLUSIVE OF BURRS, MOLD FLASH AND TIE BAR EXTRUSIONS. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994. E) DRAWING FILE NAME: MA03DREV10 TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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