EcoSPARK 2 N-Channel
Ignition IGBT
335 mJ, 400 V
FGD3440G2-F085V
Features
•
•
•
•
SCIS Energy = 335 mJ at TJ = 25°C
Logic Level Gate Drive
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
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COLLECTOR
Applications
• Automotive Ignition Coil Driver Circuits
• High Current Ignition System
• Coil on Plug Application
GATE
R1
R2
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Value
Unit
BVCER
Collector to Emitter Breakdown
Voltage (IC = 1 mA)
400
V
BVECS
Emitter to Collector Voltage − Reverse
Battery Condition (IC = 10 mA)
28
V
ESCIS25
Self Clamping Inductive Switching
Energy (Note 1)
335
mJ
ESCIS150 Self Clamping Inductive Switching
Energy (Note 2)
195
mJ
4
IC25
Collector Current Continuous
at VGE = 4.0 V, TC = 25°C
26.9
A
IC110
Collector Current Continuous
at VGE = 4.0 V, TC = 110°C
25
A
VGEM
Gate to Emitter Voltage Continuous
±10
V
PD
Power Dissipation Total, TC = 25°C
166
W
Power Dissipation Derating, TC > 25°C
1.1
W/°C
Operating Junction and Storage
Temperature
−40 to +175
°C
TSTG
Storage Junction Temperature Range
−40 to +175
°C
TL
Max. Lead Temperature for Soldering
(Leads at 1.6 mm from case for 10 s)
300
°C
TPKG
Max. Lead Temperature for Soldering
(Package Body for 10 s)
260
°C
ESD
HBM−Electrostatic Discharge Voltage
at 100 pF, 1500 W
4
kV
TJ
EMITTER
1 2
3
DPAK (SINGLE GAUGE)
CASE 369C
MARKING DIAGRAM
AYWW
FGD
3440G2
A
= Assembly Location
Y
= Year
WW
= Work Week
FGD3440G2= Device Code
ORDERING INFORMATION
See detailed ordering and shipping information on page 2
of this data sheet.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Self clamped inductive Switching Energy (ESCIS25) of 335 mJ is based on
the test conditions that is starting TJ = 25°C, L = 3 mHy, ISCIS = 15 A,
VCC = 100 V during inductor charging and VCC = 0 V during time in clamp.
2. Self Clamped inductive Switching Energy (ESCIS150) of 195 mJ is based on
the test conditions that is starting TJ = 150°C, L = 3mHy, ISCIS = 11.4 A,
VCC = 100 V during inductor charging and VCC = 0 V during time in clamp.
© Semiconductor Components Industries, LLC, 2019
October, 2020 − Rev. 3
1
Publication Order Number:
FGD3440G2−F085V/D
FGD3440G2−F085V
THERMAL RESISTANCE RATINGS
Characteristic
Junction−to−Case – Steady State (Drain)
Symbol
Max
Units
RqJC
0.9
°C/W
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BVCER
Collector to Emitter Breakdown Voltage
ICE = 2 mA, VGE = 0 V,
RGE = 1 kW, TJ = −40 to 150°C
370
400
430
V
BVCES
Collector to Emitter Breakdown Voltage
ICE = 10 mA, VGE = 0 V,
RGE = 0, TJ = −40 to 150°C
390
420
450
V
BVECS
Emitter to Collector Breakdown Voltage
ICE = −20 mA, VGE = 0 V, TJ = 25°C
28
−
−
V
BVGES
Gate to Emitter Breakdown Voltage
IGES = ±2 mA
±12
±14
−
V
ICER
Collector to Emitter Leakage Current
VCE = 250 V
RGE = 1 kW
TJ = 25°C
−
−
25
mA
TJ = 150°C
−
−
1
mA
VEC = 24 V
TJ = 25°C
−
−
1
mA
TJ = 150°C
−
−
40
−
120
−
W
10K
−
30K
W
ICE = 6 A, VGE = 4 V, TJ = 25°C
−
1.1
1.2
V
ICE = 10 A, VGE = 4.5 V, TJ = 150°C
−
1.3
1.45
ICE = 15 A, VGE = 4.5 V, TJ = 150°C
−
1.6
1.75
−
24
−
nC
TJ = 25°C
1.3
1.7
2.2
V
TJ = 150°C
0.75
1.2
1.8
VCE = 12 V, ICE = 10 A
−
2.8
−
V
VCE = 14 V, RL = 1 W, VGE = 5 V,
RG = 1 KW, TJ = 25°C
−
1.0
4
ms
−
2.0
7
VCE = 300 V, L = 1 mH, VGE = 5 V,
RG = 1KW, ICE = 6.5 A, TJ = 25°C
−
5.3
10
−
2.3
15
IECS
Emitter to Collector Leakage Current
R1
Series Gate Resistance
R2
Gate to Emitter Resistance
ON CHARACTERISTICS (Note 5)
VCE(SAT)
Collector to Emitter Saturation Voltage
DYNAMIC CHARACTERISTICS
QG(ON)
Gate Charge
ICE = 10 A, VCE = 12 V, VGE = 5 V
VGE(TH)
Gate to Emitter Threshold Voltage
ICE = 1 mA
VCE = VGE
VGEP
Gate to Emitter Plateau Voltage
SWITCHING CHARACTERISTICS
td(ON)R
trR
td(OFF)L
tfL
Current Turn−On Delay Time−Resistive
Current Rise Time−Resistive
Current Turn−Off Delay Time−Inductive
Current Fall Time−Inductive
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
PACKAGE MARKING AND ORDERING INFORMATION
Device Marking
Device
Package
Reel Diameter
Tape Width
Qty†
FGD3440G2
FGD3440G2−F085V
DPAK (Pb−Free)
330 mm
16 mm
2500
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
FGD3440G2−F085V
TYPICAL CHARACTERISTICS
Figure 1. Self Clamped Inductive Switching
Current vs. Time in Clamp
Figure 2. Self Clamped Inductive
Switching Current vs. Inductance
Figure 4. Collector to Emitter On−State Voltage
vs. Junction Temperature
Figure 3. Collector to Emitter On−State Voltage
vs. Junction Temperature
Figure 5. Collector to Emitter On−State Voltage
vs. Collector Current
Figure 6. Collector to Emitter On−State Voltage
vs. Collector Current
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3
FGD3440G2−F085V
TYPICAL CHARACTERISTICS (continued)
Figure 7. Collector to Emitter On−State Voltage
vs. Collector Current
I CE , DC COLLECTOR CURRENT (A)
50
Figure 8. Transfer Characteristics
VGE = 5V
45
40
35
30
25
20
15
10
5
0
25
50
75
100
125
150
175
TC , CASE TEMPERATURE(oC)
Figure 9. DC Collector Current vs. Case
Temperature
Figure 10. Gate Charge
Figure 11. Threshold Voltage vs. Junction
Temperature
Figure 12. Leakage Current vs. Junction
Temperature
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4
FGD3440G2−F085V
TYPICAL CHARACTERISTICS (continued)
Figure 13. Switching Time vs. Junction Temperature
Figure 14. Capacitance vs. Collector to Emitter
Figure 15. Break Down Voltage vs. Series Resistance
Figure 16. IGBT Normalized Transient Thermal Impedance, Junction to Case
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5
FGD3440G2−F085V
TEST CIRCUIT AND WAVEFORMS
Figure 18. tON and tOFF Switching Test Circuit
Figure 17. Inductive Switching Test Circuit
Figure 19. Energy Test Circuit
Figure 20. Energy Waveforms
ECOSPARK is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE F
4
1 2
DATE 21 JUL 2015
3
SCALE 1:1
A
E
b3
B
c2
4
L3
Z
D
1
L4
C
A
2
3
NOTE 7
b2
e
c
SIDE VIEW
b
0.005 (0.13)
TOP VIEW
H
DETAIL A
M
BOTTOM VIEW
C
Z
H
L2
GAUGE
PLANE
C
L
L1
DETAIL A
Z
SEATING
PLANE
BOTTOM VIEW
A1
ALTERNATE
CONSTRUCTIONS
ROTATED 905 CW
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 8:
PIN 1. N/C
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
STYLE 9:
STYLE 10:
PIN 1. ANODE
PIN 1. CATHODE
2. CATHODE
2. ANODE
3. RESISTOR ADJUST
3. CATHODE
4. CATHODE
4. ANODE
SOLDERING FOOTPRINT*
6.20
0.244
2.58
0.102
5.80
0.228
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.028 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.114 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.72
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.90 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
GENERIC
MARKING DIAGRAM*
XXXXXXG
ALYWW
AYWW
XXX
XXXXXG
IC
Discrete
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
6.17
0.243
SCALE 3:1
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
XXXXXX
A
L
Y
WW
G
3.00
0.118
1.60
0.063
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
7. OPTIONAL MOLD FEATURE.
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON10527D
DPAK (SINGLE GAUGE)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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