FIN212ACGFX

FIN212AC 12-Bit Serializer / Deserializer Supporting Cameras and Small Displays Features Data & Control Bits Frequency Capability Interface µController Usage Selectable Edge Rates Standby Current Core Voltage (VDDA/S) I/O Voltage (VDDP) ESD (I/O to GND) Package Ordering Information Description 12-Bit 40MHz Camera or LCD Microcontroller, RGB, YUV m68 & i86 Yes 40MHz); fCKREF=fSTRB Strobe Frequency Relative to CKREF Frequency fCKREF ≠ fSTRB S1=0, S0=1 18 40 S1=1, S0=0 5 14 S1=1, S0=1 10 MHz 28 PLL1=0, PLL0=0 100 PLL1=0, PLL0=1 100 PLL1=1, PLL0=0 50 PLL1=1, PLL0=1 33 /3 % of fCKREF 1 tCPWH CKREF DC T=1/fCKREF 0.2 0.5 0.8 tCPWL CKREF DC T=1/fCKREF 0.2 0.5 0.8 T tCLKT LVCMOS Input Transition Time 20 ns 10 ns tSPWH/L (5) STROBE Pulse Width HIGH/LOW 10-90% 4 T=1/fCKREF T x /14 Setup Time tSTC DP(n) Setup to STROBE tS T C S TR OBE (DIRI=1, f=5MHz) D P [1 : 1 2] ns 2.0 ns tH T C DP(n) Hold to STROBE S TR OBE (DIRI=1, f=5MHz) 2.5 Data Hold Time tHTC T x /14 T D P [1 : 1 2] D ata Serializer AC Electrical Characteristics tTCCD STROBE tRCCD VDD/2 tTCCD Transmitter Clock Input to Clock (6) Output Delay CKSV =0 21a+1.5 DIFF CKS+ CKP 23a+6.5 ns VDD/2 Note: STROBE=CKREF DIRI=1, fCKREF=fSTRB Phase Lock Loop (PLL) AC Electrical Characteristics tTPLLS0 Serializer PLL Stabilization Time 600 μs tTPLLD0 PLL Disable Time Loss of Clock 30.0 μs tTPLLD1 PLL Power-Down Time 20.0 ns CKREF toggling and stable 200 Deserializer AC Electrical Characteristics Symbol Parameter Test Conditions Data Valid tRCOL DP[1:12] Data tRCOP CKP Typ. Max. PWS1 PWS0 fSTRB=fCKREF 0 0 fSTRB=fCKREF 0 1 7a-3 7a+3 fSTRB=.5x fCKREF 1 0 13a-3 13a+3 fSTRB=.5x fCKREF 1 1 17a-3 17a+3 8a-3 8a+3 tPDV CKP Min. 7a-3 Unit 7a+3 ns 75% 50% 50% 25% tPDV tRCOH tRCOL Data Valid to CKP HIGH (Rising Edge STROBE), CL=5pF ns Setup: DIRI= 0, CKSI and DS are valid signals. © 2008 Fairchild Semiconductor Corporation FIN212AC • Rev. 1.1.1 www.fairchildsemi.com 10 µSerDes™ FIN212AC — 12-Bit Serializer / Deserializer Supporting Cameras and Small Displays AC Electrical Characteristics tRFD tRFC Output Rise/Fall Time Data (20% to 80%) Output Rise/Fall Time CKP (20% to 80%) CL=8pF CL=8pF S1=0,S0=1 3 S1=1,S0=0 8 S1=1,S0=1 5 S1=0,S0=1 2 S1=1,S0=0 7 S1=1,S0=1 4 ns ns Notes: 5. 6. Parameter is characterized, but not production tested. The average bit time “a” is a function of the serializer CKREF frequency; a=(1/f)/14. Logic Timing Controls Symbol Parameter Test Conditions t PHL_DIR, tPLH_DIR Propagation Delay DIRI to /DIRO tPLZ, tPHZ Propagation Delay DIRI to DP Min. Typ. Max. Unit DIRI L->H or H->L 17 ns DIRI L->H or H->L 25 ns 25 ns 25 ns Deserializer Disable Time: S0 or S1 LOW to DPTri-State; DIRI=0, t tDISDES DISDES S1 or S0 DP Note: If S0(2) is transitioning, S1(1) must =0 for test to be valid. tDISSER Serializer Disable Time: S0 or S1 LOW to CKP HIGH DIRI=1; S1(0) and S0(1)=H->L © 2008 Fairchild Semiconductor Corporation FIN212AC • Rev. 1.1.1 www.fairchildsemi.com 11 µSerDes™ FIN212AC — 12-Bit Serializer / Deserializer Supporting Cameras and Small Displays AC Electrical Characteristics (Continued) MLP Embossed Tape Dimensions Package A0 ±0.1 B0 ±0.1 D ±0.5 D1 Min. E ±0.1 F ±0.1 K0 ±0.1 P1 Typ. P0 Typ. P2 ±0.5 T Typ. TC ±0/05 W ±0.3 WC Typ. 5x5 5.35 5.35 1.55 1.50 1.75 5.50 1.40 8.00 4.00 2.00 0.30 0.07 12.00 9.30 6x6 5.35 5.35 1.55 1.50 1.75 5.50 1.40 8.00 4.00 2.00 0.30 0.07 12.00 9.30 Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and lateral movement requirements (see sketches A, B, and C). MLP Shipping Reel Dimensions Tape Width Dia A Max. Dim B Min. Dia C +0.5/-0.2 Dia D Min. Dim N Min. Dim W1 +2.0/-0 Dim W2 Dim W3 (LSL-USL) 8 330.0 1.5 13.0 20.2 178.0. 8.4 14.4 7.9 ~ 10.4 12 330.0 1.5 13.0 20.2 178.0. 12.4 18.4 11.9 ~ 15.4 16 330.0 1.5 13.0 20.2 178.0. 16.4 22.4 15.9 ~ 19.4 Figure 8. MLP Tape and Reel © 2008 Fairchild Semiconductor Corporation FIN212AC • Rev. 1.1.1 www.fairchildsemi.com 12 µSerDes™ FIN212AC — 12-Bit Serializer / Deserializer Supporting Cameras and Small Displays Tape and Reel Specifications BGA Embossed Tape Dimensions Package A0 ±0.1 B0 ±0.1 D ±0.5 D1 Min. E ±0.1 F ±0.1 K0 ±0.1 P1 Typ. P0 Typ. P2 ±0.5 T Typ. TC ±0/05 W ±0.3 WC Typ. 3.5 x 4.5 3.85 4.80 1.55 1.50 1.75 5.50 1.10 8.00 4.00 2.00 0.30 0.07 12.00 9.3 Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and lateral movement requirements (see sketches A, B, and C). BGA Shipping Reel Dimensions Tape Width Dia A Max. Dim B Min. Dia C +0.5/-0.2 Dia D Min. Dim N Min. Dim W1 +2.0/-0 Dim W2 Dim W3 (LSL-USL) 8 330.0 1.5 13.0 20.2 178.0. 8.4 14.4 7.9 ~ 10.4 12 330.0 1.5 13.0 20.2 178.0. 12.4 18.4 11.9 ~ 15.4 16 330.0 1.5 13.0 20.2 178.0. 16.4 22.4 15.9 ~ 19.4 Figure 9. BGA Tape and Reel © 2008 Fairchild Semiconductor Corporation FIN212AC • Rev. 1.1.1 www.fairchildsemi.com 13 µSerDes™ FIN212AC — 12-Bit Serializer / Deserializer Supporting Cameras and Small Displays Tape and Reel Specifications (Continued) µSerDes™ FIN212AC — 12-Bit Serializer / Deserializer Supporting Cameras and Small Displays Physical Dimensions 0.15 C 5.00 B A 5.00 (0.76) (0.25 ) PIN #1 IDENT 5.38 MIN 0.15 C 3.37 MAX 3.86 MIN 0.80 MAX 0.10 C 0.08 C 0.20MIN X4 (0.20) 0.05 0.00 0.28 MAX C X40 SEATING PLANE 0.50TYP E 3.70 3.50 0.45 0.35 PIN #1 IDENT PIN #1 ID 0.50 3.70 3.50 (DATUM B) PIN #1 ID (DATUM A) 0.18-0.30 0.10 0.05 0.50 C A B C NOTES: A. CONFORMS TO JEDEC REGISTRATION MO-220, VARIATION WHHD-4. THIS PACKAGE IS ALSO FOOTPRINT COMPATIBLE WITH WHHD-5. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994. D. LAND PATTERN PER IPC SM-782. E. WIDTH REDUCED TO AVOID SOLDER BRIDGING. F. DIMENSIONS ARE NOT INCLUSIVE OF BURRS, MOLD FLASH, OR TIE BAR PROTRUSIONS. G. DRAWING FILENAME: MKT-MLP32Arev3. Figure 10. 32-Lead, Molded Leadless Package (MLP) Order Number FIN212ACMLX Operating Temperature Range Package Description Packing Method -30 to 70°C 32-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 5mm Square Tape & Reel Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2008 Fairchild Semiconductor Corporation FIN212AC • Rev. 1.1.1 www.fairchildsemi.com 14 µSerDes™ FIN212AC — 12-Bit Serializer / Deserializer Supporting Cameras and Small Displays Physical Dimensions (Continued) Figure 11. 42-Ball, Ball Grid Array (BGA) Package Order Number Operating Temperature Range Package Description Packing Method FIN212ACGFX -30 to 70°C 42-Ball Ultra Small-Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5 x 4.5mm Wide, 0.5mm Ball Pitch Tape & Reel Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2008 Fairchild Semiconductor Corporation FIN212AC • Rev. 1.1.1 www.fairchildsemi.com 15 µSerDes™ FIN212AC — 12-Bit Serializer / Deserializer Supporting Cameras and Small Displays www.fairchildsemi.com © 2008 Fairchild Semiconductor Corporation FIN212AC • Rev. 1.1.1 16