FIN3386MTDX

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This literature is subject to all applicable copyright laws and is not for resale in any manner. FIN3385 / FIN3386 Low-Voltage, 28-Bit, Flat-Panel Display Link Serializer / Deserializer Features Description          The FIN3385 and FIN3386 transform 28-bit wide parallel Low-Voltage TTL (LVTTL) data into four serial Low Voltage Differential Signaling (LVDS) data streams. A phase-locked transmit clock is transmitted in parallel with the data stream over a separate LVDS link. Every cycle of transmit clock, 28-bits of input LVTTL data are sampled and transmitted. Operation -40°C to +85°C Low Power Consumption 20MHz to 85MHz Shift Clock Support ±1V Common-Mode Range around 1.2V Narrow Bus Reduces Cable Size and Cost High Throughput (up to 2.38Gbps) Internal PLL with No External Component Compatible with TIA/EIA-644 Specification 56-Lead, TSSOP Package The FIN3386 receives and converts the 4/3 serial LVDS data streams back into 28/21 bits of LVTTL data, acting as the deserializer. For the FIN3385, at a transmit clock frequency of 85MHz, 28-bits of LVTTL data are transmitted at a rate of 595Mbps per LVDS channel. This pair solves EMI and cable size problems associated with wide and high-speed TTL interfaces. Ordering Information Part Number Operating Temperature Range Package Packing Method -40 to +85°C 56-Lead Thin-Shrink Small-Outline Package (TSSOP), JEDEC MO-153,6.1mm Wide Tape and Reel FIN3385MTDX FIN3386MTDX © 2003 Fairchild Semiconductor Corporation FIN3385 / FIN3386 • Rev. 1.0.6 www.fairchildsemi.com FIN3385 / FIN3386 — Low-Voltage, 28-Bit Flat Panel Display Link Serializer / Deserializer March 2012 Figure 1. FIN3385 Transmitter Functional Diagram FIN3385 / FIN3386 — Low-Voltage, 28-Bit Flat Panel Display Link Serializer / Deserializer Block Diagrams Figure 2. FIN3386 Receiver Functional Diagram © 2003 Fairchild Semiconductor Corporation FIN3385 / FIN3386 • Rev. 1.0.6 www.fairchildsemi.com 2 Figure 3. FIN3385 (28:4 Transmitter) Pin Assignments Pin Definitions Pin Names I/O Types Number of Pins TxIn I 28/21 Description of Signals LVTTL Level Input TxCLKIn I 1 TxOut+ O 4/3 Positive LVDS Differential Data Output LVTTL Level Clock Input, the rising edge is for data strobe TxOut- O 4/3 Negative LVDS Differential Data Output TxCLKOut+ O 1 Positive LVDS Differential Clock Output TxCLKOut- O 1 Negative LVDS Differential Clock Output R_FB I 1 Rising Edge Data Strobe: Assert HIGH (VCC) Falling Edge Data Strobe: Assert LOW (Ground) /PwrDn I 1 LVTTL Level Power-Down Input Assertion (LOW) puts the outputs in High-Impedance state PLL VCC I 1 Power Supply Pin for PLL PLL GND I 2 Ground Pins for PLL LVDS VCC I 1 Power Supply Pin for LVDS Output LVDS GND I 3 Ground Pins for LVDS Output VCC I 3 Power Supply Pins for LVTTL Input GND I 5 Ground Pin for LVTTL Input © 2003 Fairchild Semiconductor Corporation FIN3385 / FIN3386 • Rev. 1.0.6 FIN3385 / FIN3386 — Low-Voltage, 28-Bit Flat Panel Display Link Serializer / Deserializer Transmitter Pin Configuration www.fairchildsemi.com 3 FIN3385 / FIN3386 — Low-Voltage, 28-Bit Flat Panel Display Link Serializer / Deserializer Receiver Pin Configuration Figure 4. FIN3386 (28:4 Receiver) Pin Assignments Pin Definitions Pin Names I/O Types Number of Pins RxIn I 4/3 Negative LVDS Differential Data Output RxIn+ I 4/3 Positive LVDS Differential Data Output RxCLKIn- I 1 Negative LVDS Differential Data Input Positive LVDS Differential Clock Input RxCLKIn+ I 1 RxOut O 28/21 RxCLKOut- O 1 Description of Signals LVTTL Level Data Output, goes HIGH for /PwrDn LOW LVTTL Clock Output /PwrDn I 1 LVTTL Level Input. Refer to Table 2 PLL VCC I 1 Power Supply Pin for PLL PLL GND I 2 Ground Pins for PLL LVDS VCC I 1 Power Supply Pin for LVDS Input LVDS GND I 3 Ground Pins for LVDS Input VCC I 4 Power Supply for LVTTL Output GND I 5 Ground Pins for LVTTL Output © 2003 Fairchild Semiconductor Corporation FIN3385 / FIN3386 • Rev. 1.0.6 www.fairchildsemi.com 4 Table 1. Input / Output Truth Table Inputs Outputs (1) TxIn TxCLKIn /PwrDn Active Active Active LOW / HIGH / High Impedance TxOut± TxCLKOut± HIGH LOW / HIGH LOW / HIGH HIGH LOW / HIGH Don’t Care(2) Floating Active HIGH LOW LOW / HIGH Floating Floating HIGH LOW Don’t Care(2) Don’t Care Don’t Care LOW High Impedance High Impedance Notes: 1. The outputs of the transmitter or receiver remain in a high-impedance state until VCC reaches 2V. 2. TxCLKOut± settles at a free-running frequency when the part is powered up, /PwrDn is HIGH, and the TxCLKIn is a steady logic level (LOW / HIGH / High-Impedance). Power-Up / Power-Down Operation Truth Tables The outputs of the transmitter remain in the High-Impedance state until the power supply reaches 2V. Table 2 shows the operation of the transmitter during power-up and power-down and operation of the /PwrDn pin. Table 2. Transmitter Power-Up / Power-Down Operation Truth Table VCC 2V >2V TxIN Don’t Care Don’t Care Active TxOUT High Impedance High Impedance Active TxCLKIn Don’t Care Don’t Care Active TxCLKOut± High Impedance High Impedance Active /PwrDn LOW LOW HIGH Table 3. Receiver Power-Up / Power-Down Operation Truth Table /PwrDn RxIn± Don’t Care RxOut High Impedance Don’t Care Active LOW LOW/HIGH RxCLKIn± Don’t Care Don’t Care RxCLKOut High Impedance /PwrDn VCC Active Note 3 Note 3 Last Valid State HIGH Last Valid State Active Note 3 Note 3 Note 3 Note 4 Active Note 4 Note 4 Note 4 LOW LOW HIGH HIGH HIGH HIGH