FM27C512Q90

FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM General Description The FM27C512 is one member of a high density EPROM Family which range in densities up to 4 Megabit. The FM27C512 is a high performance 512K UV Erasable Electrically Programmable Read Only Memory (EPROM). It is manufactured using Fairchild’s proprietary CMOS AMG™ EPROM technology for an excellent combination of speed and economy while providing excellent reliability. Features ■ High performance CMOS — 90, 120, 150 ns access time ■ Fast turn-off for microprocessor compatibility The FM27C512 provides microprocessor-based systems storage capacity for portions of operating system and application software. Its 90 ns access time provides no wait-state operation with high-performance CPUs. The FM27C512 offers a single chip solution for the code storage requirements of 100% firmwarebased equipment. Frequently-used software routines are quickly executed from EPROM storage, greatly enhancing system utility. ■ Manufacturers identification code ■ JEDEC standard pin configuration — 32-pin PLCC package — 28-pin CERDIP package The FM27C512 is configured in the standard JEDEC EPROM pinout which provides an easy upgrade path for systems which are currently using standard EPROMs. Block Diagram Data Outputs O0 - O7 VCC GND VPP OE CE/PGM Output Enable and Chip Enable Logic Output Buffers .. Y Decoder 524,288-Bit Cell Matrix ....... A0 - A15 Address Inputs X Decoder DS800035-1 AMG is a trademark of WSI, Inc. © 2001 Fairchild Semiconductor Corporation FM27C512 Rev. A 1 www.fairchildsemi.com FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM May 2001 27C040 27C010 27C256 A15 A15 VPP A12 A12 A12 A7 A7 A7 A6 A6 A6 A5 A5 A5 A4 A4 A4 A3 A3 A3 A2 A2 A2 A1 A1 A1 A0 A0 A0 O0 O0 O0 O1 O1 O1 O2 O2 O2 GND GND GND 27C256 27C010 27C040 DIP FM27C512 XX/VPP XX/VPP A16 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VCC VCC A14 A13 A8 A9 A11 OE/VPP A10 VCC CE/PGM O7 O6 O5 O4 O3 XX/PGM XX VCC A18 A17 A14 A13 A14 A14 A13 A13 A8 A9 A8 A9 A8 A9 A11 A11 A11 OE A10 OE A10 OE A10 CE/PGM CE CE/PGM O7 O6 O7 O6 O7 O6 O5 O5 O5 O4 O3 O4 O3 O4 O3 DS800035-2 Compatible EPROM pin configurations are shown in the blocks adjacement to the FM27C512 pins. Commercial Temp Range (0°C to +70°C) Pin Names Access Time (ns) A0–A15 Addresses FM27C512 Q, V 90 90 CE/PGM Chip Enable/Program FM27C512 Q, V 120 120 OE FM27C512 Q, V 150 150 O0–O7 Parameter/Order Number Output Enable Outputs NC Don’t Care (During Read) Industrial Temp Range (-40°C to +85°C) PLCC Access Time (ns) FM27C512 QE, VE 90 90 FM27C512 QE, VE 120 120 FM27C512 QE, VE 150 150 A7 A12 A15 NC VCC A14 A13 Parameter/Order Number 4 A6 A5 A4 A3 A2 A1 A0 NC O0 Q = Quartz-Windowed Ceramic DIP Package V = PLCC Package • All packages conform to the JEDEC standard. • All versions are guaranteed to function for slower speeds. 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 5 6 7 8 9 10 11 12 13 A8 A9 A11 NC OE/VPP A10 CE/PGM O7 O8 O1 O2 GND NC O3 O4 O5 14 15 16 17 18 19 20 DS800035-3 2 FM27C512 Rev. A www.fairchildsemi.com FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM Connection Diagrams Storage Temperature ESD Protection (MIL Std. 883, Method 3015.2) -65°C to +150°C All Input Voltages Except A9 with Respect to Ground VPP and A9 with Respect to Ground All Output Voltages with Respect to Ground VCC + 1.0V to GND -0.6V -0.6V to +7V Operating Range -0.7V to +14V Range VCC Supply Voltage with Respect to Ground >2000V -0.6V to +7V Temperature VCC Tolerance Commercial 0°C to +70°C +5V ±10% Industrial -40°C to +85°C +5V ±10% Read Operation DC Electrical Characteristics Symbol Parameter Test Conditions Min Max Units VIL Input Low Level -0.5 0.8 V VIH Input High Level 2.0 VCC +1 V VOL Output Low Voltage 0.4 V VOH Output High Voltage IOH = -2.5 mA ISB1 VCC Standby Current (CMOS) CE = VCC ±0.3V 100 µA ISB2 VCC Standby Current CE = VIH 1 mA ICC1 VCC Active Current CE = OE = VIL 40 mA ICC2 VCC Active Current CMOS Inputs CE = GND, f = 5 MHz Inputs = VCC or GND, I/O = 0 mA C, E Temp Ranges 35 mA IPP VPP Supply Current VPP = VCC 10 µA VPP VPP Read Voltage VCC - 0.7 VCC V ILI Input Load Current VIN = 5.5V or GND -1 1 µA ILO Output Leakage Current VOUT = 5.5V or GND -10 10 µA IOL = 2.1 mA 3.5 V f = 5 MHz AC Electrical Characteristics Symbol Parameter 90 Min Max Min 120 Max 150 Min Units Max tACC Address to Output Delay 90 120 150 tCE CE to Output Delay 90 120 150 tOE OE to Output Delay 40 50 50 tDF Output Disable to Output Float 35 25 45 tOH Output Hold from Addresses, CE or OE, Whichever Occurred First 0 3 FM27C512 Rev. A 0 ns 0 www.fairchildsemi.com FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM Absolute Maximum Ratings (Note 1) FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM Capacitance TA = +25°C, f = 1 MHz (Note 2) Symbol Parameter Conditions Typ Max Units CIN1 Input Capacitance except OE/VPP VIN = 0V 6 12 pF COUT Output Capacitance VOUT = 0V 9 12 pF CIN2 OE/VPP Input Capacitance VIN = 0V 20 25 pF AC Test Conditions Output Load 1 TTL Gate and CL = 100 pF (Note 8) ≤5 ns Input Rise and Fall Times Input Pulse Levels 0.45V to 2.4V Timing Measurement Reference Level (Note 9) Inputs Outputs 0.8V and 2V 0.8V and 2V AC Waveforms (Notes 6, 7) ADDRESS 2V 0.8V CE 2V 0.8V Address Valid t CF (Note 4, 5) OE OUTPUT t CE 2V 0.8V 2V t OE t DF (Note 3) (Note 4, 5) Hi-Z 0.8V Hi-Z Valid Output t ACC t OH (Note 3) DS800035-4 Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: This parameter is only sampled and is not 100% tested. Note 3: OE may be delayed up to tACC –tOE after the falling edge of CE without impacting tACC. Note 4: The tDF and tCF compare level is determined as follows: High to TRI-STATE, the measured VOH1 (DC) - 0.10V; Low to TRI-STATE, the measured VOL1 (DC) + 0.10V. Note 5: TRI-STATE may be attained using OE or CE . Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device between VCC and GND. Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage. Note 8: 1 TTL Gate: IOL = 1.6 mA, IOH = -400 µA. CL: 100 pF includes fixture capacitance. Note 9: Inputs and outputs can undershoot to -2.0V for 20 ns Max. 4 FM27C512 Rev. A www.fairchildsemi.com Symbol Parameter Conditions Min Typ Max Units tAS Address Setup Time 1 µs tOES OE Setup Time 1 µs tDS Data Setup Time 1 µs tVCS VCC Setup Time 1 µs tAH Address Hold Time 0 µs tDH Data Hold Time 1 µs tCF Chip Enable to Output Float Delay tPW Program Pulse Width OE = VIL 45 0 tOEH OE Hold Time 1 tDV Data Valid from CE tPRT OE Pulse Rise Time during Programming 50 ns tVR VPP Recovery Time 1 µs IPP VPP Supply Current during Programming Pulse ICC VCC Supply Current TR Temperature Ambient 20 VCC Power Supply Voltage VPP Programming Supply Voltage 50 60 ns 105 µs µs OE = VIL 250 CE = VIL OE = VPP ns 30 mA 50 mA 25 30 °C 6.25 6.5 6.75 V 12.5 12.75 13 V 0 0.45 tFR Input Rise, Fall Time VIL Input Low Voltage VIH Input High Voltage 2.4 tIN Input Timing Reference Voltage 0.8 2 V Output Timing Reference Voltage 0.8 2 V tOUT 5 ns 4 V V Programming Waveforms Program Addresses 2.0V 0.8V Program Verify Address N t AS 2.0V Data t DS OE/VPP Hi-Z Data In Stable ADD N 0.8V 2.0V t DH 0.8V Data Out Valid ADD N t DV t CF 12.75V 0.8V tPRT t AH t OES t PW t OEH t VR t VPS CE/PGM t VCS VCC 6.25V DS800035-5 Note 10: Fairchild’s standard product warranty applies to devices programmed to specifications described herein. Note 11: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with voltage applied to VPP or VCC. Note 12: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across VCC to GND to suppress spurious voltage transients which may damage the device. 5 FM27C512 Rev. A www.fairchildsemi.com FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM Programming Characteristics (Note 10) and (Note 11) FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM Turbo Programming Algorithm Flow Chart VCC = 6.5V VPP = 12.75V n=0 ADDRESS = FIRST LOCATION PROGRAM ONE 50µs PULSE INCREMENT n NO DEVICE FAILED YES n = 10? FAIL VERIFY BYTE PASS LAST ADDRESS ? NO INCREMENT ADDRESS n=0 YES ADDRESS = FIRST LOCATION VERIFY BYTE FAIL PASS INCREMENT ADDRESS NO PROGRAM ONE 50 µs PULSE LAST ADDRESS ? YES CHECK ALL BYTES 1ST: VCC = VPP = 6.0V 2ND: VCC = VPP = 4.3V Note: The standard National Semiconductor algorithm may also be used but it will take longer programming time. DS800035-6 FIGURE 1. 6 FM27C512 Rev. A www.fairchildsemi.com The EPROM is in the programming mode when the OE/VPP is at 12.75V. It is required that at least a 0.1 µF capacitor be placed across VCC to ground to suppress spurious voltage transients which may damage the device. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. DEVICE OPERATION The six modes of operation of the EPROM are listed in Table1. It should be noted that all inputs for the six modes are at TTL levels. The power supplies required are VCC and OE/VPP. The OE/VPP power supply must be at 12.75V during the three programming modes, and must be at 5V in the other three modes. The VCC power supply must be at 6.5V during the three programming modes, and at 5V in the other three modes. When the address and data are stable, an active low, TTL program pulse is applied to the CE/PGM input. A program pulse must be applied at each address location to be programmed. The EPROM is programmed with the Turbo Programming Algorithm shown in Figure 1. Each Address is programmed with a series of 50 µs pulses until it verifies good, up to a maximum of 10 pulses. Most memory cells will program with a single 50 µs pulse. (The standard National Semiconductor Algorithm may also be used but it will have longer programming time.) Read Mode The EPROM has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE/PGM) is the power control and should be used for device selection. Output Enable (OE/VPP) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tACC – tOE. The EPROM must not be programmed with a DC signal applied to the CE/PGM input. Programming multiple EPROM in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. Like inputs of the parallel EPROM may be connected together when they are programmed with the same data. A low level TTL pulse applied to the CE/PGM input programs the paralleled EPROM. Standby Mode The EPROM has a standby mode which reduces the active power dissipation by over 99%, from 220 mW to 0.55 mW. The EPROM is placed in the standby mode by applying a CMOS high signal to the CE/PGM input. When in standby mode, the outputs are in a high impedance state, independent of the OE input. Program Inhibit Programming multiple EPROMs in parallel with different data is also easily accomplished. Except for CE/PGM all like inputs (including OE/VPP) of the parallel EPROMs may be common. A TTL low level program pulse applied to an EPROM’s CE/PGM input with OE/VPP at 12.75V will program that EPROM. A TTL high level CE/PGM input inhibits the other EPROMs from being programmed. Output Disable The EPROM is placed in output disable by applying a TTL high signal to the OE input. When in output disable all circuitry is enabled, except the outputs are in a high impedance state (TRISTATE). Program Verify Output OR-Typing A verify should be performed on the programmed bits to determine whether they were correctly programmed. The verify is accomplished with OE/VPP and CE at VIL. Data should be verified TDV after the falling edge of CE. Because the EPROM is usually used in larger memory arrays, Fairchild has provided a 2-line control function that accommodates this use of multiple memory connections. The 2-line control function allows for: AFTER PROGRAMMING 1. the lowest possible memory power dissipation, and Opaque labels should be placed over the EPROM window to prevent unintentional erasure. Covering the window will also prevent temporary functional failure due to the generation of photo currents. 2. complete assurance that output bus contention will not occur. To most efficiently use these two control lines, it is recommended that CE/PGM be decoded and used as the primary device selecting function, while OE/VPP be made a common connection to all devices in the array and connected to the READ line from the system control bus. MANUFACTURER’S IDENTIFICATION CODE The EPROM has a manufacturer’s identification code to aid in programming. When the device is inserted in an EPROM programmer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. This automatic programming control is only possible with programmers which have the capability of reading the code. This assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. Programming The Manufacturer’s Identification code, shown in Table 2, specifically identifies the manufacturer and device type. The code for FM27C512 is “8F85”, where “8F” designates that it is made by Fairchild Semiconductor, and “85” designates a 512K part. CAUTION: Exceeding 14V on pin 22 (OE/VPP) will damage the EPROM. Initially, and after each erasure, all bits of the EPROM are in the “1’s” state. Data is introduced by selectively programming “0’s” into the desired bit locations. Although only “0’s” will be programmed, both “1’s” and “0’s” can be presented in the data word. The only way to change a “0” to a “1” is by ultraviolet light erasure. The code is accessed by applying 12V ±0.5V to address pin A9. Addresses A1–A8, A10–A16, and all control pins 7 FM27C512 Rev. A www.fairchildsemi.com FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM Functional Description are held at VIL. Address pin A0 is held at VIL for the manufacturer’s code, and held at VIH for the device code. The code is read on the eight data pins, O0 –O 7 . Proper code access is only guaranteed at 25°C ±5°C. Lamps lose intensity as they age. When a lamp is changed, the distance has changed, or the lamp has aged, the system should be checked to make certain full erasure is occurring. Incomplete erasure will cause symptoms that can be misleading. Programmers, components, and even system designs have been erroneously suspected when incomplete erasure was the problem. ERASURE CHARACTERISTICS SYSTEM CONSIDERATION The erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (Å). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000Å–4000Å range. The power switching characteristics of EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. The associated VCC transient voltage peaks can be suppressed by properly selected decoupling capacitors. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device between VCC and GND. This should be a high frequency capacitor of low inherent inductance. In addition, at least a 4.7 µF bulk electrolytic capacitor should be used between VCC and GND for each eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the PC board traces. The recommended erasure procedure for the EPROM is exposure to short wave ultraviolet light which has a wavelength of 2537Å. The integrated dose (i.e., UV intensity x exposure time) for erasure should be minimum of 15W-sec/cm2. The EPROM should be placed within 1 inch of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure An erasure system should be calibrated periodically. The distance from lamp to device should be maintained at one inch. The erasure time increases as the square of the distance from the lamp (if distance is doubled the erasure time increases by factor of 4). Mode Selection The modes of operation of the FM27C512 are listed in Table 1. A single 5V power supply is required in the read mode. All inputs are TTL levels excepts for VPP and A9 for device signature. TABLE 1. Mode Selection Pins CE/PGM OE/VPP VCC Outputs VIL VIL 5.0V DOUT X (Note 13) VIH 5.0V High Z Standby VIH X 5.0V High Z Programming VIL 12.75V 6.25V DIN Program Verify VIL VIL 6.25V DOUT Program Inhibit VIH 12.75V 6.25V High Z Mode Read Output Disable Note 13: X can be VIL or VIH. TABLE 2. Manufacturer’s Identification Code Pins A0 (10) A9 (24) 07 (19) 06 (18) 05 (17) 04 (16) 03 (15) 02 (13) 01 (12) 00 (11) Hex Data Manufacturer Code VIL 12V 1 0 0 0 1 1 1 1 8F Device Code VIH 12V 1 0 0 0 0 1 0 1 85 8 FM27C512 Rev. A www.fairchildsemi.com FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM Functional Description (Continued) FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM Physical Dimensions inches (millimeters) unless otherwise noted 1.465 MAX [37.211] 28 15 R 0.025 [0.635] 0.515-0.530 [13.081-13.462] R 0.030-0.055 [0.762-1.397] TYP 1 14 0.290-0.310 [7.366-7.874] U.V. WINDOW 0.050-0.060 [1.270-1.524] TYP GLASS SEALANT 0.590-0.620 [14.99-15.75] 0.180 [4.572] MAX 0.225 [5.715] MAX TYP 0.125 [3.175] MIN TYP 0.060-0.100 [1.524-2.540] TYP 0.090-0.110 [2.286-2.794] TYP 0.010 [0.254] MAX 86°-94° TYP 0.015-0.021 [0.381-0.533] TYP 0.033-0.045 [0.838-1.143] TYP 0.015-0.060 [0.381-1.524] TYP 90°-100° TYP 0.008-0.012 [0.203-0.305] TYP +0.025 0.685 -0.060 +0.635 [17.399 -1.524 ] UV Window Cavity Dual-In-Line Cerdip Package (JQ) Order Number FM27C512Q Package Number J28CQ 9 FM27C512 Rev. A www.fairchildsemi.com FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM Physical Dimensions inches (millimeters) unless otherwise noted 0.485-0.495 [12.32-12.57] 0.106-0.112 [2.69-2.84] 0.007[0.18] S B D-E S 0.449-0.453 [11.40-11.51] -H- Base Plane 0.023-0.029 [0.58-0.74] 0.015 [0.38] Min Typ -A0.045 [1.143] 60 ° 0.007[0.18] S B D-E S 0.002[0.05] S B 0.000-0.010 [0.00-0.25] Polished Optional 1 0.490-0530 [12.45-13.46] 0.400 -D4 ( [10.16] ) 30 0.541-0.545 [13.74-13-84] 29 5 0.549-0.553 [13.94-14.05] 0.015[0.38] S C D-E, F-G S -G- -B0.585-0.595 [14.86-15.11] 0.013-0.021 TYP [0.33-0.53] -FSee detail A -J13 14 20 -E- 0.002[0.05] S A 0.007[0.18] S 0.007[0.18] S A F-G S A F-G S 0.118-0.129 [3.00-3.28] 0.010[0.25] L 0.007[0.18] M 21 B A D-E, F-G S B 0.042-0.048 45°X [1.07-1.22] 0.123-0.140 [3.12-3.56] 0.050 ;; 0.025 [0.64] Min B 0.007[0.18] S 0.019-0.025 [0.48-0.64] H D-E, F-G S D-E, F-G S -C0.004[0.10] 0.020 [0.51] 0.005 Max [0.13] 0.0100 [0.254] 0.045 [1.14] 0.025 [0.64] Min Detail A Typical Rotated 90° 0.021-0.027 [0.53-0.69] R 0.030-0.040 [0.76-1.02] 0.065-0.071 [1.65-1.80] 0.053-0.059 [1.65-1.80] 0.031-0.037 [0.79-0.94] 0.006-0.012 [0.15-0.30] 0.026-0.032 Typ [0.66-0.81] C 0.078-0.095 [1.98-2.41] 0.027-0.033 [0.69-0.84] Section B-B Typical 32-Lead Plastic Leaded Chip Carrier (PLCC) Order Number FM27C512V Package Number VA32A Life Support Policy Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Fairchild Semiconductor Europe Fax: +44 (0) 1793-856858 Deutsch Tel: +49 (0) 8141-6102-0 English Tel: +44 (0) 1793-856856 Français Tel: +33 (0) 1-6930-3696 Italiano Tel: +39 (0) 2-249111-1 Fairchild Semiconductor Hong Kong 8/F, Room 808, Empire Centre 68 Mody Road, Tsimshatsui East Kowloon. Hong Kong Tel; +852-2722-8338 Fax: +852-2722-8383 Fairchild Semiconductor Japan Ltd. 4F, Natsume Bldg. 2-18-6, Yushima, Bunkyo-ku Tokyo, 113-0034 Japan Tel: 81-3-3818-8840 Fax: 81-3-3818-8841 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 10 FM27C512 Rev. A www.fairchildsemi.com