FMS3110 / FMS3115
Triple Video D/A Converters, 3x10-Bit, 150Ms/s
Features
Description
FMS3110 / FMS3115 products are low-cost, triple D/A
converters tailored for graphics and video applications
where speed is critical. Two speed grades are available:
10-bit Resolution
150 Megapixels per Second
± 0.1% Linearity Error
/SYNC and /BLANK Controls
1.0VPP Video into 37.5Ω or 75Ω Load
Internal Bandgap Voltage Reference
Double-buffered Data for Low Distortion
TTL-compatible Inputs
Low Glitch Energy
Single +5V Power Supply
Few external components are required: a current
reference resistor, current output load resistors, and
decoupling capacitors.
Applications
FMS3110-100Ms/s
FMS3115-150Ms/s
TTL-level inputs are converted to analog current outputs
that can drive 25–37.5Ω loads corresponding to doubly
terminated 50–75Ω loads. A sync current following
/SYNC input timing is added to the IOG output. /BLANK
overrides RGB inputs, setting IOG, IOB, and IOR currents
to zero when /BLANK = L. Although appropriate for
many applications, the internal 1.235V reference
voltage can be overridden by the VREF input.
Video Signal Conversion
-RGB
-YCBCR
-Composite, Y, C
Package is a 48-lead LQFP. Fabrication technology is
CMOS. Performance is guaranteed from 0 to 70°C.
SYNC
/SYNC
/BLANK
Multimedia Systems
Image Processing
True-color Graphics Systems: 1 Billion Colors
G9-0
Broadcast Television Equipment
High-Definition Television (HDTV) Equipment
B9-0
Direct Digital Synthesis
R9-0
10
10-bit D/A
Converter
IOG
10
10-bit D/A
Converter
IOB
10
10-bit D/A
Converter
IOR
CLOCK
COMP
RREF
VREF
+1.235
VREF
Figure 1. Block Diagram
Ordering Information
Part
Numbers
Conversion
Operating
Rate
Temperature Range
Screening
Package
FMS3110KRC
100Ms/s
0 to 70°C
Commercial
48-Contact Leadless Quad Flat Package
FMS3115KRC
150Ms/s
0 to 70°C
Commercial
48-Contact Leadless Quad Flat Package
All packages are lead free per JEDEC: J-STD-020B standard.
© 2000 Fairchild Semiconductor Corporation
FMS3110 / FMS3115 • Rev. 1.0.8
www.fairchildsemi.com
FMS3110 / FMS3115 — Triple Video D/A Converters, 3x10 Bit, 150Ms/s
January 2008
G0
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
NC
48
47
46
45
44
43
42
41
40
39
38
37
1
2
3
4
5
6
7
8
9
10
11
12
LQFP
FMS3110/3115
NC
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
NC
13
14
15
16
17
18
19
20
21
22
23
24
G1
G2
G3
G4
G5
G6
G7
G8
G9
/BLANK
/SYNC
VDD
Figure 2. Pin Assignments
© 2000 Fairchild Semiconductor Corporation
FMS3110 / FMS3115 • Rev. 1.0.8
36
35
34
33
32
31
30
29
28
27
26
25
RREF
VREF
COMP
IOR
IOG
OVDD
VDD
IOB
GND
GND
CLOCK
NC
FMS3110 / FMS3115 — Triple Video D/A Converters, 3x10 Bit, Ms/s
Pin Configuration
www.fairchildsemi.com
2
Name
Pin #
Value
Description
Clock / Pixel I/O
CLK
26
TTL
Clock Input. The clock input is TTL-compatible and all pixel data is registered on the
rising edge of CLK. It is recommended that CLK be driven by a dedicated TTL buffer
to avoid reflection-induced jitter, overshoot, and undershoot.
R9-0
47-37
TTL
Red Pixel Data Inputs. TTL-compatible red data inputs are registered on the rising
edge of CLK.
G9-0
48, 9–1
TTL
Green Pixel Data Inputs. TTL-compatible green data inputs are registered on the
rising edge of CLK.
B9-0
23–14
TTL
Blue Pixel Data Inputs. TTL-compatible blue data inputs are registered on the rising
edge of CLK.
Controls
Sync Pulse Input. Bringing SYNC LOW turns off a 40 IRE (7.62 mA) current source
which forms a sync pulse on the green D/A converter output. /SYNC is registered on
the rising edge of CLK with the same pipeline latency as /BLANK and pixel data.
/SYNC does not override any other data and should be used only during the blanking
interval.
/SYNC
11
TTL
/BLANK
10
TTL
Blanking Input. When /BLANK is LOW, pixel inputs are ignored and the D/A
converter outputs fall to the blanking level. /BLANK is registered on the rising edge of
CLK and has the same pipeline latency as /SYNC.
IOR
33
0.714Vpp
Red Current Output. The current source outputs of the D/A converters are capable of
driving RS-343A/SMPTE-170M-compatible levels into doubly terminated 75Ω lines.
IOG
32
1VPP
Green Current Output. The current source outputs of the D/A converters are capable
of driving RS-343A/SMPTE-170M-compatible levels into doubly terminated 75Ω lines.
Sync pulses may be added to the green D/A output.
IOB
29
0.714VPP
Blue Current Output. The current source outputs of the D/A converters are capable
of driving RS-343A/SMPTE-170M-compatible levels into doubly terminated 75Ω lines.
+1.235V
Voltage Reference Output/Input. An internal voltage source of +1.235V is output on
this pin. An external +1.235V reference may be applied here to override the internal
reference. Decoupling VREF to GND with a 0.1µF ceramic capacitor is required.
Since this is a single-supply D/A and all signals are positive-going, /SYNC is added to
the bottom of the green D/A range. Turning /SYNC OFF means turning the current
source ON. When a sync pulse is desired, the current source is turned OFF. If the
system does not require sync pulses from the green D/A converter, /SYNC should be
connected to GND.
Video Outputs
FMS3110 / FMS3115 — Triple Video D/A Converters, 3x10 Bit, Ms/s
Pin Definitions
Voltage Reference
VREF
35
VREF
36
560Ω
Current-Setting Resistor. Full-scale output current of each D/A converter is
determined by the value of the resistor connected between RREF and GND. Nominal
value of RREF is found from:
RREF = 9.1 (VREF/IFS)
where IFS is the full-scale (white) output current (in amps) from the D/A converter
(without sync). Sync is 0.4 • IFS.
D/A full-scale (white) current may also be calculated from:
IFS = VFS/RL
where VFS is the white voltage level and RL is the total resistive load (in Ω) on each
D/A converter. VFS is the blank to full-scale voltage.
COMP
34
0.1µF
Compensation Capacitor. A 0.1µF ceramic capacitor must be connected between
COMP and VDD to stabilize internal bias circuitry.
Power and Ground
VDD
12, 30, 31
+5V
Power Supply.
GND
27, 28
0.0V
Ground.
© 2000 Fairchild Semiconductor Corporation
FMS3110 / FMS3115 • Rev. 1.0.8
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only. See Figure 4.
Symbol
Parameter
Min.
Max.
Unit
-0.5
7.0
V
-0.5
VDD+0.5
V
-10
+10
mA
-0.5
VDD+0.5
V
-60
+60
mA
Infinite
s
Power Supply Voltage
VDD
Measured to Ground
VIN_A
Applied Voltage, Measured to Ground
Inputs
IIN_F
Forced Current
(1)
(2, 3)
Outputs
VOUT_A
IOUT_F
tSC
Applied Voltage, Measured to Ground
Forced Current
(1)
(2, 3)
Short-Circuit Duration, Single Output in HIGH State to Ground
Temperature
TA
Operating Ambient Temperature
+110
°C
TJ
Junction Temperature
-20
+150
°C
TL
Lead Soldering, 10 Seconds
+300
°C
TVP
Vapor Phase Soldering, 1 Minute
+220
°C
TSTG
Storage Temperature
+150
°C
-65
Notes:
1. Applied voltage must be current limited to specified range.
2. Forcing voltage must be limited to specified range.
3. Current is specified as conventional current flowing into the device.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VDD
fS
Parameter
Power Supply Voltage
Conversion Rate
tPWH
CLK Pulse-width, HIGH
tPWL
CLK Pulse-width, LOW
Min.
Nom.
Max.
Unit
4.75
5.00
5.25
V
FMS3110
100
FMS3115
150
FMS3110
3.1
FMS3115
2.5
FMS3110
3.1
FMS3115
2.5
FMS3110
10
FMS3115
6.6
Msps
ns
ns
tW
CLK Pulse-width
tS
Input Data Setup Time
1.7
ns
th
Input Data Hold Time
0
ns
VREF
CC
RLOAD
VIH
Reference Voltage, External
1.000
Compensation Capacitor
ns
1.235
1.500
0.1
Output Load
V
µF
Ω
37.5
Input Voltage, Logic HIGH
2.0
VDD
VIL
Input Voltage, Logic LOW
GND
0.8
V
TA
Ambient Temperature, Still Air
0
70
°C
© 2000 Fairchild Semiconductor Corporation
FMS3110 / FMS3115 • Rev. 1.0.8
FMS3110 / FMS3115 — Triple Video D/A Converters, 3x10 Bit, Ms/s
Absolute Maximum Ratings
V
www.fairchildsemi.com
4
Symbol
IDD
(6)
Parameter
Power Supply Current
Conditions
(5)
(5)
Min.
(4)
Typ.
Max.
Units
VDD=Max.
125
mA
VDD=Max.
655
mW
PD
Total Power Dissipation
RO
Output Resistance
CO
Output Capacitance
IOUT=0mA
30
pF
IIH
Input Current HIGH
VDD=Max., VIN=2.4V
-5
µA
IIL
Input Current LOW
VDD=Max., VIN=0.4
+5
µA
±100
µA
IREF
VREF Input Bias Current
VREF
Reference Voltage Output
VOC
Output Compliance
CDI
Digital Input Capacitance
100
0
kΩ
1.235
Referred to VDD
-0.4
V
0
+1.5
V
4
10
pF
Max.
Units
10
15
ns
1
2
ns
Notes:
4. Values shown are typical for VDD=+5V and TA=25°C.
5. Minimum and Maximum values with VDD=Max and TA=Min.
6. VREF=1.235V, RLOAD=37.5Ω, RREF=540Ω.
Switching Characteristics
Symbol
tD
tSKEW
Parameter
Clock to Output Delay
(8)
Conditions
Min.
VDD=Min.
Output Skew
(7)
Typ.
tR
Output Rise Time
10% to 90% of Full Scale
3
ns
tF
Output Fall Time
90% to 10% of Full Scale
3
ns
Max.
Units
Notes:
7. Values shown are typical for VDD=+5V and TA=25°C.
8. VREF=1.235V, RLOAD=37.5Ω, RREF=590Ω.
FMS3110 / FMS3115 — Triple Video D/A Converters, 3x10 Bit, Ms/s
Electrical Characteristics
System Performance Characteristics See Figure 3
Symbol
Parameter
(10)
Conditions
Min.
(9)
Typ.
ELI
Integral Linearity Error
VDD, VREF=Nominal
±0.10
±0.25
%/FS
ELD
Differential Linearity Error
VDD, VREF=Nominal
±0.10
±0.25
%/FS
EDM
DAC to DAC Matching
VDD, VREF=Nominal
3
PSRR
Power Supply Rejection Ratio
10
%
0.05
%/%
Notes:
9. Values shown are typical for VDD=+5V and TA=25°C.
10. VREF=1.235V, RLOAD=37.5Ω, RREF=590Ω.
© 2000 Fairchild Semiconductor Corporation
FMS3110 / FMS3115 • Rev. 1.0.8
www.fairchildsemi.com
5
FMS3110 / FMS3115 — Triple Video D/A Converters, 3x10 Bit, Ms/s
Timing Information
tPWL
1/fS
tPWH
CLK
tH
tS
PIXEL DATA
& CONTROLS
DataN
DataN+1
DataN+2
3%/FS
90%
tD
tSET
tF
OUTPUT
tR
50%
10%
Figure 3. Timing Diagram
Equivalent Circuits
VDD
VDD
p
Digital
Input
n
p
VDD
n
OUT
GND
GND
Figure 4. Equivalent Digital Input Circuit
Figure 5. Equivalent Analog Output Circuit
Figure 6. Equivalent Analog Input Circuit
© 2000 Fairchild Semiconductor Corporation
FMS3110 / FMS3115 • Rev. 1.0.8
www.fairchildsemi.com
6
Within the FMS3110/3115 are three identical 10-bit
D/A converters, each with a current source output.
External loads are required to convert the current to
voltage outputs. Data inputs RGB7-0 are overridden
by the /BLANK input. /SYNC = H activates sync
current from IOS for sync-on-green video signals.
Normally, a 75Ω source termination resistor is
connected between the D/A current output pin and
GND near the D/A converter. A 75Ω line can be
connected with another 75Ω termination resistor at the
far end of the cable. This “double termination” presents
the D/A converter a net resistive load of 37.5Ω.
Digital Inputs
The FMS3110/3115 may also be operated with a
single 75Ω terminating resistor. To lower the output
voltage swing to the desired range, the nominal value
of the resistor on RREF should be doubled.
All digital inputs are TTL-compatible. Data is
registered on the rising edge of the CLK signal.
Following one stage of pipeline delay, the analog
output changes tDO after the rising edge of CLK.
Voltage Reference
/SYNC and /BLANK
All three D/A converters are supplied with a common
voltage reference. Internal bandgap voltage reference
voltage is +1.235V with a 3KΩ source resistance. An
external voltage reference may be connected to the
VREF pin, overriding the internal voltage reference.
/SYNC and /BLANK inputs control the output level
(Figure 7 and Table 1) of the D/A converters during
CRT retrace intervals. /BLANK forces the D/A outputs
to the blanking level, while /SYNC = L turns off a
current source connected to the green D/A converter.
/SYNC = H adds a 40 IRE sync pulse to the green
output; /SYNC = L sets the green output to 0.0V
during the sync tip. /SYNC and /BLANK are
registered on the rising edge of CLK.
A 0.1µF capacitor must be connected between the
COMP pin and VDD to stabilize internal bias circuitry
and ensure low-noise operation.
Power and Ground
/BLANK gates the D/A inputs and sets the pedestal
voltage. If /BLANK = HIGH, D/A inputs are added to a
pedestal, which offsets the current output. If /BLANK
= LOW, data inputs and the pedestal are disabled.
Required power is a single +5.0V supply. To minimize
power-supply induced noise, analog +5V should be
connected to VDD pins with 0.1 and 0.01µF
decoupling capacitors placed adjacent to each VDD
pin or pin pair.
The high slew-rate of digital data makes capacitive
coupling to the outputs of any D/A converter a
potential problem. Since the digital signals contain
high-frequency components of the CLK signal, as well
as the video output signal, the resulting data feedthrough often looks like harmonic distortion or
reduced signal-to-noise performance. All ground pins
should be connected to a common solid ground plane
for best performance.
data: 660mV max.
pedestal: 54mV
sync: 286mV
Figure 7. Nominal Output Levels
FMS3110 / FMS3115 — Triple Video D/A Converters, 3x10 Bit, Ms/s
Functional Description
D/A Outputs
Each D/A output is a current source. To obtain a
voltage output, a resistor must be to ground. Output
voltage depends upon this external resistor, the
reference voltage, and the value of the gain-setting
resistor connected between RREF and GND.
Table 1. Output Voltage vs. Input Code, /SYNC and /BLANK (VREF=1.235V, RREF=590Ω, RL=37.5Ω)
RGB9-0(MSB…LSB)
11 1111 1111
11 1111 1111
11 1111 1110
11 1111 1101
Blue and Red D/As
/SYNC
/BLANK
VOUT
X
X
X
X
1
1
1
1
0.7140
0.7140
0.7134
0.7127
/SYNC
Green D/A
/BLANK
VOUT
1
0
1
1
1
1
1
1
1.0000
0.7140
0.9994
0.9987
:
:
:
:
:
:
:
10 0000 0000
01 1111 1111
X
X
1
1
0.3843
0.3837
1
1
1
1
0.6703
0.6697
:
:
:
:
:
:
:
00 0000 0010
00 0000 0001
00 0000 0000
XX XXXX XXXX
XX XXXX XXXX
X
X
X
X
X
1
1
1
0
0
0.0553
0.0546
0.0540
0.0000
0.0000
1
1
1
1
0
1
1
1
0
0
0.3413
0.3406
0.3400
0.2860
0.0000
© 2000 Fairchild Semiconductor Corporation
FMS3110 / FMS3115 • Rev. 1.0.8
www.fairchildsemi.com
7
Figure 8 illustrates a typical FMS3110/3115 interface
circuit. In this example, an optional 1.2V bandgap
reference is connected to the VREF output, overriding the
internal voltage reference source.
2.
The power plane for the FMS3110/3115 should be
separate from that which supplies the digital
circuitry. A single power plane should be used for
all of the VDD pins. If the power supply for the
FMS3110/3115 is the same as that of the system's
digital circuitry, power to the FMS3110/3115 should
be decoupled with 0.1µF and 0.01µF capacitors
and isolated with a ferrite bead.
3.
The ground plane should be solid, not crosshatched. Connections to the ground plane should
have very short leads.
4.
If the digital power supply has a dedicated power
plane layer, it should not be placed under the
FMS3110/3115, the voltage reference, or the
analog outputs. Capacitive coupling of digital power
supply noise from this layer to the FMS3110/3115
and its related analog circuitry can have an adverse
effect on performance.
5.
CLK should be handled carefully. Jitter and noise
on this clock degrade performance. Terminate the
clock line carefully to eliminate overshoot and
ringing.
Grounding
It is important that the FMS3110/3115 power supply be
well-regulated and free of high-frequency noise. Careful
power supply decoupling ensures the highest quality
video signals at the output of the circuit. The
FMS3110/3115 has separate analog and digital circuits.
To keep digital system noise from the D/A converter, it
is recommended that power supply voltages (VDD) come
from the system analog power source and all ground
connections (GND) be made to the analog ground
plane. Power supply pins should be individually
decoupled at the pin.
Printed Circuit Board Layout
Designing with high-performance mixed-signal circuits
demands printed circuits with ground planes. Overall
system performance is strongly influenced by the board
layout. Capacitive coupling from digital to analog
circuits may result in poor D/A conversion. Consider the
following suggestions when designing the layout:
1.
Keep the critical analog traces (VREF, IREF, COMP,
IOS, IOR, IOG) as short as possible and as far as
possible
from
all
digital
signals.
The
FMS3110/3115 should be located near the board
edge, close to the analog output connectors.
+5V
Related Products
FMS38XX Triple 8-bit 150Msp D/A Converters
FMS9884A 3x8-bit 140Ms/s A/D Converter
FMS3110 / FMS3115 — Triple Video D/A Converters, 3x10 Bit, Ms/s
Application Information
10µF
0.1µF
VDD
RED PIXEL
INPUT
R9-0
GREEN PIXEL
INPUT
G9-0
BLUE PIXEL
INPUT
CLOCK
/SYNC
/BLANK
B9-0
Red
GND
ZO=75Ω
IOR
IOG
IOB
FMS31XX
FMS31XX
Triple 10-bit
D/A Converter
75Ω
75Ω
75Ω
Green w/Sync
ZO=75Ω
75Ω
Blue
ZO=75Ω
75Ω
75Ω
+5V
COMP
CLK
/SYNC
/BLANK
0.1µF
VREF
RREF
560Ω
3.3kΩ(not required without
external reference)
LM185-1.2
(Optional)
0.1µF
Figure 8. Typical Interface Circuit
© 2000 Fairchild Semiconductor Corporation
FMS3110 / FMS3115 • Rev. 1.0.8
www.fairchildsemi.com
8
Inches
Symbol
A
A1
A2
B
D/E
D1/E1
e
L
N
ND
α
ccc
Millimeters
Min.
Max.
Min.
Max.
.055
.001
.053
.063
.005
1.40
.05
1.35
1.60
.15
.057
.006
.010
.346
.362
.268
.284
.019 BSC
.017
.029
48
1.45
.27
9.2
7.2
.50 BSC
.45
.75
48
.17
8.8
6.8
12
0
12
7
0
.004
Notes:
Notes
1. All dimensions and tolerances conform to ANSIY14.5M-1982.
2. Dimensions "D1" and "E1" do not include mold protrusion.Allowable
protrusion is 0.25mm per side. D1 and E1 are maximum plastic body size
dimensions including mold mismatch.
3. Pin 1 identifier is optional.
7
8
2
4. Dimension ND: Number of terminals.
5. Dimension ND: Number of terminals per package edge.
6. "L" is the length of terminal for soldering to a substrate.
7. Dimension "B" does not include dambar protrusion.Allowable dambar
protrusion shall not cause the lead width to exceed the maximum B
dimension by more than 0.08mm. Dambar can not be located on the
lower radius or the foot. Minimum space between protrusion and an
adjacent lead is 0.07mm for 0.4mm and 0.5mm pitch packages.
6
4
5
7
To be determined at seating place ÑCÑ
0.08
8.
D
D1
e
PIN 1
IDENTIFIER
E E1
FMS3110 / FMS3115 — Triple Video D/A Converters, 3x10 Bit, Ms/s
Physical Dimensions
C
L
α
0.063" Ref (1.60mm)
See Lead Detail
A
Base Plane
A2
B
Seating Plane
-CLEAD COPLANARITY
A1
ccc
C
Figure 9. 48-Contact Leadless Quad Flat Package (LMQFP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2000 Fairchild Semiconductor Corporation
FMS3110 / FMS3115 • Rev. 1.0.8
www.fairchildsemi.com
9
FMS3110 / FMS3115 — Triple Video D/A Converters, 3x10 Bit, Ms/s
© 2000 Fairchild Semiconductor Corporation
FMS3110 / FMS3115 • Rev. 1.0.8
www.fairchildsemi.com
10
