Motion SPM) 2 Series, 600 V
FNA25060
General Description
The FNA25060 is a Motion SPM 2 module providing
a fully−featured, high−performance inverter output stage for AC
induction, BLDC, and PMSM motors. These modules integrate
optimized gate drive of the built−in IGBTs to minimize EMI and
losses, while also providing multiple on−module protection features:
under−voltage lockouts, over−current shutdown, temperature sensing,
and fault reporting. The built−in, high−speed HVIC requires only
a single supply voltage and translates the incoming logic−level gate
inputs to high−voltage, high−current drive signals to properly drive the
module’s internal IGBTs. Separate negative IGBT terminals are
available for each phase to support the widest variety of control
algorithms.
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Features
• UL Certified No. E209204 (UL1557)
• 600 V − 50 A 3−Phase IGBT Inverter, Including Control ICs for
•
•
•
•
•
•
•
•
•
Gate Drive and Protections
Low−Loss, Short−Circuit−Rated IGBTs
Very Low Thermal Resistance Using Al2O3 DBC Substrate
Built−In Bootstrap Diodes and Dedicated Vs Pins Simplify PCB
Layout
Separate Open−Emitter Pins from Low−Side IGBTs for Three−Phase
Current Sensing
Single−Grounded Power Supply Supported
Built−In NTC Thermistor for Temperature Monitoring and
Management
Adjustable Over−Current Protection via Integrated Sense−IGBTs
Isolation Rating of 2500 Vrms / 1 min.
This Device is Pb−Free, Halogen Free/BFR Free and is RoHS
Compliant
Applications
SPMCA−A34
CASE MODFQ
MARKING DIAGRAM
$Y
FNA25060
&Z&K&E&E&E&3
FNA25060
$Y
&Z
&K
&E
&3
= Specific Device Code
= ON Semiconductor Logo
= Assembly Plant Code
= Lot Code
= Space Designator
= 3−Digit Date Code
ORDERING INFORMATION
• Motion Control − Industrial Motor (AC 200 V Class)
See detailed ordering and shipping information on page 2 of
this data sheet.
Related Resources
• AN−9121 − Users Guide for 600V SPM 2 Series
• AN−9076 − Mounting Guide for New SPM 2 Package
• AN−9079 − Thermal Performance of Motion SPM 2 Series by
Mounting Torque
© Semiconductor Components Industries, LLC, 2015
May, 2020 − Rev. 2
1
Publication Order Number:
FNA25060/D
FNA25060
PACKAGE MARKING AND ORDERING INFORMATION
Device
Device Marking
Package
Packing Type
Quantity
FNA25060
FNA25060
SPMCA−A34
Rail
6
Integrated Power Functions
• 600 V − 50 A IGBT inverter for three−phase DC / AC
power conversion (refer to Figure 2)
Integrated Drive, Protection, and System Control Functions
• For inverter high−side IGBTs:
•
gate−drive circuit, high−voltage isolated high−speed
level−shifting control circuit,
Under−Voltage Lock−Out Protection (UVLO),
Available bootstrap circuit example is given in Figures
4 and 14
For inverter low−side IGBTs:
gate−drive circuit, Short−Circuit Protection (SCP)
control circuit,
Under−Voltage Lock−Out Protection (UVLO)
• Fault signaling:
corresponding to UV (low−side supply) and SC faults
• Input interface:
active−HIGH interface, works with 3.3 / 5 V logic,
Schmitt−trigger input
Pin Configuration
Figure 1. Top View
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2
FNA25060
PIN DESCRIPTIONS
Pin No.
Pin Name
Pin Description
1
P
Positive DC−Link Input
2
W
Output for W Phase
3
V
Output for V Phase
4
U
Output for U Phase
5
NW
Negative DC−Link Input for W Phase
6
NV
Negative DC−Link Input for V Phase
7
NU
Negative DC−Link Input for U Phase
8
RTH
Series Resistor for Thermistor (Temperature Detection)
9
VTH
Thermistor Bias Voltage
10
VCC(L)
Low−Side Bias Voltage for IC and IGBTs Driving
11
COM(L)
Low−Side Common Supply Ground
12
IN(UL)
Signal Input for Low−Side U Phase
13
IN(VL)
Signal Input for Low−Side V Phase
14
IN(WL)
Signal Input for Low−Side W Phase
15
VFO
Fault Output
16
CFOD
Capacitor for Fault Output Duration Selection
17
CSC
Capacitor (Low−Pass Filter) for Short−Circuit Current Detection Input
18
RSC
Resistor for Short−Circuit Current Detection
19
IN(UH)
Signal Input for High−Side U Phase
20
COM(H)
High−Side Common Supply Ground
21
VCC(UH)
High−Side Bias Voltage for U Phase IC
22
VBD(U)
Anode of Bootstrap Diode for U Phase High−Side Bootstrap Circuit
23
VB(U)
High−Side Bias Voltage for U Phase IGBT Driving
24
VS(U)
High−Side Bias Voltage Ground for U Phase IGBT Driving
25
IN(VH)
Signal Input for High−Side V Phase
26
VCC(VH)
High−Side Bias Voltage for V Phase IC
27
VBD(V)
Anode of Bootstrap Diode for V Phase High−Side Bootstrap Circuit
28
VB(V)
High−Side Bias Voltage for V Phase IGBT Driving
29
VS(V)
High−Side Bias Voltage Ground for V Phase IGBT Driving
30
IN(WH)
Signal Input for High−Side W Phase
31
VCC(WH)
High−Side Bias Voltage for W Phase IC
32
VBD(W)
Anode of Bootstrap Diode for W Phase High−Side Bootstrap Circuit
33
VB(W)
High−Side Bias Voltage for W Phase IGBT Driving
34
VS(W)
High−Side Bias Voltage Ground for W Phase IGBT Driving
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3
FNA25060
Internal Equivalent Circuit and Input/Output Pins
NOTES:
1. Inverter high−side is composed of three normal−IGBTs, freewheeling diodes, and one control IC for each IGBT.
2. Inverter low−side is composed of three sense−IGBTs, freewheeling diodes, and one control IC for each IGBT.
It has gate drive and protection functions.
3. Inverter power side is composed of four inverter DC−link input terminals and three inverter output terminals.
Figure 2. Internal Block Diagram
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FNA25060
ABSOLUTE MAXIMUM RATINGS (TC = 25°C, Unless Otherwise Specified)
Symbol
Conditions
Parameter
Rating
Unit
INVERTER PART
VPN
VPN(Surge)
VCES
Supply Voltage
Applied between P − NU, NV, NW
450
V
Supply Voltage (Surge)
Applied between P − NU, NV, NW
500
V
600
V
Collector − Emitter Voltage
±IC
Each IGBT Collector Current
TC = 25°C, TJ ≤ 150°C (Note 4)
50
A
±ICP
Each IGBT Collector Current (Peak)
TC = 25°C, TJ ≤ 150°C, Under 1 ms Pulse
Width (Note 4)
100
A
PC
Collector Dissipation
TC = 25°C per One Chip (Note 4)
192
W
TJ
Operating Junction Temperature
−40 ∼ 150
°C
CONTROL PART
VCC
Control Supply Voltage
Applied between VCC(H), VCC(L) − COM
20
V
VBS
High−Side Control Bias Voltage
Applied between VB(U) − VS(U), VB(V) −
VS(V), VB(W) − VS(W)
20
V
VIN
Input Signal Voltage
Applied between IN(UH), IN(VH), IN(WH),
IN(UL), IN(VL), IN(WL) − COM
−0.3 ∼ VCC+0.3
V
VFO
Fault Output Supply Voltage
Applied between VFO − COM
−0.3 ∼ VCC+0.3
V
IFO
Fault Output Current
Sink Current at VFO pin
2
mA
VSC
Current Sensing Input Voltage
Applied between CSC − COM
−0.3 ∼ VCC+0.3
V
600
V
BOOTSTRAP DIODE PART
VRRM
Maximum Repetitive Reverse Voltage
Forward Current
TC = 25°C, TJ ≤ 150°C (Note 4)
1.0
A
IFP
Forward Current (Peak)
TC = 25°C, TJ ≤ 150°C, Under 1 ms Pulse
Width (Note 4)
2.0
A
TJ
Operating Junction Temperature
−40 ∼ 150
°C
400
V
−40 ∼ 125
°C
−40 ∼ 125
°C
2500
Vrms
IF
TOTAL SYSTEM
VPN(PROT)
Self−Protection Supply Voltage Limit
(Short−Circuit Protection Capability)
VCC = VBS = 13.5 ∼ 16.5 V, TJ = 150°C,
VCES < 600 V, Non−Repetitive, < 2 ms
TC
Module Case Operation Temperature
See Figure 2
TSTG
Storage Temperature
VISO
Isolation Voltage
60 Hz, Sinusoidal, AC 1 Minute, Connection
Pins to Heat Sink Plate
THERMAL RESISTANCE
Symbol
Rth(j−c)Q
Rth(j−c)F
Parameter
Junction to Case
Thermal Resistance (Note 5)
Conditions
Min.
Typ.
Max.
Unit
Inverter IGBT Part (per 1 / 6 Module)
−
−
0.65
°C/W
Inverter FWD Part (per 1 / 6 Module)
−
−
1.12
°C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
4. These values had been made an acquisition by the calculation considered to design factor.
5. For the measurement point of case temperature (TC), please refer to Figure 1.
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5
FNA25060
ELECTRICAL CHARACTERISTICS (TJ = 25°C, unless otherwise specified)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
INVERTER PART
Collector − Emitter Saturation Voltage
VCC = VBS = 15 V
VIN = 5 V
IC = 50 A,
TJ = 25°C
−
1.50
2.10
V
FWDi Forward Voltage
VIN = 0 V
IF = 50 A,
TJ = 25°C
−
1.80
2.40
V
Switching Times
VPN = 300 V, VCC = 15 V, IC = 50 A
TJ = 25°C
VIN = 0 V ↔ 5 V, Inductive Load
See Figure 4
(Note 6)
0.80
1.30
1.90
ms
−
0.30
0.70
ms
−
1.20
1.80
ms
tC(OFF)
−
0.15
0.55
ms
trr
−
0.25
−
ms
0.50
1.00
1.60
ms
−
0.30
0.70
ms
−
1.20
1.80
ms
tC(OFF)
−
0.25
0.65
ms
trr
−
0.20
−
ms
−
−
5
mA
VCE(SAT)
VF
tON
HS
tC(ON)
tOFF
LS
VPN = 300 V, VCC = 15 V, IC = 50 A
TJ = 25°C
VIN = 0 V ↔ 5 V, Inductive Load
See Figure 4
(Note 6)
tON
tC(ON)
tOFF
ICES
Collector − Emitter Leakage Current
VCE = VCES
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. tON and tOFF include the propagation delay of the internal drive IC. tC(ON) and tC(OFF) are the switching times of IGBT under the given
gate−driving condition internally. For the detailed information, please see Figure 3.
Figure 3. Switching Time Definition
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FNA25060
One−Leg Diagram of SPM 2
R BS
CB S
VC C
VB
COM
LS Switching
OUT
VS
IN
HS Switching
HS Switching
OUT
CSC
V
COM
15 V
NU,V,W
V
R SC
5V
Figure 4. Example Circuit for Switching Test
Figure 5. Switching Loss Characteristics (Typical)
R−T Curve
600
550
500
20
450
16
Resistance[kΩ]
Resistance[kW]
0V
4.7 kΩ
V
Inductor
IN
VC C
VFO
CFO D
V IN
VC C
VP N
U,V,W
LS Switching
5V
IC
P
400
350
300
250
200
R−T Curve in 50°C ~ 125°C
12
8
4
0
50
60
150
70
80
90
100
110
120
Temperature [°C]
100
50
0
−20
−10
0
10
20
30
40
50
60
70
80
90
100
Temperature TTH [5C]
Figure 6. R−T Curve of Built−in Thermistor
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110
120
FNA25060
BOOTSTRAP DIODE PART
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VF
Forward Voltage
IF = 1.0 A, TJ = 25°C
−
2.2
−
V
trr
Reverse−Recovery Time
IF = 1.0 A, dIF / dt = 50 A / μs,
TJ = 25°C
−
80
−
ns
CONTROL PART
Symbol
IQCCH
Parameter
Quiescent VCC Supply Current
IQCCL
IPCCH
Operating VCC Supply Current
IPCCL
Conditions
Min.
Typ.
Max.
Unit
VCC(UH,VH,WH) = 15 V,
IN(UH,VH,WH) = 0 V
VCC(UH) − COM(H),
VCC(VH) − COM(H),
VCC(WH) − COM(H)
−
−
0.15
mA
VCC(L) = 15 V,
IN(UL,VL, WL) = 0 V
VCC(L) − COM(L)
−
−
5.00
mA
VCC(UH,VH,WH) = 15 V,
fPWM = 20 kHz, Duty = 50%,
Applied to one PWM Signal
Input for High−Side
VCC(UH) − COM(H),
VCC(VH) − COM(H),
VCC(WH) − COM(H)
−
−
0.30
mA
VCC(L) = 15V, fPWM = 20 kHz,
VCC(L) − COM(L)
Duty = 50%, Applied to one
PWM Signal Input for Low−Side
−
−
9.00
mA
IQBS
Quiescent VBS Supply Current
VBS = 15 V, IN(UH, VH, WH) = 0 V VB(U) − VS(U),
VB(V) − VS(V),
VB(W) − VS(W)
−
−
0.30
mA
IPBS
Operating VBS Supply Current
VCC = VBS = 15 V,
VB(U) − VS(U),
fPWM = 20 kHz,
VB(V) − VS(V),
Duty = 50%, Applied to one
PWM Signal Input for High−Side VB(W) − VS(W)
−
−
6.50
mA
VFOH
Fault Output Voltage
VCC = 15 V, VSC = 0 V, VFO Circuit: 4.7 kΩ to 5 V Pull−up
4.5
−
−
V
VCC = 15 V, VSC = 1 V, VFO Circuit: 4.7 kΩ to 5 V Pull−up
−
−
0.5
V
−
20
−
mA
VFOL
ISEN
Sensing Current of Each Sense VCC = 15 V, VIN = 5 V,
IGBT
RSC = 0 Ω,
No Connection of Shunt
Resistor at NU,V,W Terminal
IC = 50 A
VSC(ref) Short Circuit Trip Level
Short Circuit Current Level for
ISC
Trip
VCC = 15 V (Note 7)
CSC − COM(L)
RSC = 18 Ω (±1%), No Connection of Shunt Resistor at
NU,V,W Terminal (Note 7)
0.43
0.50
0.57
V
−
100
−
A
UVCCD Supply Circuit Under− Voltage
Protection
UVCCR
Detection Level
10.3
−
12.8
V
Reset Level
10.8
−
13.3
V
UVBSD
Detection Level
9.5
−
12.0
V
UVBSR
Reset Level
10.0
−
12.5
V
50
−
−
ms
1.7
−
−
ms
−
−
2.6
V
0.8
−
−
V
tFOD
Fault−Out Pulse Width
VIN(ON) ON Threshold Voltage
VIN(OFF) OFF Threshold Voltage
RTH
Resistance of Thermistor
CFOD = Open
(Note 8)
CFOD = 2.2 nF
Applied between IN(UH, VH, WH) − COM(H), IN(UL, VL, WL) −
COM(L)
at TTH = 25°C
See Figure 6
(Note 9)
at TTH = 100°C
−
47
−
kW
−
2.9
−
kW
7. Short−circuit current protection functions only at the low−sides because the sense current is divided from main current at low−side IGBTs.
Inserting the shunt resistor for monitoring the phase current at NU, NV, NW terminal, the trip level of the short−circuit current is changed.
8. The fault−out pulse width tFOD depends on the capacitance value of CFOD according to the following approximate equation:
tFOD = 0.8 x 106 x CFOD [s].
9. TTH is the temperature of thermistor itself. To know case temperature (TC), conduct experiments considering the application.
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FNA25060
RECOMMENDED OPERATING CONDITIONS
Value
Min.
Typ.
Max.
Unit
−
300
400
V
Applied between VCC(UH, VH, WH) −
COM(H), VCC(L) − COM(L)
14.5
15.0
16.5
V
Applied between VB(U) − VS(U),
VB(V) − VS(V), VB(W) − VS(W)
13.5
15.0
18.5
V
Control Supply Variation
−1
−
1
V / ms
tdead
Blanking Time for Preventing Arm − For Each Input Signal
Short
2.0
−
−
ms
fPWM
PWM Input Signal
−40_C ≤ TC ≤ 125_C,
−40_C ≤ TJ ≤ 150_C
−
−
20
kHz
VSEN
Voltage for Current Sensing
Applied between NU, NV, NW −
COM(H, L)
(Including Surge Voltage)
−5
5
V
PWIN(ON)
Minimun Input Pulse Width
VCC = VBS = 15 V, IC ≤ 100 A,
Wiring Inductance between NU, V, W
and DC Link N < 10nH (Note 10)
2.5
−
−
ms
2.5
−
−
−40
−
150
Symbol
Parameter
Conditions
VPN
Supply Voltage
Applied between P − NU, NV, NW
VCC
Control Supply Voltage
VBS
High−Side Bias Voltage
dVCC / dt,
dVBS / dt
PWIN(OFF)
TJ
Junction Temperature
_C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
10. This product might not make right output response if input pulse width is less than the recommanded value.
11. This allowable output current value is the reference data for the safe operation of this product. This may be different from the
actual application and operating condition.
Figure 7. Allowable Maximum Output Current
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FNA25060
MECHANICAL CHARACTERISTICS AND RATINGS
Parameter
Conditions
Device Flatness
See Figure 9
Mounting Torque
Mounting Screw: M4
See Figure 10
Min.
Typ.
Max.
Unit
0
−
+200
mm
Recommended 1.0 N/m
0.9
1.0
1.5
N/m
Recommended 10.1 kg/cm
9.1
10.1
15.1
kg/cm
Terminal Pulling Strength
Load 19.6 N
10
−
−
s
Terminal Bending Strength
Load 9.8 N, 90 degrees Bend
2
−
−
times
−
50
−
g
Weight
(＋)
(＋)
Figure 8. Flatness Measurement Position
2
Pre − Screwing : 1
2
Final Screwing : 2
1
1
Figure 9. Mounting Screws Torque Order
NOTES:
12. Do not over torque when mounting screws. Too much mounting torque may cause DBC cracks, as well as bolts and Al heat−sink destruction.
13. Avoid one−sided tightening stress. Figure 9 shows the recommended torque order for the mounting screws. Uneven mounting can cause
the DBC substrate of package to be damaged. The pre−screwing torque is set to 20 ∼ 30% of maximum torque rating.
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FNA25060
Time Charts of SPMs Protective Function
Input Signal
Protection
Circuit State
RESET
SET
RESET
UVC CR
a1
Control
Supply Voltage
a6
UVC C D
a3
a2
a7
a4
Output Current
a5
Fault Output Signal
a1 : Control supply voltage rises: after the voltage rises UVCCR, the circuits start to operate when the next input is applied.
a2 : Normal operation: IGBT ON and carrying current.
a3 : Under−voltage detection (UVCCD).
a4 : IGBT OFF in spite of control input condition.
a5 : Fault output operation starts with a fixed pulse width according to the condition of the external capacitor CFOD.
a6 : Under−voltage reset (UVCCR).
a7 : Normal operation: IGBT ON and carrying current by triggering next signal from LOW to HIGH.
Figure 10. Under−Voltage Protection (Low−Side)
Input Signal
Protection
Circuit State
RESET
SET
RESET
UVBSR
Control
Supply Voltage
b1
UVBSD
b5
b3
b6
b2
b4
Output Current
High−level (no fault output )
Fault Output Signal
b1 : Control supply voltage rises: after the voltage reaches UVBSR, the circuits start to operate when the next input is applied.
b2 : Normal operation: IGBT ON and carrying current.
b3 : Under−voltage detection (UVBSD).
b4 : IGBT OFF in spite of control input condition, but there is no fault output signal.
b5 : Under−voltage reset (UVBSR).
b6 : Normal operation: IGBT ON and carrying current by triggering next signal from LOW to HIGH.
Figure 11. Under−Voltage Protection (High−Side)
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11
FNA25060
Lower Arms
Control Input
c6
Protection
Circuit state
SET
Internal IGBT
Gate−Emitter Voltage
c3
c2
c7
RESET
c4
I nt ernal delay
at protection c irc uit
S C current t rip level
c8
c1
Output Current
SC referenc e v oltage
Sensing Voltage
of Sense Resistor
Fault Output Signal
c5
RC f ilt er circuit
time cons tant
delay
c1 : Normal operation: IGBT ON and carrying current.
c2 : Short−circuit current detection (SC trigger).
c3 : All low−side IGBTs gate are hard interrupted.
c4 : All low−side IGBTs turn OFF.
c5 : Fault output operation starts with a fixed pulse width according to the condition of the external capacitor CFOD.
c6 : Input HIGH: IGBT ON state, but during the active period of fault output, the IGBT doesn’t turn ON.
c7 : Fault output operation finishes, but IGBT doesn’t turn on until triggering the next signal from LOW to HIGH.
c8 : Normal operation: IGBT ON and carrying current.
Figure 12. Short−Circuit Current Protection (Low−Side Operation only)
Input/Output Interface Circuit
+5V ( MCU or control power )
SPM
4.7 kΩ
IN(UH) , IN (VH) , IN(WH)
IN (UL) , IN (VL) , IN( WL)
MCU
VFO
COM
14. RC coupling at each input might change depending on the PWM control scheme used in the application and the wiring impedance
of the application’s printed circuit board.
The input signal section of the Motion SPM 2 product integrates 5 kW (typ.) pull−down resistor. Therefore, when using an external
filtering resistor, please pay attention to the signal voltage drop at input terminal.
Figure 13. Recommended MCU I/O Interface Circuit
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FNA25060
Figure 14. Typical Application Circuit
15. To avoid malfunction, the wiring of each input should be as short as possible (less than 2 − 3 cm).
16. VFO output is an open−drain type. This signal line should be pulled up to the positive side of the MCU or control power supply with a resistor
that makes IFO up to 2 mA. Please refer to Figure 13.
17. Fault out pulse width can be adjust by capacitor C5 connected to the CFOD terminal.
18. Input signal is active−HIGH type. There is a 5 kΩ resistor inside the IC to pull−down each input signal line to GND. RC coupling circuits should
be adopted for the prevention of input signal oscillation. R1C1 time constant should be selected in the range 50 ~ 150 ns (recommended R1
= 100 W, C1 = 1 nF).
19. Each wiring pattern inductance of point A should be minimized (recommend less than 10 nH). Use the shunt resistor R4 of surface mounted
(SMD) type to reduce wiring inductance. To prevent malfunction, wiring of point E should be connected to the terminal of the shunt resistor
R4 as close as possible.
20. To insert the shunt resistor to measure each phase current at NU, NV, NW terminal, it makes to change the trip level ISC about the short−ciruit
current.
21. To prevent errors of the protection function, the wiring of points B, C, and D should be as short as possible. The wiring of B between CSC
filter and RSC terminal should be divided at the point that is close to the terminal of sense resistor R5.
22. For stable protection function, use the sense resistor R5 with resistance variation within 1% and low inductance value.
23. In the short−circuit protection circuit, select the R6C6 time constant in the range 1.0 ∼ 1.5 ms. R6 should be selected with a minimum of 10
times larger resistance than sense resistor R5. Do enough evaluaiton on the real system because short−circuit protection time may vary
wiring pattern layout and value of the R6C6 time constant.
24. Each capacitor should be mounted as close to the pins of the Motion SPM 2 product as possible.
25. To prevent surge destruction, the wiring between the smoothing capacitor C7 and the P & GND pins should be as short as possible. The use
of a high−frequency non− inductive capacitor of around 0.1 ∼ 0.22 mF between the P & GND pins is recommended.
26. Relays are used in most systems of electrical equipments in industrial application. In these cases, there should be sufficient distance between
the MCU and the relays.
27. The Zener diode or transient voltage suppressor should be adapted for the protection of ICs from the surge destruction between each pair
of control supply terminals (recommanded Zener diode is 22 V / 1 W, which has the lower Zener impedance characteristic than about15 W).
28. C2 of around seven times larger than bootstrap capacitor C3 is recommended.
29. Please choose the electrolytic capacitor with good temperature characteristic in C3. Choose 0.1 ∼ 0.2 mF R−category ceramic capacitors with
good temperature and frequency characteristics in C4.
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SPMCA−A34 / 34LD, PDD STD, DBC DIP TYPE
CASE MODFQ
ISSUE O
DOCUMENT NUMBER:
DESCRIPTION:
98AON13565G
DATE 31 JAN 2017
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
SPMCA−A34 / 34LD, PDD STD, DBC DIP TYPE
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