DATA SHEET
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Motion SPM) 45 Series
FNA41560T2
General Description
FNA41560T2 is a Motion SPM 45 module providing
a fully−featured, high−performance inverter output stage for AC
Induction, BLDC, and PMSM motors. These modules integrate
optimized gate drive of the built−in IGBTs to minimize EMI
and losses, while also providing multiple on−module protection
features including under−voltage lockouts, over−current shutdown,
thermal monitoring of drive IC, and fault reporting. The built−in,
high−speed HVIC requires only a single supply voltage and translates
the incoming logic−level gate inputs to the high−voltage, high−current
drive signals required to properly drive the module’s internal IGBTs.
Separate negative IGBT terminals are available for each phase
to support the widest variety of control algorithms.
Features
3D Package Drawing (Click to Activate 3D Content)
SPMAA−C26 / 26LD, PDD STD CERAMIC TYPE,
LONG LEAD DUAL FORM TYPE
CASE MODFC
• UL Certified No. E209204 (UL1557)
• 600 V − 15 A 3−Phase IGBT Inverter with Integral Gate Drives
•
•
•
•
•
•
•
•
and Protection
Low Thermal Resistance Using Ceramic Substrate
Low−Loss, Short−Circuit−Rated IGBTs
Built−In Bootstrap Diodes and Dedicated Vs Pins Simplify PCB
Layout
Built−In NTC Thermistor for Temperature Monitoring
Separate Open−Emitter Pins from Low−Side IGBTs for Three−Phase
Current Sensing
Single−Grounded Power Supply
Isolation Rating of 2000 Vrms / 1 min.
This is a Pb−Free and Halogen Free/BFR Free Device
MARKING DIAGRAM
26
10
$Y
FNA41560T2
XXX
YWW
9
1
$Y
FNA41560T2
XXX
Y
WW
= onsemi Logo
= Specific Device Code
= Trace Code
= Year
= Work Week
Applications
• Motion Control − Home Appliance / Industrial Motor
ORDERING INFORMATION
See detailed ordering and shipping information on page 14 of
this data sheet.
Related Resources
• AN−9084 − Smart Power Module, Motion SPM® 45 H V3 Series
User’s Guilde
• AN−9072 − Smart Power Module Motion SPM® in SPM45H
•
•
Thermal Performance Information
AN−9071 − Smart Power Module Motion SPM® in SPM45H
Mounting Guidance
AN−9760 − PCB Design Guidance for SPM®
© Semiconductor Components Industries, LLC, 2016
October, 2021 − Rev. 2
1
Publication Order Number:
FNA41560T2/D
FNA41560T2
Integrated Power Functions
• 600 V − 15 A IGBT inverter for three−phase DC / AC
power conversion (refer to Figure 2)
Integrated Drive, Protection, and System Control Functions
• For inverter high−side IGBTs:
gate−drive circuit, high−voltage isolated high−speed
level−shifting control circuit,
Under−Voltage Lock−Out Protection (UVLO)
• Fault signaling:
•
NOTE: Available bootstrap circuit example is given in
Figures 14
• For inverter low−side IGBTs:
gate−drive circuit, Short−Circuit Protection (SCP)
control supply circuit,
Under−Voltage Lock−Out Protection (UVLO)
corresponding to UVLO (low−side supply)
and SC faults
Input interface:
active−HIGH interface, works with 3.3 / 5 V logic,
Schmitt−trigger input
Pin Configuration
Figure 1. Top View
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FNA41560T2
PIN DESCRIPTIONS
Pin No.
Pin Name
Pin Description
1
VTH
Thermistor Bias Voltage
2
RTH
Series Resistor for the Use of Thermistor (Temperature Detection)
3
P
Positive DC−Link Input
4
U
Output for U−Phase
5
V
Output for V−Phase
6
W
Output for W−Phase
7
NU
Negative DC−Link Input for U−Phase
8
NV
Negative DC−Link Input for V−Phase
9
NW
Negative DC−Link Input for W−Phase
10
CSC
Shut Down Input for Short−circuit Current Detection Input
11
VFO
Fault Output
12
IN(WL)
Signal Input for Low−Side W−Phase
13
IN(VL)
Signal Input for Low−Side V−Phase
14
IN(UL)
Signal Input for Low−Side U−Phase
15
COM
Common Supply Ground
16
VDD(L)
Low−Side Common Bias Voltage for IC and IGBTs Driving
17
VDD(H)
High−Side Common Bias Voltage for IC and IGBTs Driving
18
IN(WH)
Signal Input for High−Side W−Phase
19
IN(VH)
Signal Input for High−Side V−Phase
20
IN(UH)
Signal Input for High−Side U−Phase
21
VS(W)
High−Side Bias Voltage Ground for W−Phase IGBT Driving
22
VB(W)
High−Side Bias Voltage for W−Phase IGBT Driving
23
VS(V)
High−Side Bias Voltage Ground for V−Phase IGBT Driving
24
VB(V)
High−Side Bias Voltage for V−Phase IGBT Driving
25
VS(U)
High−Side Bias Voltage Ground for U−Phase IGBT Driving
26
VB(U)
High−Side Bias Voltage for U−Phase IGBT Driving
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FNA41560T2
Internal Equivalent Circuit and Input/Output Pins
VTH (1)
Thermistor
(26) VB(U)
(25) VS(U)
(24) VB(V)
(23) VS(V)
(22) VB(W)
(21) VS(W)
(20) IN(UH)
(19) IN(VH)
(18) IN(WH)
(17) VDD(H)
(16) VDD(L)
(15) COM
(14) IN(UL)
(13) IN (VL)
(12) IN(WL)
(11) VFO
(10) CSC
RTH (2)
P (3)
UVB
UVS
OUT(UH)
VVB
UVS
U(4)
VVS
WVB
WVS
IN(UH)
OUT(VH)
VVS
V (5)
IN(VH)
IN(WH)
VDD
OUT(WH)
COM
WVS
W(6)
VDD
OUT(UL)
COM
NU (7)
IN(UL)
IN(VL)
IN(WL)
OUT(VL)
NV (8)
VFO
CSC
OUT(WL)
NW (9)
NOTES:
1. Inverter high−side is composed of three normal−IGBTs, freewheeling diodes, and one control IC for each IGBT.
2. Inverter low−side is composed of three sense−IGBTs, freewheeling diodes, and one control IC for each IGBT.
It has gate drive and protection functions.
3. Inverter power side is composed of four inverter DC−link input terminals and three inverter output terminals.
Figure 2. Internal Block Diagram
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FNA41560T2
ABSOLUTE MAXIMUM RATINGS (TJ = 25°C, unless otherwise specified)
Parameter
Symbol
Conditions
Rating
Unit
INVERTER PART
VPN
VPN(Surge)
VCES
Supply Voltage
Applied between P − NU, NV, NW
450
V
Supply Voltage (Surge)
Applied between P − NU, NV, NW
500
V
600
V
Collector − Emitter Voltage
±IC
Each IGBT Collector Current
TC = 25°C, TJ < 150°C
15
A
±ICP
Each IGBT Collector Current (Peak)
TC = 25°C, TJ < 150°C,
Under 1 ms Pulse Width (Note 4)
30
A
PC
Collector Dissipation
TC = 25°C per One Chip (Note 4)
TJ
Operating Junction Temperature
38
W
−40 ∼ 150
°C
CONTROL PART
VDD
Control Supply Voltage
Applied between VDD(H), VDD(L) − COM
20
V
VBS
High−Side Control Bias Voltage
Applied between VB(U) − VS(U),
VB(V) − VS(V), VB(W) − VS(W)
20
V
VIN
Input Signal Voltage
Applied between IN(UH), IN(VH), IN(WH),
IN(UL), IN(VL), IN(WL) − COM
−0.3 ∼ VDD + 0.3
V
VFO
Fault Output Supply Voltage
Applied between VFO − COM
−0.3 ∼ VDD + 0.3
V
IFO
Fault Output Current
Sink Current at VFO pin
VSC
Current−Sensing Input Voltage
Applied between CSC − COM
1
mA
−0.3 ∼ VDD + 0.3
V
600
V
BOOTSTRAP DIODE PART
VRRM
Maximum Repetitive Reverse Voltage
IF
Forward Current
TC = 25°C, TJ < 150°C
0.5
A
IFP
Forward Current (Peak)
TC = 25°C, TJ < 150°C,
Under 1 ms Pulse Width (Note 4)
2.0
A
TJ
Operating Junction Temperature
−40 ∼ 150
°C
400
V
−40 ∼ 125
°C
TOTAL SYSTEM
VPN(PROT)
Self−Protection Supply Voltage Limit
(Short−Circuit Protection Capability)
VDD = VBS = 13.5 ∼ 16.5 V, TJ = 150°C,
Non−Repetitive, < 2 ms
TC
Module Case Operation Temperature
See Figure 1
TSTG
Storage Temperature
VISO
Isolation Voltage
60 Hz, Sinusoidal, AC 1 Minute,
Connect Pins to Heat Sink Plate
−40 ∼ 125
°C
2000
Vrms
THERMAL RESISTANCE
Symbol
Parameter
Rth(j−c)Q
Junction to Case Thermal Resistance
(Note 5)
Rth(j−c)F
Conditions
Min.
Typ.
Max.
Unit
Inverter IGBT Part (per 1 / 6 Module)
−
−
3.20
°C/W
Inverter FWDi Part (per 1 / 6 Module)
−
−
4.00
°C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
4. These values had been made an acquisition by the calculation considered to design factor.
5. For the measurement point of case temperature (TC), please refer to Figure 1.
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FNA41560T2
ELECTRICAL CHARACTERISTICS (TJ = 25°C, unless otherwise specified)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
INVERTER PART
Collector − Emitter Saturation
Voltage
VDD = VBS = 15 V
VIN = 5 V
IC = 15 A,
TJ = 25°C
−
1.60
2.20
V
FWDi Forward Voltage
VIN = 0 V
IF = 15 A,
TJ = 25°C
−
2.00
2.60
V
Switching Times
VPN = 300 V, VDD = VBS = 15 V, IC = 15 A
TJ = 25°C
VIN = 0 V ↔ 5 V, Inductive Load
(Note 6)
0.40
0.80
1.30
ms
−
0.20
0.50
ms
−
0.85
1.35
ms
tC(OFF)
−
0.25
0.55
ms
trr
−
0.10
−
ms
0.45
0.85
1.35
ms
−
0.25
0.55
ms
−
0.90
1.40
ms
tC(OFF)
−
0.25
0.55
ms
trr
−
0.15
−
ms
−
−
1
mA
VCE(SAT)
VF
tON
HS
tC(ON)
tOFF
LS
VPN = 300 V, VDD = VBS = 15 V, IC = 15 A
TJ = 25°C
VIN = 0 V ↔ 5 V, Inductive Load
(Note 6)
tON
tC(ON)
tOFF
ICES
Collector − Emitter Leakage
Current
VCE = VCES
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. tON and tOFF include the propagation delay of the internal drive IC. tC(ON) and tC(OFF) are the switching times of IGBT under the given gate
driving condition internally. For the detailed information, please see Figure 3.
Figure 3. Switching Time Definition
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FNA41560T2
Inductive Load, VPN = 300 V, VDD = 15 V, TJ = 150°C
Inductive Load, VPN = 300 V, VDD = 15 V, TJ = 25°C
IGBT Turn−on, Eon
IGBT Turn−off, Eoff
FRD Turn−off, Erec
1200
IGBT Turn−on, Eon
IGBT Turn−off, Eoff
FRD Turn−off, Erec
1400
ESW, Switching Loss (mJ)
ESW, Switching Loss (mJ)
1400
1000
800
600
400
200
1200
1000
800
600
400
200
0
0
0
5
10
15
0
5
IC, Collector Current (A)
10
15
IC, Collector Current (A)
Figure 4. Switching Loss Characteristics (Typical)
CONTROL PART
Symbol
Parameter
IQDDH
Quiescent VDD Supply Current
IQDDL
IPDDH
Operating VDD Supply Current
IPDDL
Conditions
Min.
Typ.
Max.
Unit
VDD(H) = 15 V, IN(UH,VH, WH) = 0 V
VDD(H) − COM
−
−
0.10
mA
VDD(L) = 15 V, IN(UL,VL, WL) = 0 V
VDD(L) − COM
−
−
2.65
mA
VDD(H) = 15 V,
fPWM = 20 kHz, Duty = 50%,
Applied to one PWM Signal
Input for High−Side
VDD(H) − COM
−
−
0.15
mA
VDD(L) = 15V,
fPWM = 20 kHz, Duty = 50%,
Applied to one PWM Signal
Input for Low−Side
VDD(L) − COM
−
−
4.00
mA
IQBS
Quiescent VBS Supply Current
VBS = 15 V, IN(UH, VH, WH) = 0 V
VB(U) − VS(U),
VB(V) − VS(V),
VB(W) − VS(W)
−
−
0.30
mA
IPBS
Operating VBS Supply Current
VDD = VBS = 15 V,
fPWM = 20 kHz,
Duty = 50%, Applied to one PWM
Signal Input for High−Side
VB(U) − VS(U),
VB(V) − VS(V),
VB(W) − VS(W)
−
−
2.00
mA
VFOH
Fault Output Voltage
VSC = 0 V, VFO Circuit: 4.7 kΩ to 5 V Pull−up
4.5
−
−
V
VSC = 1 V, VFO Circuit: 4.7 kΩ to 5 V Pull−up
−
−
0.5
V
0.45
0.50
0.55
V
10.5
−
13.0
V
VFOL
VSC(ref)
Short Circuit Trip Level
VDD = 15 V (Note 7)
UVDDD
Supply Circuit Under− Voltage
Protection
Detection Level
UVDDR
CSC − COM
Reset Level
11.0
−
13.5
V
UVBSD
Detection Level
10.0
−
12.5
V
UVBSR
Reset Level
10.5
−
13.0
V
30
−
−
ms
−
−
2.6
V
0.8
−
−
V
tFOD
Fault−Out Pulse Width
VIN(ON)
ON Threshold Voltage
VIN(OFF)
OFF Threshold Voltage
RTH
Resistance of Thermistor
Applied between IN(UH, VH, WH) − COM,
IN(UL, VL, WL) − COM
at TTH = 25°C (Note 8)
−
47
−
kW
at TTH = 100°C
−
2.9
−
kW
7. Short−circuit current protection is functioning only at the low−sides.
8. TTH is the temperature of thermistor itselt. To know case temperature (TC), please make the experiment considering your application.
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FNA41560T2
R−T Curve
600
500
20
450
16
Resistance (kW)
Resistance (kW)
550
400
350
300
250
200
R−T Curve in 50°C ~ 125°C
12
8
4
0
150
50
60
70
80
90 100 110 120
Temperature (°C)
100
50
0
−20 −10
0
10
20
30
40
50
60
70
80
90 100 110 120
TTH, Temperature (°C)
Figure 5. R−T Curve of The Built−In Thermistor
BOOTSTRAP DIODE PART
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VF
Forward Voltage
IF = 0.1 A, TC = 25°C
−
2.5
−
V
trr
Reverse−Recovery Time
IF = 0.1 A, dIF / dt = 50 A / μs,
TJ = 25°C
−
80
−
ns
Built−In Bootstrap Diode VF − IF Characteristic
1.0
0.9
0.8
IF (A)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
TC = 25°C
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
VF (V)
NOTE:
Built−in bootstrap diode includes around 15 W resistance characteristic.
Figure 6. Built−In Bootstrap Diode Characteristic
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FNA41560T2
RECOMMENDED OPERATING CONDITIONS
Value
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VPN
Supply Voltage
Applied between P − NU, NV, NW
−
300
400
V
VDD
Control Supply Voltage
Applied between VDD(H), VDD(L) −
COM
13.5
15.0
16.5
V
VBS
High−Side Bias Voltage
Applied between VB(U) − VS(U),
VB(V) − VS(V), VB(W) − VS(W)
13.0
15.0
18.5
V
dVDD / dt, dVBS / dt
Control Supply Variation
−1
−
1
V / ms
tdead
Blanking Time for Preventing
Arm − Short
For each input signal
1
−
−
ms
fPWM
PWM Input Signal
−40_C ≤ TC ≤ 125_C,
−40_C ≤ TJ ≤ 150_C
−
−
20
kHz
VSEN
Voltage for Current Sensing
Applied between NU, NV, NW − COM
(Including Surge−Voltage)
−4
−
4
V
PWIN(ON)
Minimun Input Pulse Width
VDD = VBS = 15 V, IC ≤ 15 A,
Wiring Inductance between NU, V, W
and DC Link N < 10 nH (Note 9)
0.5
−
−
ms
0.5
−
−
VDD = VBS = 15 V, IC ≤ 30 A,
Wiring Inductance between NU, V, W
and DC Link N < 10 nH (Note 9)
1.2
−
−
1.2
−
−
−40
−
150
PWIN(OFF)
PWIN(ON)
Minimun Input Pulse Width
PWIN(OFF)
TJ
Junction Temperature
ms
_C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
9. This product might not make right output response if input pulse width is less than the recommanded value.
Iorms, Allowable Output Current (Arms)
15
12
fSW = 5 kHz
9
6
VDC = 300 V, VDD = VBS = 15 V
Tj = 150°C, TC = 125°C
M.I. = 0.9, P.F. = 0.8
Sinusoidal PWM
3
0
0
20
40
fSW = 15 kHz
60
80
100
120
140
TC, Case Temperature (°C)
NOTE:
This allowable output current value is the reference data for the safe operation of this product. This may be different
from the actual application and operating condition.
Figure 7. Allowable Maximum Output Current
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FNA41560T2
MECHANICAL CHARACTERISTICS AND RATINGS
Parameter
Conditions
Device Flatness
See Figure 8
Mounting Torque
Mounting Screw: M3
See Figure 9
Min.
Typ.
Max.
Unit
0
−
+120
mm
Recommended 0.7 N/m
0.6
0.7
0.8
N/m
Recommended 7.1 kg/cm
6.2
7.1
8.1
kg/cm
−
11.00
−
g
Weight
Figure 8. Flatness Measurement Position
1
Figure 9. Mounting Screws Torque Order
NOTES:
10. Do not make over torque when mounting screws. Much mounting torque may cause ceramic cracks, as well as bolts and Al heat−sink
destruction.
11. Avoid one−sided tightening stress. Figure 9 shows the recommended torque order for the mounting screws. Uneven mounting can cause
the ceramic substrate damaged. The pre−screwing torque is set to 20 ∼ 30% of maximum torque rating.
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FNA41560T2
Time Charts of Protective Function
Input Signal
Protection
SET
RESET
RESET
Circuit State
UVDDR
b1
Control
a6
UVDDD
Supply Voltage
a3
a2
a7
a4
Output Current
a5
Fault Output Signal
a1 : Control supply voltage rises: after the voltage rises UVDDR, the circuits start to operate when the next input is applied.
a2 : Normal operation: IGBT ON and carrying current.
a3 : Under−voltage detection (UVDDD).
a4 : IGBT OFF in spite of control input condition.
a5 : Fault output operation starts with a fixed pulse width.
a6 : Under−voltage reset (UVDDR).
a7 : Normal operation: IGBT ON and carrying current by triggering next signal from LOW to HIGH.
Figure 10. Under−Voltage Protection (Low−Side)
Input Signal
Protection
Circuit State
RESET
SET
b5
b1
Control
Supply Voltage
RESET
b3
b6
b2
b4
Output Current
Fault Output Signal
High−level (no fault output )
b1 : Control supply voltage rises: after the voltage reaches UVBSR, the circuits start to operate when the next input is applied.
b2 : Normal operation: IGBT ON and carrying current.
b3 : Under−voltage detection (UVBSD).
b4 : IGBT OFF in spite of control input condition, but there is no fault output signal.
b5 : Under−voltage reset (UVBSR).
b6 : Normal operation: IGBT ON and carrying current by triggering next signal from LOW to HIGH.
Figure 11. Under−Voltage Protection (High−Side)
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FNA41560T2
Lower Arms
c6
Control Input
c7
Protection
Circuit state
SET
Internal IGBT
Gate−Emitter Voltage
c3
RESET
c4
c2
SC
c1
c8
Output Current
SC Reference
Voltage
Sensing Voltage
of Sense Resistor
Fault Output Signal
c5
CR Circuit Time
Constant Delay
(with the external sense resistance and RC filter connection)
c1 : Normal operation: IGBT ON and carrying current.
c2 : Short−circuit current detection (SC trigger).
c3 : All low−side IGBTs gate are hard interrupted.
c4 : All low−side IGBTs turn OFF.
c5 : Fault output operation starts with a fixed pulse width according to the condition of the external capacitor CFOD.
c6 : Input HIGH: IGBT ON state, but during the active period of fault output, the IGBT doesn’t turn ON.
c7 : Fault output operation finishes, but IGBT doesn’t turn on until triggering the next signal from LOW to HIGH.
c8 : Normal operation: IGBT ON and carrying current.
Figure 12. Short−Circuit Current Protection (Low−Side Operation only)
Input/Output Interface Circuit
+5 V (for MCU or Control power)
RPF = 10 kΩ
SPM
IN(UH) , IN (VH) , IN(WH)
IN (UL) , IN (VL) , IN( WL)
MCU
VFO
COM
NOTE:
RC coupling at each input might change depending on the PWM control scheme used in the application and the wiring
impedance of the application’s printed circuit board. The input signal section of the Motion SPM 45 product integrates
5 kW(typ.) pull−down resistor. Therefore, when using an external filtering resistor, please pay attention to the signal voltage
drop at input terminal.
Figure 13. Recommended MCU I/O Interface Circuit
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FNA41560T2
(26) VB(U)
CBS
CBSC
RS
(25) VS(U)
(20) IN(UH)
Gating UH
(24) VB(V)
CBSC
CBS
RS
(23) VS(V)
(19) IN(VH)
Gating VH
(22) VB(W)
CBSC
CBS
RS
Gating WH
(18) IN(WH)
(17) VDD(H)
+15 V
CPS
(21) VS(W)
CPS
CPS
CSPC15
CSP15
(15) COM
MCU
HVIC
VS(U)
VS(V)
IN(VH)
VS(V)
Gating WL
M
V (5)
VB(W)
VS(W)
IN(WH)
VDD
CDCS
OUT(WH)
VS(W)
VDC
W (6)
COM
LVIC
VDD
NU (7)
CSPC05 CSP05
(11) VFO
Fault
Gating VL
OUT(VH)
OUT(UL)
RS
Gating UL
U (4)
VS(U)
VB(V)
RPF
CBP F
OUT(UH)
IN(UH)
+5 V
(16) VDD(L)
P (3)
VB(U)
RSU
VFO
CPF
RS
(14) IN(UL)
RS
(13) IN(VL)
RS
(12) IN(WL)
CSC
(10) CSC
CPS CP S CPS
RF
RTH
Input Signal for
Short−Circuit Protection
OUT(VL)
IN(UL)
NV (8)
RSV
IN(VL)
IN(WL)
COM
OUT(WL)
CSC
NW (9)
RSW
(1) VTH
(2) RTH
THERMISTOR
Temp. Monitoring
U−Phase Current
V−Phase Current
W−Phase Current
Figure 14. Typical Application Circuit
NOTES:
12. To avoid malfunction, the wiring of each input should be as short as possible (less than 2 − 3 cm).
13. VFO output is an open−drain type. This signal line should be pulled up to the positive side of the MCU or control power supply with a resistor
that makes IFO up to 1 mA.
14. CSP15 of around seven times larger than bootstrap capacitor CBS is recommended.
15. Input signal is active−HIGH type. There is a 5 kW resistor inside the IC to pull down each input signal line to GND. RC coupling circuits is
recommanded for the prevention of input signal oscillation. RSCPS time constant should be selected in the range 50 ~ 150 ns (recommended
RS = 100 W, CPS = 1 nF).
16. To prevent errors of the protection function, the wiring around RF and CSC should be as short as possible.
17. In the short−circuit protection circuit, please select the RFCSC time constant in the range 1.5 ~ 2 ms. Do enough evaluaiton on the real system
because short−circuit protection time may vary wiring pattern layout and value of the RFCSC time constant.
18. The connection between control GND line and power GND line which includes the NU, NV, NW must be connected to only one point. Please
do not connect the control GND to the power GND by the broad pattern. Also, the wiring distance between control GND and power GND
should be as short as possible.
19. Each capacitor should be mounted as close to the pins of the Motion SPM 45 product as possible.
20. To prevent surge destruction, the wiring between the smoothing capacitor and the P & GND pins should be as short as possible. The use
of a high−frequency non−inductive capacitor of around 0.1 ~ 0.22 mF between the P and GND pins is recommended.
21. Relays are used in almost every systems of electrical equipment in home appliances. In these cases, there should be sufficient distance
between the MCU and the relays.
22. The zener diode or transient voltage suppressor should be adopted for the protection of ICs from the surge destruction between each pair
of control supply terminals (recommanded zener diode is 22 V / 1 W, which has the lower zener impedance characteristic than about 15 W).
23. Please choose the electrolytic capacitor with good temperature characteristic in CBS. Also, choose 0.1 ~ 0.2 mF R−category ceramic
capacitors with good temperature and frequency characteristics in CBSC.
www.onsemi.com
13
FNA41560T2
PACKAGE MARKING AND ORDERING INFORMATION
Device
Device Marking
Package
Shipping
FNA41560T2
FNA41560T2
SPMAA−C26 / 26LD, PDD STD CERAMIC TYPE,
LONG LEAD DUAL FORM TYPE
(Pb−Free)
12 Units / Rail
SPM is registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or
other countries.
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14
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SPMAA−C26 / 26LD, PDD STD CERAMIC TYPE, LONG LEAD DUAL FORM TYPE
CASE MODFC
ISSUE O
DATE 31 JAN 2017
DOCUMENT NUMBER:
DESCRIPTION:
98AON13555G
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
SPMAA−C26 / 26LD, PDD STD CERAMIC TYPE, LONG LEAD DUAL
PAGE 1 OF 1
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