FNB81060T3
Motion SPM) 8 Series
FNB81060T3 is a Motion SPM 8 module providing a
fully−featured, high−performance inverter output stage for AC
Induction, BLDC, and PMSM motors. These modules integrate
optimized gate drive of the built−in IGBTs to minimize EMI and
losses, while also providing multiple on−module protection features
including under−voltage lockouts, inter−lock function, over−current
shutdown, thermal monitoring of drive IC, and fault reporting. The
built−in, high−speed HVIC requires only a single supply voltage and
translates the incoming logic−level gate inputs to the high−voltage,
high−current drive signals required to properly drive the module’s
robust shortcircuit−rated IGBTs. Separate negative IGBT terminals
are available for each phase to support the widest variety of control
algorithms.
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Features
• UL Certified No. E209204 (UL1557)
• 600 V − 10 A 3−Phase IGBT Inverter Including Control IC for Gate
•
•
•
•
•
•
•
•
•
Drive and Protections
Low−Loss, Short−Circuit Rated IGBTs
Separate Open−Emitter Pins from Low−Side IGBTs for Three−Phase
Current Sensing
Active−high Interface, works with 3.3 / 5 V Logic, Schmitt−trigger
Input
HVIC for Gate Driving, Under−Voltage, Over Current and
Short−Circuit Current Protection
Fault Output for Under−Voltage, Over Current and Short−Circuit
Current Protection
Inter−Lock Function to Prevent Short−Circuit
Shut−Down Input
HVIC Temperature−Sensing Built−In for Temperature Monitoring
Isolation Rating: 1500 Vrms / min.
3D Package Drawing
(Click to Activate 3D Content)
SPMFA−A25
CASE MODEZ
MARKING DIAGRAM
Applications
• Motion Control − Home Appliance / Industrial Motor / HVAC
Related Resources
• AN−9112 * Smart Power Module, Motion SPM 8 Series User’s
Guide
Integrated Power Functions
• 600 V − 10 A IGBT Inverter for Three Phase DC / AC Power
ON
NB81060T3
XXX
Y
WW
= ON Semiconductor Logo
= Specific Device Code
= Lot Number
= Year
= Work Week
Conversion (Please refer to Figure 2)
Integrated Drive, Protection and System Control Functions
• For Inverter High−side IGBTs: gate drive circuit, high−voltage
•
isolated high−speed level shifting control circuit Under−Voltage
Lock−Out (UVLO) protection (Note: Available bootstrap circuit
example is given in Figures 4 and 16)
Control Circuit Under−Voltage Lock−Out (UVLO) protection
© Semiconductor Components Industries, LLC, 2019
August, 2019 − Rev. 2
1
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
Publication Order Number:
FNB81060T3/D
FNB81060T3
• For Inverter Low−side IGBTs: gate drive circuit, Over Current
•
•
Protection (OCP), Short−Circuit Protection (SCP) control supply
circuit Under−Voltage Lock−Out (UVLO) protection
Fault Signaling: corresponding to UVLO (low−side supply) and SC
faults
Input Interface: High−active interface, works with 3.3 / 5 V logic,
Schmitt trigger input
PIN CONFIGURATION
(25) VBU
(1) P
(24) COM
(23) INUH
(22) INUL
(21) VDD
(20) /SDU
(2) U, VSU
Case temperature (Tc)
Detecting point
(3) NU
(19) VBV
(4) V, VSV
(18) INVH
(17) INVL
(16) VDD
(15) /SDV
(5) NV
(14) VBW
(13) INWH
(12) INWL
(11) VDD
(10) Csc
(9) /FO,/SDW,VTS
(8) COM
(6) W, VSW
(7) NW
Figure 1. Pin Configuration − Top View
Table 1. PIN DESCRIPTIONS
Pin Number
Pin Name
1
P
2
U, VSU
3
NU
4
V, VSV
5
NV
6
W, VSW
7
NW
Pin Description
Positive DC−Link Input
Output for U Phase
Negative DC−Link Input for U Phase
Output for V Phase
Negative DC−Link Input for V Phase
Output for W Phase
Negative DC−Link Input for W Phase
8
COM
9
/FO, /SDW, VTS
Common Supply Ground
10
CSC
Shut Down Input for Over Current and Short Circuit Protection
Fault Output, Shut−Down Input for W Phase, Temperature Output of Drive IC
11
VDD
Common Bias Voltage for IC and IGBTs Driving
12
INWL
Signal Input for Low−Side W Phase
13
INWH
Signal Input for High−Side W Phase
14
VBW
High−Side Bias Voltage for W−Phase IGBT Driving
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FNB81060T3
Table 1. PIN DESCRIPTIONS
Pin Number
Pin Name
Pin Description
15
/SDV
Shut−Down Input for V Phase
16
VDD
Common Bias Voltage for IC and IGBTs Driving
17
INVL
Signal Input for Low−Side V Phase
18
INVH
Signal Input for High−Side V Phase
19
VBV
High−Side Bias Voltage for V−Phase IGBT Driving
20
/SDU
Shut−Down Input for U Phase
21
VDD
Common Bias Voltage for IC and IGBTs Driving
22
INUL
Signal Input for Low−Side U Phase
23
INUH
Signal Input for High−Side U Phase
24
COM
Common Supply Ground
25
VBU
High−Side Bias Voltage for U−Phase IGBT Driving
INTERNAL EQUIVALENT CIRCUIT AND INPUT/OUTPUT PINS
P
VBU
INUH
INUL
VDD
/SDU
COM
VB
HIN
LIN
HO
VDD
/SDU
COM
U,VSU
VS
LO
NU
VBV
INVH
INVL
VDD
/SDV
VB
HIN
LIN
VDD
/SDV
COM
HO
V,VSV
VS
LO
Nv
VBW
INWH
INWL
VDD
Csc
/FO, /SDW, VTS
COM
VB
HIN
LIN
HO
VDD
Csc
VS
/FO, /SDW, VTS
COM
W,VSW
LO
Nw
Notes:
1. Inverter high−side is composed of three IGBTs, freewheeling diodes.
2. Inverter low−side is composed of three IGBTs, freewheeling diodes.
3. Inverter power side is composed of four inverter DC−link input terminals and three inverter output terminals.
Figure 2. Internal Block Diagram
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FNB81060T3
Table 2. ABSOLUTE MAXIMUM RATINGS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Conditions
Rating
Unit
INVERTER PART
VPN
VPN(Surge)
VCES
Supply Voltage
Applied between P − NU, NV, NW
450
V
Supply Voltage (Surge)
Applied between P − NU, NV, NW
500
V
600
V
± IC
Each IGBT Collector Current
TC = 25°C, TJ ≤ 150°C (Note 1)
10
A
± ICP
Each IGBT Collector Current (Peak)
TC = 25°C, TJ ≤ 150°C, Under 1 ms Pulse Width
(Note 1)
20
A
−40 ~ 150
_C
TJ
Collector − Emitter Voltage
Operating Junction Temperature
CONTROL PART
VDD
Control Supply Voltage
Applied between VDD − COM
20
V
VBS
High−Side Control Bias Voltage
Applied between VBU − VSU, VBV − VSV, VBW −
VSW
20
V
VIN
Input Signal Voltage
Applied between INUH, INVH, INWH, INUL, INVL,
INWL − COM
−0.3 ~ VDD + 0.3
V
VFS
Function Supply Voltage
Applied between /FO, /SDW, VTS − COM
−0.3 ~ VDD + 0.3
V
IFO
Fault Current
Sink Current at /FO, /SDW, VTS pin
2
mA
VSC
Current Sensing Input Voltage
Applied between CSC − COM
−0.3 ~ VDD + 0.3
V
400
V
−40 ~ 125
_C
−40 ~ 125
_C
1600
Vrms
TOTAL SYSTEM
VPN(PROT)
TC
Self Protection Supply Voltage Limit
(Short Circuit Protection Capability)
VDD = VBS = 13.5 ~ 16.5 V, TJ = 150°C, Non−
Repetitive, < 2 ms
Module Case Operation Temperature
See Figure 1
TSTG
Storage Temperature
VISO
Isolation Voltage
Connect Pins to Heat Sink Plate
AC 60 Hz, Sinusoidal, AC 1 Minute, Connection
Pins to Heat Sink Plate
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. These values had been made an acquisition by the calculation considered to design factor.
Table 3. THERMAL RESISTANCE
Symbol
Rth(j−c)Q
Rth(j−c)F
Parameter
Junction−to−Case Thermal
Resistance (Note 2)
Conditions
Min
Typ
Max
Unit
Inverter IGBT part, (Per Module)
−
−
3.40
_C/W
Inverter FWDi part, (Per Module)
−
−
3.86
_C/W
2. For the measurement point of case temperature (TC), please refer to Figure 1.
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FNB81060T3
Table 4. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified.)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
INVERTER PART
VCE(SAT)
Collector − Emitter Saturation VDD = VBS = 15 V, VIN = 5 V,
IC = 8 A
Voltage
TJ = 25°C
−
1.50
2.10
V
TJ = 150°C
−
1.80
−
V
FWDi Forward Voltage
TJ = 25°C
−
1.90
2.50
V
TJ = 150°C
−
1.80
−
V
0.25
0.75
1.25
ms
−
0.15
0.45
ms
tOFF
−
0.50
1.00
ms
tC(OFF)
−
0.10
0.40
ms
trr
−
0.10
−
ms
0.25
0.75
1.25
ms
−
0.15
0.45
ms
tOFF
−
0.50
1.00
ms
tC(OFF)
−
0.10
0.40
ms
trr
−
0.10
−
ms
−
−
1.00
mA
VF
HS
tON
VIN = 0 V, IF = 8 A
Switching Times
VPN = 400 V, VDD = VBS = 15 V, IC = 10 A, TJ = 25°C
VIN = 0 V ↔ 5 V, Inductive load (Note 3)
tC(ON)
LS
tON
VPN = 400 V, VDD = VBS = 15 V, IC = 10 A, TJ = 25°C
VIN = 0 V ↔ 5 V, Inductive load (Note 3)
tC(ON)
ICES
Collector − Emitter Leakage
Current
VCE = VCES
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. tON and tOFF include the propagation delay of the internal drive IC. tC(ON) and tC(OFF) are the switching times of IGBT under the given
gate−driving condition internally. For the detailed information, please see Figure 3.
HINx
LINx
t rr
t off
t on
100% ICx
I Cx
90% I Cx
10% VCEx
10% I Cx
v CEx
10% VCEx
10% ICx
t c(on)
t c(off)
Figure 3. Switching Time
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FNB81060T3
One−Leg Diagram of SPM 8
IC
P
CBS
VB
LS Switching
HO
HIN
HS Switching
VPN
U,V,W
VS
V
Inductor
LIN
LS Switching
400V
VDD
VIN
5V
/Fo, /SDw, V TS
VDD
0V
10kW
Csc
COM
V
+15V
+5V
HS Switching
LO
NU,V,W
V
Figure 4. Example Circuit for Switching Test
Inductive Load, VPN = 300V, VDD=15V, TJ=25 °C
500
IGBT Turn−on, Eon
IGBT Turn−off, Eoff
FRD Turn−off, Erec
SWITCHING LOSS ESW [uJ]
400
300
200
100
300
200
100
0
0
0
1
2
3
4
5
6
7
8
9
10
11
0
1
COLLECTOR CURRENT, IC [AMPERES]
2
3
4
5
6
7
4.8
3.3V pull−up with 4.7kohm
5V pull−up with 10kohm
4.3
3.8
3.3
2.8
2.3
1.8
1.3
0
25
8
9
COLLECTOR CURRENT, IC [AMPERES]
Figure 5. Switching Loss Characteristics
VTS from Pin 9 [V]
SWITCHING LOSS ESW [uJ]
400
Inductive Load, VPN = 300V, VDD=15V, TJ=150 °C
500
IGBT Turn−on, Eon
IGBT Turn−off, Eoff
FRD Turn−off, Erec
50
75
T HVIC [ C]
100
125
O
Figure 6. V−T Curve of Temperature Output of IC
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6
150
10
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FNB81060T3
Table 5. ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CONTROL PART
IQDD
Quiescent VDD Supply
Current
VDD = 15 V, IN(UH,VH,WH,UL,VL,WL) = 0 V
VDD − COM
−
−
1.7
mA
IPDD
Operating VDD Supply
Current
VDD = 15 V, fPWM = 20 kHz, duty = 50%,
applied to one PWM signal input
VDD − COM
−
−
2.2
mA
IQBS
Quiescent VBS Supply
Current
VBS = 15 V, IN(UH, VH, WH) = 0 V
VB(U) − VS(U), VB(V) −
VS(V), VB(W) − VS(W)
−
−
100
mA
IPBS
Operating VBS Supply
Current
VDD = VBS = 15 V, fPWM = 20 kHz,
duty = 50%, applied to one PWM signal
input for high − side
VB(U) − VS(U), VB(V) −
VS(V), VB(W) − VS(W)
−
−
600
mA
VFOH
Fault Output Voltage
VSC = 0 V, VF Circuit: 10 kW to 5 V Pull−up
3.81
−
−
V
VSC = 1 V, VF Circuit: 10 kW to 5 V Pull−up
−
−
0.5
V
0.46
0.49
0.52
V
Detection level
10.0
11.5
13.0
V
VFOL
VSC(ref)
Short−Circuit Trip Level VDD = 15 V (Note 4)
UVDDD
Supply Circuit Under−
Voltage Protection
Reset level
10.5
12.0
13.5
V
UVBSD
Detection level
9.5
11.0
12.5
V
UVBSR
Reset level
10.0
11.5
13.0
V
VDD = VBS = 15 V, THVIC = 25°C
−
82.5
−
mA
VDD = VBS = 15 V, THVIC = 75°C
−
207.5
−
mA
VDD = VBS = 15 V, THVIC = 25°C, 10 kW to 5 V Pull−up
−
4.18
−
V
VDD = VBS = 15 V, THVIC = 75°C, 10 kW to 5 V Pull−up
−
2.93
−
V
Fault−Out Pulse Width
40
−
−
ms
Shut−down Reset level Applied between /FO − COM
−
−
2.4
V
0.8
−
−
V
UVDDR
IFO_T
VFO_T
tFOD
VFSDR
VFSDD
HVIC Temperature
Sensing Current
HVIC Temperature
Sensing Voltage See
Figure 7
Shut−down Detection
level
VIN(ON)
ON Threshold Voltage
VIN(OFF)
OFF Threshold Voltage
Applied between IN(UH), IN(VH), IN(WH), IN(UL), IN(VL), IN(WL) − COM
−
−
2.4
V
0.8
−
−
V
−
280
−
W
BOOTSTRAP DIODE PART
RBS
Bootstrap Diode Resis- VDD = 15 V, TJ = 25°C
tance
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Short−circuit current protection function is for all six IGBTs if the /FO, /SDW, VTS pin is connected to /SDx pins.
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FNB81060T3
0.06
0.05
IF [A]
0.04
0.03
0.02
0.01
o
T J =25 C, V DD =15V
0.00
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
V F [V]
Figure 7. Built−In Bootstrap Diode Characteristics
Table 6. RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
−
300
400
V
VPN
Supply Voltage
Applied between P − NU, NV, NW
VDD
Control Supply Voltage
Applied between VDD − COM
14.0
15
16.5
V
VBS
High − Side Bias Voltage
Applied between VBU − VSU, VBV −VSV, VBW − VSW
13.0
15
18.5
V
−1
−
1
V/ms
For each input signal
0.5
−
−
ms
Voltage for Current Sensing
Applied between NU, NV, NW − COM (Including surge
voltage)
−4
4
V
Minimun Input Pulse Width
VDD = VBS = 15 V, IC ≤ 20 A, Wiring Inductance
between NU, V, W and DC Link N < 10nH (Note 5)
0.7
−
−
ms
0.7
−
−
dVDD / dt, Control Supply Variation
dVBS / dt
tdead
VSEN
PWIN(ON)
Blanking Time for Preventing
Arm − Short
PWIN(OFF)
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. This product might not make response if input pulse width is less than the recommended value.
Table 7. MECHANICAL CHARACTERISTICS AND RATINGS
Parameter
Conditions
Device Flatness
See Figure 8
Mounting Torque
Mounting Screw: M3
See Figure 9 (Note 6, 7)
Min
Typ
Max
Unit
−50
−
100
mm
Recommended 0.7 N • m
0.6
0.7
0.8
N•m
Recommended 7.1 kg • cm
5.9
6.9
7.9
kg • cm
−
5.0
−
g
Weight
6. Do not make over torque when mounting screws. Much mounting torque may cause package cracks, as well as bolts and Al heat−sink
destruction.
7. Avoid one side tightening stress. Figure 9 shows the recommended torque order for mounting screws. Uneven mounting can cause the DBC
substrate of package to be damaged. The pre−screwing torque is set to 20 ~ 30% of maximum torque rating.
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FNB81060T3
Figure 8. Flatness Measurement Position
Pre−Screwing: 1 → 2
Final Screwing: 2 → 1
2
1
Figure 9. Mounting Screws Torque Order
PACKAGE MARKING AND ORDERING INFORMATION
Device
Device Marking
Package
Shipping
FNB81060T3
NB81060T3
SPMFA−A25
15 Units / Rail
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FNB81060T3
TIME CHARTS OF PROTECTIVE FUNCTION
Input Signal
Protection
Circuit State
RESET
SET
RESET
UVDDR
a1
Control
Supply Voltage
a6
UVDDD
a3
a2
a7
a4
Output Current
a5
Fault Output Signal
a1: Control supply voltage rises: after the voltage rises UVDDR, the circuits start to operate when next input is applied.
a2: Normal operation: IGBT ON and carrying current.
a3: Under−voltage detection (UVDDD).
a4: IGBT OFF in spite of control input condition.
a5: Fault output operation starts.
a6: Under−voltage reset (UVDDR).
a7: Normal operation: IGBT ON and carrying current.
Figure 10. Under−Voltage Protection (Low−Side)
Input Signal
Protection
Circuit State
RESET
SET
RESET
UVBSR
Control
Supply Voltage
b5
b1
UVBSD
b3
b6
b2
b4
Output Current
High−level (no fault output)
Fault Output Signal
b1: Control supply voltage rises: after the voltage reaches UVBSR, the circuits start to operate when next input is applied.
b2: Normal operation: IGBT ON and carrying current.
b3: Under−voltage detection (UVBSD).
b4: IGBT OFF in spite of control input condition, but there is no fault output signal.
b5: Under−voltage reset (UVBSR).
b6: Normal operation: IGBT ON and carrying current.
Figure 11. Under−Voltage Protection (High−Side)
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FNB81060T3
Hin
Lin
ÉÉ
É
d3
Ho
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
d1
Lo
d2
ÉÉÉ
ÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
d4
d5
Hin : High−side Input Signal
Lin : Low−side Input Signal
Ho : High−side IGBT Gate Voltage
Lo : Low−side IGBT Gate Voltage
/Fo : Fault Output
/Fo
d1: High Side First − Input − First − Output Mode
d2: Low Side Noise Mode: No LO
d3: High Side Noise Mode: No HO
d4: Low Side First − Input − First − Output Mode
d5: IN − Phase Mode: No HO
Figure 12. Inter−Lock Function
HIN
LIN
Smart Turn−off
HO
Soft Off
Activated by next input
after fault clear
LO
Over−Current
Detection
No Output
CSC
/FO
HIN : High−side Input Signal
LIN : Low−side Input Signal
HO : High−Side Output Signal
LO : Low−Side Output Signal
CSC : Over Current Detection Input
/FO : Fault Out Function
Figure 13. Fault−Out Function by Over Current Protection
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FNB81060T3
HIN
LIN
Activated by next
input after fault
clear
No Output
HO
Smart
Turn−off
Soft Off
LO
C SC
/SD x
External
shutdown input
HIN : High−side Input Signal
LIN : Low−side Input Signal
HO : High−Side Output Signal
LO : Low−Side Output Signal
CSC : Over Current Detection Input
/SDx : Shutdown Input Function
Figure 14. Shutdown Input Function by External Command
INPUT/OUTPUT INTERFACE CIRCUIT
5 V Line (MCU or Control power)
R PF = 10k W
SPM
MCU
IN UH , IN
VH
IN UL , IN
VL
/FO, /SD
, IN
, IN
W,
V
WH
WL
TS
COM
NOTE:
RC coupling at each input (parts shown dotted) might change depending on the PWM control scheme used in the
application and the wiring impedance of the application’s printed circuit board. The input signal section of the SPM 8
product integrates 5 kW (typ.) pull−down resistor. Therefore, when using an external filtering resistor, please pay
attention to the signal voltage drop at input terminal.
Figure 15. Recommended MCU I/O Interface Circuit
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FNB81060T3
P
15V
VBU
VB
Gating UH
Gating UL
CBS
RS
CBSC
INUH
INUL
RS
CPS
VDD
CPS
/SDU
COM
HO
HIN
LIN
VS
VDD
/SD U
COM
LO
U,VSU
Nu
M
C
U
VBV
CBS
RS
Gating VH
Gating VL
CBSC
INVH
INVL
RS
CPS
VDD
CPS
/SDV
5V
CBS
RS
INWH
INWL
VDD
Fault
/Fo, /SDw, VTS
Csc
CPS
CPF
HIN
VS
LIN
VDD
/SDV
LO
V,VSV
CSP15
COM
RF
CSPC15
D
M
CDCS
VDC
Nv
VB
HO
CBSC
RS
CPS
HO
COM
VBW
Gating WH
Gating WL
VB
HIN
LIN
W,VSW
VS
VDD
/Fo, /SDw, VTS
A
LO
Csc
COM
Nw
CSC
RSU
E
RSV
B
Power
GND Line
RSW
C
W−Phase Current
V−Phase Current
U−Phase Current
Input Signal for
Short−Circuit Protection
Control
GND Line
Figure 16. Typical Application Circuit
NOTES:
8. To avoid malfunction, the wiring of each input should be as short as possible (Less than 2 ~ 3 cm).
9. /FO is open−drain type. This signal line should be pulled up to the positive side of the MCU or control power supply with a resistor that makes
IFO up to 2 mA. (Figure 15.)
10. CSP15 of around seven times larger than bootstrap capacitor CBS is recommended.
11. Input signal is active−HIGH type. There is a 5 kW resistor inside the IC to pull down each input signal line to GND. RC coupling circuits are
recommended for the prevention of input signal oscillation. RSCPS time constant should be selected in the range 50 ~ 150 ns (Recommended
RS = 100 W, CPS = 1 nF).
12. Each wiring pattern inductance of A point should be minimized (Recommend less than 10nH). Use the shunt resistor RS(U/V/W) of surface
mounted (SMD) type to reduce wiring inductance. To prevent malfunction, wiring of point E should be connected to the terminal of the shunt
resistor RS(U/V/W) as close as possible.
13. To prevent errors of the protection function, the wiring of B, C, and D point should be as short as possible.
14. In the short−circuit current protection circuit, please select the RFCSC time constant in the range 1.5 ~ 2 ms. Do enough evaluation on the
real system because short−circuit protection time may vary wiring pattern layout and value of the RF and CSC time constant.
15. The connection between control GND line and power GND line which includes the NU, NV, NW must be connected to only one point. Please
do not connect the control GND to the power GND by the broad pattern. Also, the wiring distance between control GND and power GND
should be as short as possible.
16. Each capacitor should be mounted as close to the pins of the Motion SPM 8 product as possible.
17. To prevent surge destruction, the wiring between the smoothing capacitor and the P and GND pins should be as short as possible. The use
of a high frequency non−inductive capacitor of around 0.1 ~ 0.22 mF between the P and GND pins is recommended.
18. Relays are used in almost every systems of electrical equipments of home appliances. In these cases, there should be sufficient distance
between the CPU and the relays.
19. The zener diode or transient voltage suppressor should be adapted for the protection of ICs from the surge destruction between each pair
of control supply terminals (Recommended zener diode is 22 V / 1 W, which has the lower zener impedance characteristic than about 15 W).
20. Please choose the electrolytic capacitor with good temperature characteristic in CBS. Also, choose 0.1 ~ 0.2 mF R−category ceramic
capacitors with good temperature and frequency characteristics in CBSC.
21. For the detailed information, please refer to the application notes.
22. /FO and /SD must be connected as short as possible.
SPM is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
www.onsemi.com
13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SPMFA−A25 / 25LD, FULL PACK, DIP TYPE, SPM8 SERIES
CASE MODEZ
ISSUE O
DOCUMENT NUMBER:
DESCRIPTION:
98AON13572G
DATE 31 JAN 2017
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
SPMFA−A25 / 25LD, FULL PACK, DIP TYPE, SPM8 SERIES
PAGE 1 OF 1
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