FOD2200SV

FOD2200 Low Input Current Logic Gate Optocouplers Features Description ■ 1kV/µs minimum common mode rejection The FOD2200 is an optically coupled logic gate that combine an AlGaAs LED and an integrated high gain photo detector. The detector has a three state output stage and has a detector threshold with hysteresis. The three state output eliminates the need for a pullup resistor and allows for direct drive of data busses. The hysteresis provides differential mode noise immunity and eliminates the potential for output signal chatter. ■ Compatible with LSTTL, TTL, and CMOS logic ■ Wide VCC range (4.5V to 20V) ■ 2.5Mbd guaranteed over temperature ■ Low input current (1.6mA) ■ Three state output (no pullup resistor required) ■ Guaranteed performance from 0°C to 85°C ■ Hysteresis ■ Safety and regulatory approved – UL1577, 5000 VRMS for 1 min. – IEC60747-5-2 ■ >8.0mm clearance and creepage distance (option ‘T’ or ‘TS’) ■ 1,414V Peak Working Insulation Voltage (VIORM) Applications ■ Isolation of high speed logic systems The Electrical and Switching Characteristics of the FOD2200 are guaranteed over the temperature range of 0°C to 85°C and a VCC range of 4.5V to 20V. Low IF and wide VCC range allow compatibility with TTL, LSTTL, and CMOS logic and result in lower power consumption compared to other high speed opto-couplers. Logic signals are transmitted with a maximum propagation delay of 300ns. The FOD2200 is useful for isolating high speed logic interfaces, buffering of input and output lines, and implementing isolated line receivers in high noise environments. ■ Computer peripheral interfaces Truth Table (Positive Logic) ■ Microprocessor system interfaces ■ ■ ■ ■ Ground loop elimination Pulse transformer replacement Isolated bus driver High speed line receiver LED Enable Output On H Z Off H Z On L H Off L L Functional Block Diagram and Schematic Package Outlines ICC 8 VCC NC 1 8 6 VE CATHODE 3 + VF SHIELD IO 2 7 IE – NC 4 8 IF 7 VO ANODE 2 VCC 6 3 5 GND SHIELD 5 8 VO VE GND 8 8 1 ©2004 Fairchild Semiconductor Corporation FOD2200 Rev. 1.0.4 1 1 1 www.fairchildsemi.com FOD2200 — Low Input Current Logic Gate Optocouplers August 2010 As per IEC 60747-5-2. This optocoupler is suitable for “safe electrical insulation” only within the safety limit data. Compliance with the safety ratings shall be ensured by means of protective circuits. Symbol Parameter Min. Typ. Max. Unit Installation Classifications per DIN VDE 0110/1.89 Table 1 For Rated Mains Voltage < 150Vrms I–IV For Rated Mains Voltage < 300Vrms I–IV For Rated Mains Voltage < 450Vrms I–III For Rated Mains Voltage < 600Vrms I–III For Rated Mains Voltage < 1000Vrms (Option T, TS) I–III Climatic Classification 40/85/21 Pollution Degree (DIN VDE 0110/1.89) 2 CTI Comparative Tracking Index 175 VPR Input to Output Test Voltage, Method b, VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec., Partial Discharge < 5pC 2651 Input to Output Test Voltage, Method a, VIORM x 1.5 = VPR, Type and Sample Test with tm = 60 sec.,Partial Discharge < 5 pC 2121 VIORM Max Working Insulation Voltage 1,414 Vpeak VIOTM Highest Allowable Over Voltage 6000 Vpeak External Creepage 8 mm External Clearance 7.4 mm 10.16 mm 0.5 mm Case Temperature 150 °C Input Current 10 mA Output Power (Duty Factor ≤ 2.7%) 150 mW 109 Ω External Clearance (for Option T or TS - 0.4” Lead Spacing) Insulation Thickness Safety Limit Values – Maximum Values Allowed in the Event of a Failure TCase IS,INPUT PS,OUTPUT RIO Insulation Resistance at TS, VIO = 500V ©2004 Fairchild Semiconductor Corporation FOD2200 Rev. 1.0.4 www.fairchildsemi.com 2 FOD2200 — Low Input Current Logic Gate Optocouplers Safety and Insulation Ratings Symbol Parameter Value Units TSTG Storage Temperature -40 to +125 °C TOPR Operating Temperature -40 to +85 °C TSOL Lead Solder Temperature (1.6mm below seating plane) 260 for 10 sec °C Peak Transient Input Current (≤1µs PW, 300pps) 1.0 A IF Average Forward Input Current 10 mA VR Reverse Input Voltage 5.0 V PD Output Power Dissipation (No derating required up to 85°C) 45 mW 0 to 20 V EMITTER IF (PK) DETECTOR VCC Supply Voltage IO Average Output Current 25 mA VE Three State Enable Voltage -0.5 to 20 V VO Output Voltage -0.5 to 20 V PD Output Power Dissipation (No derating required up to 85°C) 150 mW Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Min. Max. Units 1.6* 5 mA 0.1 mA IF(ON) Forward Input Current IF(OFF) Forward Input Current VCC Supply Voltage, Output 4.5 20 V VEL Enable Voltage, LOW Level 0 0.8 V VEH Enable Voltage, HIGH Level 2.0 20 V 0 +85 °C TA Operating Temperature N Fan Out (TTL Load) 4 *The initial switching threshold is 1.6mA or less. It is recommended that 2.2mA be used to permit at least a 20% CTR degradation guardband. ©2004 Fairchild Semiconductor Corporation FOD2200 Rev. 1.0.4 www.fairchildsemi.com 3 FOD2200 — Low Input Current Logic Gate Optocouplers Absolute Maximum Ratings (TA = 25°C unless otherwise specified) Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. VEH = 2V to 20V, VEL = 0V to 0.8V, IF(OFF) = 0 mA to 0.1mA unless otherwise specified.)(1) Individual Component Characteristics Symbol Parameter Test Conditions Min. Typ.* Max. Unit 1.75 V EMITTER VF Input Forward Voltage IF = 5mA BVR Input Reverse Breakdown Voltage IR = 10µA CIN Input Capacitance TA = 25°C ∆VF/∆TA Input Diode Temperature Coefficient 1.40 1.7 5.0 V Pins 2 & 3, VF = 0, f = 1MHz IF = 5mA 60 pF -1.4 mV/°C DETECTOR ICCH ICCL High Level Supply Current IF = 5mA, IO = Open, VE = Don’t Care VCC = 5.5V 3.5 4.5 VCC = 20V 4.0 6.0 Low Level Supply Current IF = 0, IO = Open, VE = Don’t care VCC = 5.5V 4.4 6.0 VCC = 20V 5.2 7.5 -0.1 -0.32 mA 20 µA IEL Low Level Enable Current VE = 0.4V IEH High Level Enable Current VE = 2.7V VE = 5.5V High Level Enable Voltage VEL Low Level Enable Voltage mA 100 VE = 20V VEH mA 0.005 250 2.0 V 0.8 V Switching Characteristics (TA = 0°C to +85°C, IF(ON) = 1.6mA to 5mA, IF(OFF) = 0 to 0.1mA, VCC = 4.5V to 20V unless otherwise specified.) Symbol AC Characteristics Test Conditions (2)(4) Min. Typ.* Max. Unit TPLH Propagation Delay Time to Output High Level With Peaking Capacitor (Fig. 1) 120 300 ns TPHL Propagation Delay Time to Output Low Level With Peaking Capacitor(3)(4) (Fig. 1) 180 300 ns Output Rise Time (10% to 90%) (5) (Fig. 1) 80 ns (Fig. 1) tr tf Output Fall Time (90% to 10%) (6) 25 ns tPZH Enable Propagation Delay Time to Output High Level (Fig. 2) 40 ns tPZL Enable Propagation Delay Time to Output Low Level (Fig. 2) 50 ns TPHZ Disable Propagation Delay Time from (Fig. 2) Output High Level 95 ns TPLZ Disable Propagation Delay Time from (Fig. 2) Output Low Level 80 ns |CMH| Common Mode Transient Immunity (at Output High Level) |CML| Common Mode Transient Immunity (at Output Low Level) TA =25°C, VOH (Min.) = 2.0V, VCC = 5V(7) (Fig. 3) TA =25°C, IF = 0mA VOL (Max.) = 0.8 V, VCC = 5V(8) (Fig. 3) IF = 1.6mA, |VCM| = 50V 1,000 IF = 5mA, |VCM| = 1,000V 10,000 |VCM| = 50V 1,000 |VCM| = 1,000V 10,000 V/µs V/µs *Typical values at TA = 25°C, VCC = 5V, IF(ON) = 3mA unless otherwise specified. ©2004 Fairchild Semiconductor Corporation FOD2200 Rev. 1.0.4 www.fairchildsemi.com 4 FOD2200 — Low Input Current Logic Gate Optocouplers Electrical Characteristics (TA = 0°C to +85°C, VCC = 4.5V to 20V, IF(ON) = 1.6mA to 5mA, Transfer Characteristics (TA = 0°C to +85°C, VCC = 4.5V to 20V, IF(ON) = 1.6mA to 5mA, VEH = 2V to 20V, VEL = 0V to 0.8V, IF(OFF) = 0mA to 0.1mA unless otherwise specified.)(1) Symbol IOHH DC Characteristics Test Conditions Min. Typ.* Max. Unit µA Output Leakage Current (VOUT > VCC) VCC = 4.5V, IF = 5mA VO = 5.5V 2.0 100 VO = 20V 2.5 500 VOL Low Level Output Voltage VCC = 4.5 V, IF = 0mA, VE = 0.4 V, IOL = 6.4mA(2) 0.33 0.5 V IFT Input Threshold Current VCC = 4.5V, VO = 0.5V, VE = 0.4V, IOL = 6.4mA 1.6 mA VOH Logic High Output Voltage IOH = -2.6mA IOZL High Impedance State Output Current VO = 0.4V, VEN = 2V, IF = 5mA -20 µA IOZH High Impedance State Output Current VO = 2.4 V, VEN = 2 V, IF = 5mA 20 µA VO = 5.5 V, VEN = 2 V, IF = 5mA 100 2.4 VCC – 1.8 VO = 20 V, VEN = 2 V, IF = 5mA IOSL IOSH IHYS Logic Low Short Circuit Output Current(10) Logic High Short Circuit Output Current(10) Input Current Hysteresis V 500 VO = VCC = 5.5V, IF = 0mA 25 VO = VCC = 20V, IF = 0mA 40 VCC = 5.5V, IF = 5mA, VO = GND -10 VCC = 20V, IF = 5mA, VO = GND -25 mA mA VCC = 4.5V 0.03 mA Isolation Characteristics (TA = 0°C to +85°C unless otherwise specified) Symbol VISO Characteristics Withstand Insulation Test Voltage Test Conditions RH < 50%, TA = 25°C, t = 1 Min. min.(9) 5000 500 VDC(9) RI-O Resistance (Input to Output) VI-O = CI-O Capacitance (Input to Output) VI-O = 0V, f = 1MHz(9) Typ.* Max. Unit VRMS 1012 Ω 0.6 pF *Typical values at TA = 25°C, VCC = 5V, IF(ON) = 3mA unless otherwise stated. Notes: 1. The VCC supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package VCC and GND pins of each device. 2. tPLH – Propagation delay is measured from the 50% level on the LOW to HIGH transition of the input current pulse to the 1.3V level on the LOW to HIGH transition of the output voltage pulse. 3. tPHL – Propagation delay is measured from the 50% level on the HIGH to LOW transition of the input current pulse to the 1.3V level on the HIGH to LOW transition of the output voltage pulse. 4. When the peaking capacitor is omitted, propagation delay times may increase by 100ns. 5. tr – Rise time is measured from the 10% to the 90% levels on the LOW to HIGH transition of the output pulse. 6. tf – Fall time is measured from the 90% to the 10% levels on the HIGH to LOW transition of the output pulse. 7. CMH – The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the high state (i.e., VOUT > 2.0V). 8. CML – The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the low state (i.e., VOUT < 0.8V). 9. Device considered a two-terminal device: Pins 1, 2, 3 and 4 shorted together, and Pins 5, 6, 7 and 8 shorted together. 10. Duration of output short circuit time should not exceed 10ms. ©2004 Fairchild Semiconductor Corporation FOD2200 Rev. 1.0.4 www.fairchildsemi.com 5 FOD2200 — Low Input Current Logic Gate Optocouplers Electrical Characteristics (Continued) FOD2200 — Low Input Current Logic Gate Optocouplers Test Circuits PULSE GEN. t r = t f = 5 ns f = 100 kHz 10 % DUTY CYCLE VO = 5 V IF INPUT MONITORING NODE R1 VCC OUTPUT VO MONITORING NODE FOD2200 1 VCC 8 2 7 3 6 5V 619 Ω D1 D2 C2 = 15 pF GND 5 4 C1 = 120 pF D3 5 kΩ D4 THE PROBE AND JIG CAPACITANCES ARE INCLUDED IN C 1 AND C2. 2.15 kΩ 1.10 kΩ 681 Ω RI 5 mA IF (ON) 1.6 mA 3 mA ALL DIODES ARE 1N916 OR 1N3064. IF (ON) 50 % IF (ON) 0 mA INPUT IF t PLH t PHL VOH 1.3 V VOL OUTPUT VO Fig. 1. Test Circuit and Waveforms for tPLH, tPHL, tr and tf PULSE GENERATOR ZO = 50 Ω t r = t f = 5 ns CL = 15 pF INCLUDING PROBE AND JIG CAPACITANCES . +5 V VCC VO FOD2200 1 VCC 8 2 7 3 6 4 GND 5 S1 D1 IF 619 Ω D2 CL 5 kΩ INPUT VC MONITORING NODE D3 D4 S2 D1-4 ARE 1N916 OR 1N3064. INPUT VE t PZL OUTPUT S1 CLOSED VO S2 OPEN t PZH OUTPUT VO S1 OPEN S2 CLOSED t PLZ 1.3 V 3.0 V 1.3 V 0V S1 AND S2 CLOSED 0.5 V 0.5 V 1.3 V 0V t PHZ VOL VOH ≈1.5 V S1 AND S2 CLOSED Fig. 2. Test Circuit and Waveforms for tPHZ, tPZH, tPLZ, and tPZL ©2004 Fairchild Semiconductor Corporation FOD2200 Rev. 1.0.4 www.fairchildsemi.com 6 VCC FOD2200 A 1 VCC 8 B 2 7 3 6 RIN VFF 4 GND OUTPUT VO MONITORING NODE 0.1 µF BYPASS 5 VCM PULSE GENERATOR + – 50 V VCM 0V SWITCH AT A: I F = 1.6mA VOH VO (MIN.)* SWITCH AT B: I F = 0mA VO (MAX.)* OUTPUT VO VOL * SEE NOTE 6. Fig. 3. Test Circuit and Typical Waveforms for Common Mode Transient Immunity VCC1 (+5V) VCC1 (+5V) 120pF FOD2200 1.1 kΩ DATA INPUT 1 VCC 8 2 7 3 TTL OR LSTTL TOTEM POLE OUTPUT GATE 6 GND 4 5 FOD2200 1.1 kΩ DATA OUTPUT UP TO 16 LSTTL LOADS OR 4 TTL LOADS DATA INPUT 2 DATA INPUT TTL OR LSTTL 1 VCC 8 2 7 D1 3 4 7 DATA INPUT 6 GND CMOS DATA OUTPUT 6 GND 4 5 RL 1.1kΩ 2.37kΩ 3.83kΩ 5.11kΩ 2 120pF (OPTIONAL*) 1.1 kΩ FOD2200 1.1kΩ 2 RL Figure 5. LSTTL to CMOS Interface Circuit VCC (+5 V) VCC1 (+5 V) VCC 8 VCC2 5V 10V 15V 20V 1 Figure 4. Recommended LSTTL to LSTTL Circuit 1 3 TTL OR LSTTL TOTEM POLE OUTPUT GATE 1 VCC2 (4.5V TO 20V) 120pF (OPTIONAL*) VCC2 (+5V) 5 OPEN COLLECTOR GATE 4.7k Ω FOD2200 1 VCC 8 2 7 3 TTL OR LSTTL 4 6 GND 5 D1 (1N4150) REQUIRED FOR ACTIVE PULL-UP DRIVER. Figure 7. Series LED Drive with Open Collector Gate (4.7kΩ Resistor Shunts IOH from the LED) Figure 6. Recommended LED Drive Circuit *The 120pF capacitor may be omitted in applications where 500ns propagation delay is sufficient. ©2004 Fairchild Semiconductor Corporation FOD2200 Rev. 1.0.4 www.fairchildsemi.com 7 FOD2200 — Low Input Current Logic Gate Optocouplers Test Circuits (Continued) Figure 8. Input Forward Current vs Forward Voltage Figure 9. Output Voltage vs. Input Forward Current 5 IF – FORWARD CURRENT (mA) 100 VCC = 4.5V TA = 25°C 4 VO – Output Voltage (V) 10 TA = 85°C TA = 70°C 1 TA = -40°C TA = 25°C TA = 0°C 0.1 0.01 3 IO = -2.6mA 2 IF(OFF) IF(ON) 1 IO = 6.4mA 0 0.001 0.9 1.0 1.1 1.2 1.3 1.4 1.5 V F – FORWARD VOLTAGE (V) 1.6 0.0 1.7 1.0 0.8 IF(OFF) 0.4 0.2 0.0 -40 VOH – LOGIC HIGH OUTPUT VOLTAGE (V) VOL – LOGIC LOW OUTPUT VOLTAGE (V) VCC = 5V, 20V -20 0 20 40 60 TA – Ambient Temperature (°C) 80 12 8 4 0 8 12 16 VCC – SUPPLY VOLTAGE (V) 0.5 0.4 0.3 0.2 0.1 0.0 20 tf, tr – RISE, FALL TIME (µs) tP – PROPAGATION DELAY (µs) tPHL, IF = 3mA 140 tPHL, IF = 1.6mA tPLH, IF = 1.6mA–5mA 100 VCC = 4.5V IF = 5 mA -1 -2 VO = 2.7V -3 -4 VO = 2.4V -5 -6 -7 -40 -20 0 20 40 60 80 TA – AMBIENT TEMPERATURE (°C) 100 Figure 15. Rise, Fall Time vs Ambient Temperature tPHL, IF = 5mA 180 100 200 VCC = 5V C1 (120pF) Peaking Capacitor Is Used. See Figure 1. 220 0 20 40 60 80 TA – AMBIENT TEMPERATURE (°C) 0 Figure 14. Propagation Delay vs Ambient Temperature 260 -20 Figure 13. Logic High Output Current vs. Ambient Temperature IO = -2.6 mA TA = 25°C IF ≥ IF (ON) 4 0.6 -40 Figure 12. Logic High Output Voltage vs. Supply Voltage 0 VCC = 4.5V IF = 0 mA IO = 6.4 mA 0.7 100 20 16 1.2 0.8 IOH – LOGIC HIGH OUTPUT CURRENT (mA) INPUT CURRENT THRESHOLD (mA) 1.2 IF(ON) 0.4 0.6 0.8 1.0 IF – INPUT FORWARD CURRENT (mA) Figure 11. Logic Low Output Voltage vs. Ambient Temperature Figure 10. Input Threshold Current vs. Ambient Temperature 0.6 0.2 60 VCC = 5V IF = 1.6mA 160 120 tr 80 40 tf 0 -40 -20 0 20 40 60 80 TA – AMBIENT TEMPERATURE (°C) ©2004 Fairchild Semiconductor Corporation FOD2200 Rev. 1.0.4 -40 100 -20 0 20 40 60 80 TA – AMBIENT TEMPERATURE (°C) 100 www.fairchildsemi.com 8 FOD2200 — Low Input Current Logic Gate Optocouplers Typical Performance Curves Through Hole 0.4" Lead Spacing (Option T) PIN 1 ID. 4 3 2 PIN 1 ID. 1 4 3 2 1 0.270 (6.86) 0.250 (6.35) 5 6 7 0.270 (6.86) 0.250 (6.35) 8 5 0.070 (1.78) 0.045 (1.14) 0.154 (3.90) 0.120 (3.05) 0.022 (0.56) 0.016 (0.41) 7 8 0.390 (9.91) 0.370 (9.40) 0.020 (0.51) MIN 0.200 (5.08) MAX 6 0.156 (3.94) 0.144 (3.68) SEATING PLANE SEATING PLANE 0.390 (9.91) 0.370 (9.40) 0.156 (3.94) 0.070 (1.78) 0.144 (3.68) 0.045 (1.14) 0.020 (0.51) MIN 0.200 (5.08) MAX 15° MAX 0.016 (0.40) 0.008 (0.20) 0.154 (3.90) 0.120 (3.05) 0.300 (7.62) TYP 0.100 (2.54) TYP 0.022 (0.56) 0.016 (0.41) 0.016 (0.40) 0.008 (0.20) 0.100 (2.54) TYP 0.031 (0.78) Surface Mount – 0.3" Lead Spacing (Option S) 0° to 15° 0.400 (10.16) TYP 8-Pin Surface Mount DIP – Land Pattern (Option S) 0.390 (9.91) 0.370 (9.40) 4 3 2 0.070 (1.78) PIN 1 ID. 1 0.060 (1.52) 0.270 (6.86) 0.250 (6.35) 5 6 7 0.100 (2.54) 8 0.295 (7.49) 0.156 (3.94) 0.144 (3.68) 0.070 (1.78) 0.045 (1.14) 0.020 (0.51) MIN 0.200 (5.08) MAX 0.022 (0.56) 0.016 (0.41) 0.100 (2.54) TYP 0.415 (10.54) 0.300 (7.62) TYP 0.030 (0.76) 0.016 (0.40) 0.008 (0.20) 0.015 (0.40) MIN Both Sides 0.315 (8.00) MIN 0.405 (10.30) MAX. Note: All dimensions are in inches (millimeters) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2004 Fairchild Semiconductor Corporation FOD2200 Rev. 1.0.4 www.fairchildsemi.com 9 FOD2200 — Low Input Current Logic Gate Optocouplers Package Dimensions Surface Mount – 0.4" Lead Spacing (Option TS) 8-Pin Surface Mount DIP – Land Pattern (Option TS) 0.390 (9.91) 0.370 (9.40) 4 3 2 1 0.070 (1.78) PIN 1 ID. 0.060 (1.52) 0.270 (6.86) 0.250 (6.35) 5 6 7 0.100 (2.54) 8 0.392 (9.96) 0.156 (3.94) 0.144 (3.68) 0.020 (0.51) MIN 0.200 (5.08) MAX 0.511 (13.0) 0.300 (7.62) TYP 0.070 (1.78) 0.045 (1.14) 0.031 (0.775) 0.022 (0.56) 0.016 (0.41) 0.100 (2.54) TYP 0.030 (0.76) 0.016 (0.40) 0.008 (0.20) 0.015 (0.40) MIN Both Sides 0.400 (10.16) 0.497 (12.6) MAX. Note: All dimensions are in inches (millimeters) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2004 Fairchild Semiconductor Corporation FOD2200 Rev. 1.0.4 www.fairchildsemi.com 10 FOD2200 — Low Input Current Logic Gate Optocouplers Package Dimensions (Continued) Part Number Package Packing Method FOD2200 DIP 8-Pin Tube (50 units per tube) FOD2200S SMT 8-Pin (Lead Bend) Tube (50 units per tube) FOD2200SD SMT 8-Pin (Lead Bend) Tape and Reel (1,000 units per reel) FOD2200V DIP 8-Pin, IEC60747-5-2 option Tube (50 units per tube) FOD2200SV SMT 8-Pin (Lead Bend), IEC60747-5-2 option Tube (50 units per tube) FOD2200SDV SMT 8-Pin (Lead Bend), IEC60747-5-2 option Tape and Reel (1,000 units per reel) FOD2200TV DIP 8-Pin, 0.4” Lead Spacing, IEC60747-5-2 option Tube (50 units per tube) FOD2200TSV SMT 8-Pin, 0.4” Lead Spacing, IEC60747-5-2 option Tube (50 units per tube) FOD2200TSR2V SMT 8-Pin, 0.4” Lead Spacing, IEC60747-5-2 option Tape and Reel (700 units per reel) Marking Information 1 2200 V XX YY B 3 2 6 5 4 Definitions 1 Fairchild logo 2 Device number 3 IEC60747-5-2 Option (only appears on component ordered with this option) (Pending approval) 4 Two digit year code, e.g., ‘08’ 5 Two digit work week ranging from ‘01’ to ‘53’ 6 Assembly package code ©2004 Fairchild Semiconductor Corporation FOD2200 Rev. 1.0.4 www.fairchildsemi.com 11 FOD2200 — Low Input Current Logic Gate Optocouplers Ordering Information D0 P0 t K0 P2 E F A0 W1 d t P User Direction of Feed Symbol W W B0 Description D1 Dimension in mm Tape Width 16.0 ± 0.3 Tape Thickness 0.30 ± 0.05 P0 Sprocket Hole Pitch 4.0 ± 0.1 D0 Sprocket Hole Diameter 1.55 ± 0.05 E Sprocket Hole Location 1.75 ± 0.10 F Pocket Location 7.5 ± 0.1 2.0 ± 0.1 P2 P Pocket Pitch A0 Pocket Dimensions 12.0 ± 0.1 10.30 ±0.20 B0 10.30 ±0.20 K0 4.90 ±0.20 W1 d R ©2004 Fairchild Semiconductor Corporation FOD2200 Rev. 1.0.4 Cover Tape Width 13.2 ± 0.2 Cover Tape Thickness 0.1 max Max. Component Rotation or Tilt 10° Min. Bending Radius 30 www.fairchildsemi.com 12 FOD2200 — Low Input Current Logic Gate Optocouplers Carrier Tape Specifications (Option SD) D0 P0 t K0 P2 E F A0 W1 d P User Direction of Feed Symbol W W B0 Description D1 Dimension in mm Tape Width 24.0 ± 0.3 Tape Thickness 0.40 ± 0.1 P0 Sprocket Hole Pitch 4.0 ± 0.1 D0 Sprocket Hole Diameter 1.55 ± 0.05 E Sprocket Hole Location 1.75 ± 0.10 F Pocket Location 11.5 ± 0.1 t 2.0 ± 0.1 P2 P Pocket Pitch A0 Pocket Dimensions 16.0 ± 0.1 12.80 ± 0.1 B0 10.35 ± 0.1 K0 5.7 ±0.1 W1 d R ©2004 Fairchild Semiconductor Corporation FOD2200 Rev. 1.0.4 Cover Tape Width 21.0 ± 0.1 Cover Tape Thickness 0.1 max Max. Component Rotation or Tilt 10° Min. Bending Radius 30 www.fairchildsemi.com 13 FOD2200 — Low Input Current Logic Gate Optocouplers Carrier Tape Specifications (Option TSR2V) FOD2200 — Low Input Current Logic Gate Optocouplers Reflow Profile Temperature (°C) TP 260 240 TL 220 200 180 160 140 120 100 80 60 40 20 0 Max. Ramp-up Rate = 3°C/S Max. Ramp-down Rate = 6°C/S tP Tsmax tL Preheat Area Tsmin ts 120 240 360 Time 25°C to Peak Time (seconds) Profile Freature Pb-Free Assembly Profile Temperature Min. (Tsmin) 150°C Temperature Max. (Tsmax) 200°C Time (tS) from (Tsmin to Tsmax) 60–120 seconds Ramp-up Rate (tL to tP) 3°C/second max. Liquidous Temperature (TL) 217°C Time (tL) Maintained Above (TL) 60–150 seconds Peak Body Package Temperature 260°C +0°C / –5°C Time (tP) within 5°C of 260°C 30 seconds Ramp-down Rate (TP to TL) 6°C/second max. Time 25°C to Peak Temperature ©2004 Fairchild Semiconductor Corporation FOD2200 Rev. 1.0.4 8 minutes max. www.fairchildsemi.com 14 AccuPower™ Auto-SPM™ Build it Now™ CorePLUS™ CorePOWER™ CROSSVOLT™ CTL™ Current Transfer Logic™ DEUXPEED® Dual Cool™ EcoSPARK® n EfficientMax™ ESBC™ ® Fairchild® Fairchild Semiconductor® FACT Quiet Series™ FACT® FAST® FastvCore™ FETBench™ FlashWriter®* FPS™ F-PFS™ FRFET® SM Global Power Resource Green FPS™ Green FPS™ e-Series™ Gmax™ GTO™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MicroPak2™ MillerDrive™ MotionMax™ Motion-SPM™ OptoHiT™ OPTOLOGIC® OPTOPLANAR® ® PDP SPM™ Power-SPM™ PowerTrench® PowerXS™ Programmable Active Droop™ QFET® QS™ Quiet Series™ RapidConfigure™ ™ Saving our world, 1mW/W/kW at a time™ SignalWise™ SmartMax™ SMART START™ SPM® STEALTH™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SupreMOS® SyncFET™ Sync-Lock™ ® * The Power Franchise® TinyBoost™ TinyBuck™ TinyCalc™ TinyLogic® TINYOPTO™ TinyPower™ TinyPWM™ TinyWire™ TriFault Detect™ TRUECURRENT™* " SerDes™ UHC® Ultra FRFET™ UniFET™ VCX™ VisualMax™ XS™ * Trademarks of System General Corporation, used under license by Fairchild Semiconductor. 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Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Advance Information Formative / In Design Preliminary First Production No Identification Needed Full Production Obsolete Not In Production Definition Datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I49 ©2004 Fairchild Semiconductor Corporation FOD2200 Rev. 1.0.4 www.fairchildsemi.com 15 FOD2200 — Low Input Current Logic Gate Optocouplers TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.