FOD8001

High Noise Immunity, 3.3 V / 5 V Logic Gate Optocoupler FOD8001 Description www.onsemi.com The FOD8001 is a 3.3 V / 5 V high−speed logic gate optocoupler, which supports isolated communications allowing digital signals to communicate between systems without conducting ground loops or hazardous voltages. It utilizes ON Semiconductor patented coplanar packaging technology, Optoplanar®, and optimized IC design to achieve high noise immunity, characterized by high common mode rejection and power supply rejection specifications. This high−speed logic gate optocoupler, packaged in a compact 8−pin small outline package, consists of a high−speed AlGaAs LED driven by a CMOS buffer IC coupled to a CMOS detector IC. The detector IC comprises an integrated photodiode, a high−speed transimpedance amplifier and a voltage comparator with an output driver. The CMOS technology coupled to the high efficiency of the LED achieves low power consumption as well as very high speed (40ns propagation delay, 6ns pulse width distortion). SOIC8 CASE 751DZ MARKING DIAGRAM 1 Features • High Noise Immunity characterized by Common Mode Rejection • • • • (CMR) and Power Supply Rejection (PSR) Specifications ♦ 20 kV/ms Minimum Static CMR @ Vcm = 1000 V ♦ 25 kV/ms Typical Dynamic CMR @ Vcm = 1500 V, 20 MBaud Rate ♦ PSR in Excess of 10% of the Supply Voltages across Full Operating Bandwidth High Speed: ♦ 25 Mbit/s Date Rate (NRZ) ♦ 40 ns max. Propagation Delay ♦ 6 ns max. Pulse Width Distortion ♦ 20 ns max. Propagation Delay Skew 3.3 V and 5 V CMOS Compatibility Extended Industrial Temperate Range, −40°C to 105°C Temperature Range Safety and Regulatory Pending Approvals: ♦ UL1577, 3750 VACRMS for 1 min. ♦ IEC60747−5−2 (pending) 1. 2. 3. 4. ON 8001 X YY 5. S1 ON 8001 2 X YY S1 5 3 4 = ON Semiconductor Logo = Device Number = One−Digit Year Code, e.g. ‘8’ = Two Digit Work Week Ranging from ‘01’ to ‘53’ = Assembly Package Code ORDERING INFORMATION See detailed ordering and shipping information on page 8 of this data sheet. Applications • Industrial Fieldbus Communications ♦ Profibus, DeviceNet, CAN, RS485 • Programmable Logic Control • Isolated Data Acquisition System TRUTH TABLE VI LED VO HIGH OFF HIGH LOW ON LOW © Semiconductor Components Industries, LLC, 2020 August, 2020 − Rev. 1 1 Publication Order Number: FOD8001/D FOD8001 Functional Schematic PIN DEFINITIONS Pin Name 1 VDD1 2 VI 8 VDD2 VDD1 1 VI 2 7 NC 3 6 VO * Pin Number GND1 4 Pin Function Description Input Supply Voltage Input Data 3 5 GND2 LED Anode – Must be left unconnected 4 GND1 Input Ground 5 GND2 Output Ground 6 VO Output Data 7 NC Not Connected 8 VDD2 Output Supply Voltage *: Pin 3 must be left unconnected Figure 1. Functional Schematic ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise specified) Symbol Parameter Value Units TSTG Storage Temperature −40 to +125 °C TOPR Operating Temperature −40 to +105 °C TSOL Lead Solder Temperature (Refer to Reflow Temperature Profile) 260 for 10 s °C VDD1, VDD2 Supply Voltage VI Input Voltage II Input DC Current 0 to 6.0 V −0.5 to VDD1 + 0.5 V −10 to +10 mA −0.5 to VDD2 + 0.5 V Average Output Current 10 mA PDI Input Power Dissipation (Note 1) 90 mW PDO Total Power Dissipation (Note 2) 70 mW VO Output Voltage IO Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Derate linearly from 25°C at a rate of tbd W/°C 2. Derate linearly from 25°C at a rate of tbd mW/°C RECOMMENDED OPERATING CONDITIONS Symbol Min. Max. Unit Ambient Operating Temperature −40 +105 °C Supply Voltages (3.3 V Operation) (Note 3) 3.0 3.6 V Supply Voltages (5.0 V Operation) (Note 3) 4.5 5.5 VIH Logic High Input Voltage 2.0 VDD V VIL Logic Low Input Voltage 0 0.8 V tr, tf Input Signal Rise and Fall Time 1.0 ms TA VDD1, VDD2 Parameter Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 3. 0.1 mF bypass capacitor must be connected between Pin 1 and 4, and 5 and 8. ISOLATION CHARACTERISTICS (Apply over all recommended conditions, typical value is measured at TA = 25°C) Symbol Characteristics Test Conditions Min. Typ. Max. Unit VISO Input−Output Isolation Voltage f = 60 Hz, t = 1.0 min., II−O ≤ 10 mA (Notes 4, 5) 3750 VacRMS RISO Isolation Resistance VI−O = 500V (Note 4) 1011 W CISO Isolation Capacitance VI−O = 0 V, f = 1.0MHz (Note 4) 0.2 4. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted together. 5. 3,750 VACRMS for 1 minute duration is equivalent to 4,500 VACRMS for 1 second duration. www.onsemi.com 2 pF FOD8001 ELECTRICAL CHARACTERISTICS (Apply over all recommended conditions, typical value is measured at VDD1 = VDD2 = +3.3 V, VDD1 = +3.3 V and VDD2 = +5.0 V, VDD1 = +5.0 V and VDD2 = +3.3 V, VDD1 = VDD2 = +5.0 V, TA = 25°C) Symbol Parameter Conditions Min. Typ. Max. Units 6.2 10.0 mA INPUT CHARACTERISTICS IDD1L Logic Low Input Supply Current VI = 0 V IDD1H Logic High Input Supply Current VI = VDD1 IIA, IIB Input Current 0.8 −10 3.0 mA +10 mA OUTPUT CHARACTERISTICS IDD2L Logic Low Output Supply Current VI = 0 V 4.5 9.0 mA IDD2H Logic High Output Supply Current VI = VDD1 4.5 9.0 mA Logic High Output Voltage IO = −20 mA, VI = VIH, VDD2 = +3.3 V 2.9 3.3 IO = −4 mA, VI = VIH, VDD2 = +3.3 V 1.9 2.9 IO = −20 mA, VI = VIH, VDD2 = +5.0 V 4.4 5.0 IO = −4 mA, VI = VIH, VDD2 = +5.0 V 4.0 4.8 VOH VOL Logic Low Output Voltage V IO = 20 mA, VI = VIL 0 0.1 IO = 4 mA, VI = VIL 0.3 1.0 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. SWITCHING CHARACTERISTICS (Apply over all recommended conditions, typical value is measured at VDD1 = VDD2 = +3.3 V, VDD1 = +3.3 V and VDD2 = +5.0 V, VDD1 = +5.0 V and VDD2 = +3.3 V, VDD1 = VDD2 = +5.0 V, TA = 25°C) Symbol Parameter Typ. Max. Unit tPHL Propagation Delay Time to Logic Low Output CL = 15 pF Test Conditions Min. 25 40 ns tPLH Propagation Delay Time to Logic High Output CL = 15 pF 25 40 ns PWD Pulse Width Distortion, | tPHL – tPLH | PWD = 40 ns, CL = 15 pF 2 6 ns 25 Mb/s 20 ns Data Rate tPSK Propagation Delay Skew tR Output Rise Time (10%–90%) tF Output Fall Time (90%–10%) CL = 15 pF (6) 6.5 ns 6.5 ns |CMH| Common Mode Transient Immunity at Output High VI = VDD1, VO > 0.8 VDD1, VCM = 1000 V (Note 7) 20 40 kV/ms |CML| Common Mode Transient Immunity at Output Low VI = 0 V, VO < 0.8 V, VCM = 1000 V (Note 7) 20 40 kV/ms CPDI Input Dynamic Power Dissipation Capacitance (Note 8) 30 pF CPDO Output Dynamic Power Dissipation Capacitance (Note 8) 3 pF 6. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the recommended operating conditions. 7. Common mode transient immunity at output high is the maximum tolerable positive dVcm/dt on the leading edge of the common mode impulse signal, Vcm, to assure that the output will remain high. Common mode transient immunity at output low is the maximum tolerable negative dVcm/dt on the trailing edge of the common pulse signal, Vcm, to assure that the output will remain low. 8. Unloaded dynamic power dissipation is calculated as follows: CPD x VDD x f + IDD + VPD where f is switched time in MHz. www.onsemi.com 3 FOD8001 4.0 VITH − Typical Input Voltage Switching Threshold (V) TYPICAL PERFORMANCE CURVES VDD1 = VDD2 = 3.3 V VO − Output Voltage (V) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 1 2 3 4 5 2.0 VDD2 = 3.3 V 1.8 1.6 1.4 1.2 1.0 3.0 3.5 VI − Input Voltage (V) Figure 2. Typical Output Voltage vs. Input Voltage tP − Propagation Delay (ns) 30 5.5 Frequency = 12.5 MHz Duty Cycle = 50% 3.5 VDD1 = VDD2 = 3.3 V 26 tPHL 24 tPLH 22 3.0 2.5 2.0 1.5 1.0 0.5 20 −40 −20 0 20 40 60 80 0.0 −40 100 −20 0 20 40 60 80 100 TA − Ambient Temperature (°C) TA − Ambient Temperature (°C) Figure 4. Propagation Delay vs. Ambient Temperature Figure 5. Pulse Width Distortion vs. Ambient Temperature 7.5 Frequency = 12.5 MHz Duty Cycle = 50% VDD1 = VDD2 = 3.3 V Frequency = 12.5 MHz Duty Cycle = 50% 7.0 VDD1 = VDD2 = 3.3 V 7.0 6.5 tf − Fall Time (ns) tr − Rise Time (ns) 5.0 4.0 Frequency = 12.5 MHz Duty Cycle = 50% VDD1 = VDD2 = 3.3 V 28 7.5 4.5 Figure 3. Input Voltage Switching Threshold vs. Input Supply Voltage PWD − Pulse Width Distortion (ns) 32 4.0 VDD1 − Input Supply Voltage (V) 6.5 6.0 5.5 5.0 6.0 4.5 5.5 −40 −20 0 20 40 60 80 4.0 −40 100 −20 0 20 40 60 80 TA − Ambient Temperature (°C) TA − Ambient Temperature (°C) Figure 6. Typical Rise Time vs. Ambient Temperature Figure 7. Typical Fall Time vs. Ambient Temperature www.onsemi.com 4 100 FOD8001 TYPICAL PERFORMANCE CURVES (Continued) 34 Frequency = 12.5 MHz Duty Cycle = 50% 2.4 VDD1 = VDD2 = 3.3 V PWD − Pulse Width Distortion (ns) 32 tP − Propagation Delay (ns) 2.6 Frequency = 12.5 MHz Duty Cycle = 50% VDD1 = VDD2 = 3.3 V 30 tPHL 28 tPLH 26 24 2.2 2.0 1.8 1.6 1.4 1.2 22 15 20 25 30 35 40 45 50 1.0 15 55 20 Figure 8. Typical Propagation Delay vs. Output Load Capacitance 12 40 45 50 55 Frequency = 12.5 MHz Duty Cycle = 50% 14 VDD1 = VDD2 = 3.3 V 12 tf − Fall Time (ns) tr − Rise Time (ns) 35 16 10 9 8 7 10 8 6 6 4 5 4 2 15 20 25 30 35 40 45 50 55 15 Figure 10. Typical Rise Time vs. Output Load Capacitance 6.5 6.0 5.0 TA =25_C 4.5 IDD2 − Output Supply Current (mA) 6.0 5.5 25 30 35 40 45 50 55 Figure 11. Typical Fall Time vs. Output Load Capacitance VDD1 = 5.5 V TA =105_C 20 CL − Output Load Capacitance (pF) CL − Output Load Capacitance (pF) IDD1 − Input Supply Current (mA) 30 Figure 9. Typical Width Distortion vs. Output Load Capacitance Frequency = 12.5 MHz Duty Cycle = 50% VDD1 = VDD2 = 3.3 V 11 25 CL − Output Load Capacitance (pF) CL − Output Load Capacitance (pF) TA =−40_C 4.0 VDD1 =V DD2 *Pin 6 Floating 5.8 TA =25_C 5.6 TA =−40_C 5.4 TA =105_C 5.2 3.5 3.0 5.0 0 2000 4000 6000 8000 10000 0 12000 2000 4000 6000 8000 10000 12000 f − Frequency (kHz) f − Frequency (kHz) Figure 12. Input Supply Current vs. Frequency Figure 13. Output Supply Current vs. Frequency www.onsemi.com 5 FOD8001 TEST CIRCUITS 1 8 2 7 3 6 0.1 mF VDD1 = 3.3V 0.1 mF VDD2 0V–3.3V O Pulse width = 40ns Duty Cycle = 50% CL 4 5 tPLH tPHL 3.3V Input 50% VIN VOH 90% Output 50% VOUT 10% VOL tR tF Figure 14. Test Circuit for Propagation Delay and Rise Time, Fall Time 1 8 2 7 3 6 0.1 mF SW 0.1 mF VDD2 B A VDD1 = 3.3V O CL 4 5 +– VCM 1kV VCM GND VOH Switching Pos. (A) V IN = 3.3V CMH 0.8 x VDD 0.8V VOL Switching Pos. (B) V IN = 0V CML Figure 15. Test Circuit for Instantaneous Common Mode Rejection Voltage www.onsemi.com 6 FOD8001 APPLICATION INFORMATION Test circuit functions were built to interface a commercial pseudo−random bit sequence (PRBS) generator and error detector with a pair of high speed optocouplers, FOD8001, connected in a loop−back configuration. With a 10 MBaud PRBS serial data stream, no error was detected until the common mode voltage rose above 2.5 kV with a dv/dt of 45 kV/ms. And increasing the data rate beyond 10 Mbaud, the test was conducted at 20 MBaud, and no error was detected at dv/dt of 25 kV/ms at common mode voltage of 1.5 kV. The test data for the dynamic CMR is comparable or better than the static CMR specifications found in the datasheet. These excellent noise rejection performances are results of the innovative circuit design and the patented coplanar assembly process. Noise is defined as any unwanted signal that degrades or interferes with the operation of a system or circuit. Input−output noise rejection is a key characteristic of an optocoupler, and the performance specification for this noise rejection is called, “Common Mode Transient Immunity or Common Mode Rejection, CMR”. The CMR test configuration is presented in high speed optocoupler datasheets, which tests the optocoupler to a specified rate of interfering signal (dv/dt), at a specified peak voltage (Vcm). This defined noise signal is applied to the test device while the coupler is a stable logic high or logic low state. This test procedure evaluates the interface device in a constant or static logic state. This type of CMR can be referred to as “Static CMR”. ON Semiconductor high speed optocouplers, which use an optically transparent, electrically conductive shield, and offer active totem pole logic output have static CMR in excess of 50 kV/ms at peak amplitudes of 1.5 kV to 2.0 kV. Power Supply Noise Rejection High levels of electrical noise can cause the optocoupler to register the incorrect logic state. The most commonly discussed noise signal is the common mode noise found between the input and output of the optocoupler. However, common mode noise is not the only path of noise into the input or output of the optocoupler. Due to the high gain and wide bandwidth of the transimpedance amplifier used for the photo detector circuits, power supply noise can cause the optocoupler to change state independent of the LED operation. Power supply noise is typically characterized as either random or periodic pulses with varying amplitudes and rates of rise and fall. The necessary tests have been conducted to understand the influence of the power supply noise and its effect of the proper operation of the FOD8001. The optocoupler under test offered power supply noise rejection in excess of 10% of the supply voltage for a frequency ranging from 100 kHz to 35 MHz, for logic high and logic low states. Dynamic Common Mode Rejection The noise susceptibility of an interface while it is actively transferring data is a common requirement in serial data communication. However, the static CMR specification is not adequate in quantifying the electrical noise susceptibility for optocouplers used in isolating high speed data transfer. A serial data communication network’s noise performance is usually quantified as the number of bit errors per second or as a ratio of the number of bits transmitted in a specified time frame. This describes Bit Error Rate, BER. Test equipment that evaluates BER is called a Bit Error Rate Tester, BERT. When a BERT system is combined with a CMR tester, the active or dynamic noise rejection of an isolated interface can then be quantified. This type of CMR is thus defined as “Dynamic CMR”. Therefore, evaluating the common mode rejection while the optocoupler is switching at high speed represents a realistic approach to understand noise interference. www.onsemi.com 7 FOD8001 ORDERING INFORMATION Packing Method† Option Order Entry Identifier Package No Suffix FOD8001 SOIC8 (Pb−Free)* Tube (50 Units per Tube) R2 FOD8001R2 SOIC8 (Pb−Free)* Tape and Reel (2,500 Units per Reel) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *All packages are lead free per JEDEC: J−STD−020B standard. REFLOW PROFILE 300 260_C 280 260 >245_C = 42 Sec Temperature (5C) 240 220 200 180 160 Time above 140 183_C = 90 Sec 120 1.822_C/Sec Ramp up rate 100 80 60 40 33 Sec 20 0 0 60 120 180 270 360 Time (s) OPTOPLANAR is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 8 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC8 CASE 751DZ ISSUE O DOCUMENT NUMBER: DESCRIPTION: 98AON13733G SOIC8 DATE 30 SEP 2016 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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