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FOD8316
2.5 A Output Current, IGBT Drive Optocoupler with
Desaturation Detection and Isolated Fault Sensing
Features
Description
■ High Noise Immunity Characterized by
The FOD8316 is an advanced 2.5 A output current
IGBT drive optocoupler capable of driving most 1200 V /
150 A IGBTs. It is ideally suited for fast-switching driving
of power IGBTs and MOSFETs used in motor-control
inverter applications and high-performance power
systems. The FOD8316 offers critical protection features
necessary for preventing fault conditions that lead to
destructive thermal runaway of IGBTs.
■
■
■
■
■
■
■
■
■
■
■
■
Common Mode Rejection – 35 kV/µs Minimum,
VCM = 1500 VPEAK
2.5 A Peak Output Current Driving Capability for Most
1200 V / 150 A IGBTs
Optically Isolated Fault Sensing Feedback
“Soft” IGBT Turn-off
Built-in IGBT Protection
– Desaturation Detection
– Under-Voltage Lockout (UVLO) Protection
Wide Supply Voltage Range: 15 V to 30 V
– P-Channel MOSFETs at Output Stage Enables
Output Voltage Swing Close to the Supply Rail
(Rail-to-Rail Output)
3.3 V / 5 V, CMOS/TTL Compatible Inputs
High Speed
– 500 ns Maximum Propagation Delay Over Full
Operating Temperature Range
Extended Industrial Temperate Range:
–40°C to 100°C
Safety and Regulatory Approvals
– UL1577, 4,243 VRMS for 1 Minute
– DIN EN/IEC 60747-5-5:
1,414 VPEAK Working Insulation Voltage Rating
8,000 VPEAK Transient Isolation Voltage Rating
RDS(ON) of 1 Ω (Typical) Offers Lower Power
Dissipation
User-Configurable: Inverting, Non-inverting,
Auto-reset, Auto-shutdown
8 mm Creepage and Clearance Distances
The device utilizes Fairchild’s proprietary Optoplanar®
coplanar packaging technology, and optimized IC design
to achieve high noise immunity, characterized by high
common-mode rejection and power supply rejection
specifications.
The FOD8316 consists of an integrated gate drive optocoupler featuring low RDS(ON) CMOS transistors to drive
the IGBT from rail-to-rail and an integrated high-speed
isolated feedback for fault sensing. The device is housed
in a compact 16-pin small-outline plastic package which
meets the 8 mm creepage and clearance requirements.
Applications
■ Industrial Inverter
■ Induction Heating
■ Isolated IGBT Drive
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.1
www.fairchildsemi.com
FOD8316 — 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
July 2014
VIN–
UVLO
(VDD2 – VE)
X
X
Active
X
X
X
LOW
X
X
X
HIGH
X
HIGH
LOW
Not Active
VIN+
DESAT
Detected?
FAULT
VO
X
X
LOW
Yes
LOW
LOW
X
X
LOW
X
X
LOW
No
HIGH
HIGH
Pin Configuration
VIN+
1
16 VE
VIN–
2
15 VLED2+
VDD1
3
14 DESAT
GND1
4
13 VDD2
RESET
5
12 VS
FAULT
6
11 VO
VLED1+
7
10 VSS
VLED1-*
8
9
VSS
*Pin 8 (VLED1-) is internally connected to Pin 4 (GND1).
Figure 1. Pin Configuration
Pin Definitions
Pin #
Name
Description
1
VIN+
Non-inverting Gate Drive Control Input
2
VIN–
Inverting Gate-Drive Control Input
3
VDD1
Positive Input Supply Voltage (3 V to 5.5 V)
4
GND1
Input Ground
5
RESET
FAULT Reset Input
6
FAULT
Fault Output (Open Drain)
7
VLED1+
LED 1 Anode (Do not connect. Leave floating.)
8
VLED1-
LED 1 Cathode (Must be connected to ground.)
9
VSS
Output Supply Voltage (Negative)
10
VSS
Output Supply Voltage (Negative)
11
VO
Gate-Drive Output Voltage
12
VS
Pull-up PMOS Transistor Source
13
VDD2
14
DESAT
15
VLED2+
16
VE
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.1
Positive Output Supply Voltage
Desaturation Voltage Input
LED 2 Anode (Do not connect. Leave floating.)
Output Supply Voltage / IGBT Emitter
www.fairchildsemi.com
2
FOD8316 — 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Truth Table
VLED1+
7
Output IC
VDD1 3
13
Input IC
12
VIN+ 1
VIN– 2
VDD2
VS
FAULT 6
GND1
VLED1–
Driver
LED1
Gate Drive
Optocoupler
UVLO
11
4
8
Shield
DESAT
9,10
14
RESET
VO
5
Fault
16
LED2
VSS
DESAT
VE
Fault Sense
Optocoupler
Shield
15
VLED2+
Figure 2. Functional Block Diagram
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.1
www.fairchildsemi.com
3
FOD8316 — 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Block Diagram
As per DIN EN/IEC 60747-5-5, this optocoupler is suitable for “safe electrical insulation” only within the safety limit
data. Compliance with the safety ratings must be ensured by means of protective circuits.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Installation Classifications per DIN VDE 0110/1.89 Table 1
Rated Mains Voltage < 150 VRMS
I–IV
Rated Mains Voltage < 300 VRMS
I–IV
Rated Mains Voltage < 450 VRMS
I–IV
Rated Mains Voltage < 600 VRMS
I–IV
Rated Mains Voltage < 1000 VRMS
I–III
Climatic Classification
40/100/21
Pollution Degree (DIN VDE 0110/1.89)
2
CTI
Comparative Tracking Index (DIN IEC 112/VDE 0303 Part 1)
175
VPR
Input-to-Output Test Voltage, Method b, VIORM x 1.875 = VPR,
100% Production Test with tm = 1 s, Partial Discharge < 5 pC
2651
Vpeak
Input-to-Output Test Voltage, Method a, VIORM x 1.6 = VPR,
Type and Sample Test with tm = 10 s, Partial Discharge < 5 pC
2262
Vpeak
VIORM
Maximum Working Insulation Voltage
1414
Vpeak
VIOTM
Highest Allowable Over Voltage
8000
Vpeak
External Creepage
8.0
mm
External Clearance
8.0
mm
Insulation Thickness
0.5
mm
150
°C
100
mW
600
mW
109
Ω
Safety Limit Values – Maximum Values in Failure;
TCase
Case Temperature
Safety Limit Values – Maximum Values in Failure;
PS,INPUT
Input Power
Safety Limit Values – Maximum Values in Failure;
PS,OUTPUT
RIO
Output Power
Insulation Resistance at TS, VIO = 500 V
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.1
www.fairchildsemi.com
4
FOD8316 — 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Safety and Insulation Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. TA = 25ºC unless otherwise specified.
Symbol
Parameter
Value
Units
TSTG
Storage Temperature
-40 to +125
ºC
TOPR
Operating Temperature
-40 to +100
ºC
TJ
Junction Temperature
TSOL
Lead Wave Solder Temperature
(no solder immersion)
-40 to +125
ºC
260 for 10 seconds
ºC
15
mA
Refer to reflow temperature profile on page 27.
IFAULT
Fault Output Current
Current(1)
IO(PEAK)
Peak Output
VE – VSS
Negative Output Supply Voltage(2)
VDD2 – VE
Positive Output Supply Voltage
VO(peak)
VDD2 – VSS
VDD1
VIN+, VIN- and VRESET
VFAULT
VS
A
V
-0.5 to 35 – (VE – VSS)
V
Gate Drive Output Voltage
-0.5 to 35
V
Output Supply Voltage
-0.5 to 35
V
Positive Input Supply Voltage
-0.5 to 6
V
Input Voltages
-0.5 to VDD1
V
Fault Pin Voltage
-0.5 to VDD1
V
VSS + 6.5 to VDD2
V
VE to VE + 11
V
100
mW
600
mW
Source of Pull-up PMOS Transistor Voltage
DESAT Voltage
VDESAT
3
0 to 15
Dissipation(3)(5)
PDI
Input Power
PDO
Output Power Dissipation(4)(5)
Notes:
1. Maximum pulse width = 10 µs, maximum duty cycle = 0.2%.
2. This negative output supply voltage is optional. It’s only needed when negative gate drive is implemented. Refer to
“Dual Supply Operation – Negative Bias at Vss” on page 23.
3. No derating required across temperature range.
4. Derate linearly above 64°C, free air temperature at a rate of 10.2 mW/°C
5. Functional operation under these conditions is not implied. Permanent damage may occur if the device is subjected
to conditions outside these ratings.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
TA
VDD1
VDD2 – VSS
Parameter
Ambient Operating Temperature
Min.
Max.
Unit
-40
+100
ºC
Supply Voltage(6)
3
5.5
V
Total Output Supply Voltage
15
30
V
Input
VE – VSS
Negative Output Supply Voltage
0
15
V
VDD2 – VE
Positive Output Supply Voltage(6)
15
30 – (VE – VSS)
V
VSS + 7.5
VDD2
V
VS
Source of Pull-up PMOS Transistor Voltage
Note:
6. During power up or down, it is important to ensure that VIN+ remains low until both the input and output supply
voltages reaches the proper recommended operating voltages to avoid any momentary instability at the output state.
See also the discussion in the “Time to Good Power” section on page 23.
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.1
www.fairchildsemi.com
5
FOD8316 — 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Absolute Maximum Ratings
Apply over all recommended conditions, typical value is measured at TA = 25ºC
Symbol
Parameter
Conditions
Min.
4,243
VISO
Input-Output Isolation
Voltage
TA = 25°C, Relative Humidity < 50%,
t = 1.0 minute, II-O ≤ 10 µA,
50 Hz(7)(8)(9)
RISO
Isolation Resistance
VI-O = 500 V(7)
CISO
Isolation Capacitance
VI-O = 0 V, Freq = 1.0
MHz(7)
Typ.
Max.
Units
VRMS
1011
Ω
1
pF
Notes:
7. Device is considered a two terminal device: pins 1 to 8 are shorted together and pins 9 to 16 are shorted together.
8. 4,243 VRMS for 1-minute duration is equivalent to 5,091 VRMS for 1-second duration.
9. The input-output isolation voltage is a dielectric voltage rating as per UL1577. It should not be regarded as an
input-output continuous voltage rating. For the continuous working voltage rating refer to your equipment-level
safety specification or DIN EN/IEC 60747-5-5 Safety and Insulation Ratings Table.
Electrical Characteristics
Apply over all recommended conditions, typical value is measured at VDD1 = 5V, VDD2 – VSS = 30 V, VE – VSS = 0 V,
and TA = 25°C; unless otherwise specified.
Symbol
Parameter
Conditions
VIN+L, VIN-L,
VRESETL
Logic Low Input Voltages
VIN+H, VIN-H,
VRESETH
Logic High Input Voltages
IIN+L, IIN-L,
IRESETL
Logic Low Input Currents
VIN = 0.4 V
IFAULTL
FAULT Logic Low Output Current
VFAULT = 0.4 V
IFAULTH
FAULT Logic High Output Current VFAULT = VDD1
High Level Output Current
VO = VDD2 – 3 V
IOH
Low Level Output Current
Typ.
Max.
0.8
2.0
-0.5
VO = VDD2 – 6 V(10)
IOL
Min.
VO = VSS + 3 V
Units Figure
V
V
-0.001
mA
5.0
12.0
mA
3, 34
-40
0.002
µA
34
-1
-3
A
4, 9, 35
-2.5
1
VO = VSS + 6 V(11)
2.5
90
IOLF
Low Level Output Current During
Fault Condition
VO – VSS = 14 V
VOH
High Level Output Voltage
IO = –100 mA(12)(13)(14) VS – 1.0 V
VOL
Low Level Output Voltage
IO = 100 mA
IDD1H
High Level Supply Current
IDD1L
Low Level Supply Current
IDD2H
High Level Output Supply Current VO = Open(14)
IDD2L
A
3
A
185
230
mA
6, 40
V
7, 9, 37
0.1
0.5
V
8, 10,
37
VIN+ = VDD1 = 5.5 V,
VIN– = 0 V
14
17
mA
11, 38
VIN+ = VIN- = 0 V,
VDD1 = 5.5 V
2
3
mA
1
3
mA
VS – 0.5 V
Low Level Output Supply Current
VO = Open
0.8
2.8
mA
ISH
High Level Source Current
IO = 0 mA
0.65
1.5
mA
ISL
Low Level Source Current
IO = 0 mA
0.6
1.4
IEL
VE Low Level Supply Current
IEH
VE High Level Supply Current
ICHG
Blanking Capacitor Charge
Current
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.1
5, 36
A
VDESAT = 2 V(14)(15)
-0.5
-0.2
-0.5
-0.25
-0.13
-0.25
12, 13,
39
39
mA
39
mA
15, 39
mA
-0.37
mA
14, 40
www.fairchildsemi.com
6
FOD8316 — 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Isolation Characteristics
Apply over all recommended conditions, typical value is measured at VDD1 = 5 V, VDD2 – VSS = 30 V, VE – VSS = 0V,
and TA = 25°C; unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
10
36
Max.
Units Figure
IDSCHG
Blanking Capacitor
Discharge Current
VDESAT = 7 V
VUVLO+
Under Voltage Lockout
Threshold(14)
VO > 5 V @ 25°C
9
10
V
Under Voltage Lockout
Threshold Hysteresis
@ 25°C
0.4
1.5
V
DESAT Threshold(14)
VDD2 – VE > VULVO- ,
VO < 5 V
6.0
7.0
VUVLOUVLOHYS
VDESAT
VO < 5 V @ 25°C
11.5
13.5
9.0
mA
40
V
17, 31,
41
V
18, 40
Notes:
10. Maximum pulse width = 10 µs, maximum duty cycle = 0.2%.
11. Maximum pulse width = 4.99 ms, maximum duty cycle = 99.8%.
12. VOH is measured with the DC load current in this testing (Maximum pulse width = 1 ms, maximum duty
cycle = 20%).When driving capacitive loads, VOH will approach VDD as IOH approaches zero units.
13. Positive output supply voltage (VDD2 – VE) should be at least 15 V to ensure adequate margin in excess of the
maximum under-voltage lockout threshold, VUVLO+, of 13.5 V.
14. When VDD2 – VE > VUVLO and output state VO is allowed to go high, the DESAT detection feature is active and
provides the primary source of IGBT protection. UVLO is needed to ensure DESAT detection is functional.
15. The blanking time, tBLANK, is adjustable by an external capacitor (CBLANK), where tBLANK = CBLANK × (VDESAT / ICHG).
Switching Characteristics
Apply over all recommended conditions, typical value is measured at VDD1 = 5 V, VDD2 – VSS = 30 V, VE – VSS = 0 V,
and TA = 25°C; unless otherwise specified.
Symbol
Parameter
tPHL
Propagation Delay Time to
Logic Low Output(17)
tPLH
Propagation Delay Time to
Logic High Output(18)
PWD
Pulse Width Distortion,
| tPHL – tPLH|(19)
PDD Skew
Conditions
Min.
Rg = 10 Ω, Cg = 10nF,
f = 10 kHz,
Duty Cycle = 50%(16)
Typ.
Max.
300
500
ns
250
500
ns
50
300
ns
350
ns
–350
Propagation Delay Difference
Between Any Two Parts or
Channels, ( tPHL – tPLH)(20)
Units Figure
tR
Output Rise Time (10% to 90%)
34
ns
tF
Output Fall Time (90% to 10%)
34
ns
tDESAT(90%)
DESAT Sense to 90% VO Delay(21)
tDESAT(10%)
DESAT Sense to 10% VO Delay(21)
tDESAT(FAULT)
tDESAT(LOW)
tRESET(FAULT)
PWRESET
Rg = 10 Ω, Cg = 10 nF,
VDD2 – VSS = 30 V
42, 50
ns
25, 43
2
3
µs
26, 28,
29, 43
DESAT Sense to Low Level FAULT
Signal Delay(22)
1.8
5
µs
27, 43,
51
DESAT Sense to DESAT Low
Propagation Delay(23)
850
ns
43
µs
30, 44,
51
RESET to High Level FAULT Signal
Delay(24)
3
RESET Signal Pulse Width
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.1
850
19, 20,
21, 22,
23, 24,
42, 50
1.2
6
20
µs
www.fairchildsemi.com
7
FOD8316 — 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Electrical Characteristics (Continued)
Apply over all recommended conditions, typical value is measured at VDD1 = 5 V, VDD2 – VSS = 30 V, VE – VSS = 0 V,
and TA = 25°C; unless otherwise specified.
Symbol
Parameter
tUVLO ON
UVLO Turn On Delay(25)
tUVLO OFF
(26)
tGP
UVLO Turn Off Delay
Time to Good Power
(27)
Conditions
Min.
Typ.
Max.
Units Figure
VDD2 = 20V in
1.0ms Ramp
4
µs
31, 45
3
µs
VDD2 = 0 to 30V in
10µs Ramp
30
µs
32, 33,
45
| CMH |
Common Mode Transient
Immunity at Output High
TA = 25ºC, VDD1 = 5V,
VDD2 = 25V,
VSS = Ground,
VCM = 1500Vpk(28)
35
50
kV/µs
47, 48
| CML |
Common Mode Transient
Immunity at Output Low
TA = 25ºC, VDD1 = 5V,
VDD2 = 25V,
VSS = Ground,
VCM = 1500Vpk(29)
35
50
kV/µs
46, 49
Notes:
16. This load condition approximates the gate load of a 1200 V / 150 A IGBT.
17. Propagation delay tPHL is measured from the 50% level on the falling edge of the input pulse (VIN+, VIN-) to the 50%
level of the falling edge of the VO signal. Refer to Figure 50.
18. Propagation delay tPLH is measured from the 50% level on the rising edge of the input pulse (VIN+, VIN-) to the 50%
level of the rising edge of the VO signal. Refer to Figure 50.
19. PWD is defined as | tPHL – tPLH | for any given device.
20. The difference between tPHL and tPLH between any two FOD8316 parts under same operating conditions with equal
loads.
21. This is the amount of time the DESAT threshold must be exceeded before VO begins to go LOW. This is supply
voltage dependent. See Figure 51.
22. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes LOW.
See Figure 51.
23. The length of time the DESAT threshold must be exceeded before VO begins to go LOW, and the FAULT output
begins to go LOW. See Figure 51.
24. The length of time from when RESET is asserted LOW, until FAULT output goes HIGH. See Figure 51.
25. The UVLO turn-on delay, tUVLO ON, is measured from VUVLO+ threshold voltage of the output supply voltage (VDD2)
to the 5 V level of the rising edge of the VO signal.
26. The UVLO turn-off delay, tUVLO OFF, is measured from VUVLO– threshold voltage of the output supply voltage (VDD2)
to the 5 V level of the falling edge of the VO signal.
27. The time to good power, tGP, is measured from 13.5 V level of the rising edge of the output supply voltage (VDD2)
to the 5 V level of the rising edge of the VO signal.
28. Common-mode transient immunity at output HIGH state is the maximum tolerable negative dVCM/dt on the trailing
edge of the common-mode pulse, VCM, to assure the output will remain in HIGH state (i.e., VO > 15 V or
FAULT > 2 V).
29.Common-mode transient immunity at output LOW state is the maximum positive tolerable dVCM/dt on the leading
edge of the common-mode pulse, VCM, to assure the output will remain in LOW state (i.e., VO < 1.0 V or
FAULT < 0.8 V).
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.1
www.fairchildsemi.com
8
FOD8316 — 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Switching Characteristics (Continued)
7
IOH – OUTPUT HIGH CURRENT (A)
IFAULTL – FAULT CURRENT (mA)
50
40
30
20
VDD1 = 5 V
VIN+ = 5 V
ILED2+ = 10 mA
TA = 25°C
10
0
0
1
2
3
4
6
5
VO = V DD2 – 6 V
4
3
VO = V DD2 – 3 V
2
1
VDD2 – V SS = 30 V
VDD1 = 5V
0
-40
-20
0
5
VFAULTL – FAULT VOLTAGE (V)
Figure 3. Fault Logic Low Output Current (IFAULTL)
vs. Fault Logic Low Output Voltage (VFAULTL)
60
80
100
225
IOLF – LOW LEVEL OUTPUT CURRENT
DURING FAULT CONDITIONS (mA)
IOL – OUTPUT LOW CURRENT (A)
40
Figure 4. Output High Current (IOH)
vs. Temperature
7
6
5
VO = V SS + 6 V
4
3
VO = V SS + 3 V
2
1
0
-40
VDD2 – V SS = 30 V
VDD1 = 5 V
-20
0
20
40
60
80
TA = -40°C
200
TA = 25°C
175
150
125
100
75
VDD2 – V SS = 30 V
VDD1 = 5 V
50
25
0
100
TA = 100°C
5
TA – TEMPERATURE (°C)
20
25
30
0.25
VOL – OUTPUT LOW VOLTAGE (V)
IO = -650 μA
0
-0.1
IO = -100 mA
-0.2
-0.3
-0.5
-40
15
Figure 6. Low Level Output Current (IOLF) vs.
Output Voltage (VO)
0.1
-0.4
10
VO – OUTPUT VOLTAGE (V)
Figure 5. Output Low Current (IOL) vs.
Temperature
(VOH–VDD2) – HIGH OUTPUT VOLTAGE DROP (V)
20
TA – TEMPERATURE (°C)
VDD2 – V SS = 30 V
VDD1 = 5 V
VIN+ = 5 V
-20
0
20
40
60
80
0.15
IO = 100 mA
0.10
0.05
0
-40
100
TA – TEMPERATURE (°C)
VDD2 – V SS = 30 V
VDD1 = 5 V
VIN+ = 0 V
-20
0
20
40
60
80
100
TA – TEMPERATURE (°C)
Figure 7. Output High Voltage (VOH–VDD2)
vs. Temperature
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.1
0.20
Figure 8. Output Low Voltage (VOL)
vs. Temperature
www.fairchildsemi.com
9
FOD8316 — 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Typical Performance Characteristics
5
VOL – OUTPUT LOW VOLTAGE (V)
VOH – OUTPUT HIGH VOLTAGE (V)
30
29
TA = -40°C
25°C
28
100°C
27
26
VDD2 – V SS = 30 V
VDD1 = 5 V
VIN+ = 5 V
25
0
0.5
1.0
1.5
2.0
VDD2 – V SS = 30 V
VDD1 = 5 V
VIN+ = 0 V
4
3
TA = 100°C
2
25°C
-40°C
1
0
2.5
0
0.5
IOH – OUTPUT HIGH CURRENT (A)
Figure 9. Output High Voltage (VOH) vs.
Output High Current (IOH)
2.0
2.5
1.4
IDD2 – OUTPUT SUPPLY CURRENT (mA)
VDD1 = 5.5 V
VIN+= 5 V (I DD1H) or 0 V (I DD1L)
15
IDD1H
10
5
IDD1L
0
-40
-20
0
20
40
60
80
1.2
IDD2H
1.0
0.8
IDD2L
0.6
VDD2 – V SS = 30 V
VDD1 = 5 V
VIN+ = 5 V (I DD2H) or 0 V (I DD2L)
0.4
-40
100
-20
0
TA – TEMPERATURE (°C)
20
40
60
80
100
TA – TEMPERATURE (°C)
Figure 11. Supply Current (IDD1)
vs. Temperature
Figure 12. Output Supply Current (IDD2)
vs. Temperature
1.2
-0.15
ICHG – BLANKING CAPACITOR CHARGING
CURRENT (mA)
IDD2 – OUTPUT SUPPLY CURRENT (mA)
1.5
Figure 10. Output Low Voltage (VOL) vs.
Output Low Current (IOL)
20
IDD1 – SUPPLY CURRENT (mA)
1.0
IOL – OUTPUT LOW CURRENT (A)
VDD1 = 5 V
VIN+ = 5 V (I DD2H) or 0 V (I DD2L)
1.0
IDD2H
0.8
IDD2L
0.6
0.4
15
20
25
VDD2 – V SS = 30 V
VDD1 = 5 V
VIN+ = 5 V
VDESAT = 0 V to 6 V
-0.20
-0.25
-0.30
-40
30
-20
0
20
40
60
80
100
VDD2 – OUTPUT SUPPLY VOLTAGE (V)
TA – TEMPERATURE (°C)
Figure 13. Output Supply Current (IDD2) vs.
Output Supply Voltage (VDD2)
Figure 14. Blanking Capacitor Charging
Current (ICHG) vs. Temperature
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.1
www.fairchildsemi.com
10
FOD8316 — 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Typical Performance Characteristics (Continued)
3.0
-0.15
2.5
IS – SOURCE CURRENT (mA)
IE – SUPPLY CURRENT (mA)
-0.10
IEL
-0.20
IEH
-0.25
-0.30
-0.35
VDD2 – V SS = 30 V
VDD1 = 5 V
VIN+ = 5 V (I EH) / 0 V (I EL)
-0.40
-40
-20
0
20
40
60
80
2.0
1.5
1.0
0.5
0
100
-40°C
25°C
100°C
VDD2 – V SS = 30 V
VDD1 = 5 V
VIN+ = 5 V
0
0.5
1.0
TA – TEMPERATURE (°C)
Figure 15. Supply Current (IE) vs.
Temperature
V UVLO – UNDER VOLTAGE LOCKOUT THRESHOLD (V)
1.5
2.0
IO – OUTPUT CURRENT (mA)
Figure 16. Source Current (IS) vs.
Output Current (IO)
8.0
VDESAT – DESAT THRESHOLD (V)
15
V UVLO+
10
V UVLO–
5
7.5
7.0
6.5
VDD2 – V SS = 30 V
VDD1 = 5 V
VIN+ = 5 V
VDD1 = 5 V
VIN+ = 5 V
0
-40
-20
0
20
40
60
80
6.0
-40
100
-20
0
20
40
60
80
100
TA – TEMPERATURE (°C)
TA – TEMPERATURE (°C)
Figure 17. Under Voltage Lockout
Threshold (VUVLO) vs. Temperature
Figure 18. DESAT Threshold (VDESAT)
vs. Temperature
0.5
0.45
tP – PROPAGATION DELAY (μs)
tP – PROPAGATION DELAY (μs)
0.40
0.4
tPLH
0.3
tPHL
0.2
0.1
-40
VDD2 – V SS = 30 V
VDD1 = 5 V
f = 10 kHz 50% Duty Cycle
RL = 10 Ω, C L = 10 nF
-20
0
20
40
60
80
tPLH
0.30
tPHL
0.25
0.20
0.15
0.10
15
100
TA – TEMPERATURE (°C)
VDD1 = 5 V
f = 10 kHz 50% Duty Cycle
RL = 10 Ω, CL = 10 nF
20
25
30
VDD2 – SUPPLY VOLTAGE (V)
Figure 20. Propagation Delay (tP) vs.
Supply Voltage (VDD2)
Figure 19. Propagation Delay (tP)
vs. Temperature
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.1
0.35
www.fairchildsemi.com
11
FOD8316 — 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Typical Performance Characteristics (Continued)
0.35
VDD2 – V SS = 30 V
f = 10 kHz 50% Duty Cycle
RL = 10 Ω, CL = 10 nF
tPHL – PROPAGATION DELAY (μs)
tPLH – PROPAGATION DELAY (μs)
0.45
0.40
0.35
0.30
VDD1 = 4.5 V
VDD1 = 5.0 V
VDD1 = 5.5 V
0.25
-40
-20
0
20
40
60
80
VDD2 – V SS = 30 V
f = 10 kHz 50% Duty Cycle
RL = 10 Ω, CL = 10 nF
0.30
0.25
0.20
VDD1 = 4.5 V
VDD1 = 5.0 V
VDD1 = 5.5 V
0.15
-40
100
-20
0
TA – TEMPERATURE (°C)
60
80
100
0.40
VDD2 – V SS = 30 V
VDD1 = 5 V
f = 10 kHz 50% Duty Cycle
RL = 10 Ω
0.35
tP – PROPAGATION DELAY (μs)
tP – PROPAGATION DELAY (μs)
0.40
tPLH
0.30
tPHL
0.25
0
20
40
60
80
0.35
tPLH
0.30
tPHL
0.25
0.20
100
VDD2 – V SS = 30 V
VDD1 = 5 V
f = 10 kHz 50% Duty Cycle
CL = 10 nF
0
10
CL – LOAD CAPACITANCE (nF)
tDESAT(10%) – DESAT SENSE TO 10% VO DELAY (μs)
VDD2 – V SS = 30 V
VDD1 = 5 V
VIN+ = 5 V
RL = 10 Ω, CL = 10 nF
1.1
1.0
0.9
-20
0
20
40
60
80
100
TA – TEMPERATURE (°C)
40
50
3.0
VDD2 – V SS = 15 or 30 V
VDD1 = 5 V
VIN+ = 5 V
RL = 10 Ω, CL = 10 nF
2.5
VDD2 – V SS = 30 V
2.0
VDD2 – V SS = 15 V
1.5
1.0
-40
-20
0
20
40
60
80
100
TA – TEMPERATURE (°C)
Figure 25. DESAT Sense to 90%
VO (tDESAT(90%)) vs. Temperature
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.1
30
Figure 24. Propagation Delay (tP) vs.
Load Resistance (RL)
1.2
0.8
-40
20
RL – LOAD RESISTANCE (Ω)
Figure 23. Propagation Delay (tP) vs.
Load Capacitance (CL)
tDESAT(90%) – DESAT SENSE TO 90% VO DELAY (μs)
40
Figure 22. Propagation Delay Time to
Logic Low Output (tPHL) vs. Temperature
Figure 21. Propagation Delay Time to
Logic High Output (tPLH) vs. Temperature
0.20
20
TA – TEMPERATURE (°C)
Figure 26. DESAT Sense to 10% VO
Delay (tDESAT(10%)) vs. Temperature
www.fairchildsemi.com
12
FOD8316 — 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Typical Performance Characteristics (Continued)
0.008
VDD2 – V SS = 30 V
VDD1 = 5 V
VIN+ = 5 V
RL = 10 Ω, CL = 10 nF
2.4
tDESAT(10%) – DESAT SENSE TO 10% VO
tDESAT(FAULT) – DESAT SENSE TO LOW FAULT
SIGNAL DELAY (μs)
2.6
2.2
VE – V SS = 0 V
VE – V SS = 15 V
2.0
1.8
1.6
-40
-20
0
20
40
60
80
100
VDD2 – V SS = 15 V or 30 V
VDD1 = 5 V
VIN+ = 5 V
RL = 10 Ω
0.006
VDD2 – V SS = 30 V
0.004
0.002
0
VDD2 – V SS = 15 V
0
5
TA – TEMPERATURE (°C)
15
20
25
30
Figure 28. DESAT Sense to 10% VO
Delay (tDESAT(10%)) vs. Load Capacitance (CL)
0.0030
10
VDD2 – V SS = 15 V or 30 V
VDD1 = 5 V
VIN+ = 5 V
CL = 10 nF
tRESET(FAULT) – RESET TO HIGH LEVEL FAULT
SIGNAL DELAY (μs)
tDESAT(10%) – DESAT SENSE TO 10% VO DELAY (μs)
Figure 27. DESAT Sense to Low Fault Signal
Delay (tDESAT(FAULT)) vs. Temperature
0.0250
VDD2 – V SS = 30 V
0.0020
VDD2 – V SS = 15 V
0.0015
0.0010
10
20
30
40
50
9
VDD2 – V SS = 30 V
VIN+ = 5 V
RL = 10 Ω, C L = 10 nF
8
VDD1 = 5.5 V
7
VDD1 = 5.0 V
6
VDD1 = 4.5 V
5
4
-40
RL – LOAD RESISTANCE (Ω)
-20
0
20
40
60
80
100
TA – TEMPERATURE (°C)
Figure 30. RESET to High Level FAULT
Signal Delay (tRESET(FAULT)) vs. Temperature
Figure 29. DESAT Sense to 10% VO
Delay (tDESAT(10%)) vs. Load Resistance (RL)
10
100
VDD2 = 20 V
VDD1 = 5 V
VIN+ = 5 V
f = 50 Hz, 50% Duty Cycle
tR = 1 ms
8
tGP – TIME TO GOOD POWER (μs)
tUVLO – UNDER VOLTAGE LOCKOUT
THRESHOLD DELAY (μs)
10
CL – LOAD CAPACITANCE (nF)
6
tUVLO ON
4
tUVLO OFF
2
0
-40
-20
0
20
40
60
80
80
60
40
20
0
15
100
TA – TEMPERATURE (°C)
20
30
25
VDD2 – SUPPLY VOLTAGE (V)
Figure 31. Under Voltage Lockout Threshold
Delay (tUVLO) vs. Temperature
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.1
VDD1 = 5 V
VIN+ = 5 V
f = 50 Hz, 50% Duty Cycle
Figure 32. Time to Good Power (tGP)
vs. Supply Voltage (VDD2)
www.fairchildsemi.com
13
FOD8316 — 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Typical Performance Characteristics (Continued)
FOD8316 — 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Typical Performance Characteristics (Continued)
tGP – TIME TO GOOD POWER (μs)
120
100
VDD2 = 15 V to 30 V
VDD1 = 5 V
VIN+ = 5 V
f = 50 Hz 50% Duty Cycle
80
60
40
20
0
-40
-20
0
20
40
60
80
100
TA – TEMPERATURE (°C)
Figure 33. Time to Good Power (tGP)
vs. Temperature
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.1
www.fairchildsemi.com
14
5V
VFAULT
+
–
FOD8316
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
8
VLED1-*
VSS
A
0.1 μF
10 mA
0.1 μF
–
+
IFAULT
VFAULT = 0.4 V for IFAULTL
VDD2 13
9
Switch A closed for IFAULTL
Switch A opened for IFAULTH
VFAULT = 5.0 V for IFAULTH
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 34. Fault Output Current (IFAULTL) and (IFAULTH) Test Circuit
Pulse Gen
PW = 10 μs
Period = 5 ms
+
–
0.1 μF
5V
–
+
FOD8316
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
8
VLED1-*
VSS
VDD2 13
+
–
0.1μF
0.1 μF 47 μF
VE
0.1 μF 47 μF
+
–
VO
+
–
30 V
3 kΩ
9
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 35. High Level Output Current (IOH) Test Circuit
Pulse Gen
PW = 4.99 ms
Period = 5 ms
+
–
0.1 μF
5V
–
+
FOD8316
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
8
VLED1-*
VSS
0.1 μF
+
–
VE
+
–
30 V
VDD2 13
0.1 μF 47 μF
3 kΩ
VO
+
–
9
0.1 μF 47 μF
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 36. Low Level Output Current (IOL) Test Circuit
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.1
www.fairchildsemi.com
15
FOD8316 — 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Test Circuits
FOD8316 — 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Test Circuits (Continued)
A
B
5V
0.1 μF
+
–
FOD8316
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
8
VLED1-*
VSS
0.1 μF
VDD2 13
+
–
100 mA
pulsed
VO
3 kΩ
Switch A for VOH test
Switch B for VOL test
VE
100 mA
pulsed
30 V
B
A
0.1 μF
+
–
9
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 37. High Level (VOH) and Low Level (VOL) Output Voltage Test Circuit
A
B
5V
0.1 μF
+
–
FOD8316
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
8
VLED1-*
VSS
IDD1
Switch A for IDD1H test
Switch B for IDD1L test
VDD2 13
9
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 38. High Level (IDD1H) and Low Level (IDD1L) Supply Current Test Circuit
A
B
0.1 μF
5V
+
–
FOD8316
IE
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
8
VLED1-*
VSS
Switch A for IDD2H, ISH and IEH test
Switch B for IDD2L, ISL and IEL test
VDD2 13
0.1 μF
VE
+
–
IDD2
IS
VO
0.1 μF
30 V
+
–
9
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 39. High Level (IDD2H), Low Level (IDD2L) Output Supply Current,
High Level (ISH), Low Level (ISL) Source Current,
VE High Level (IEH), and VE Low Level (IEL) Supply Current Test Circuit
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.1
www.fairchildsemi.com
16
+
–
VE 16
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VDESAT
+
–
5V
0.1 μF
FOD8316
1
ICHG/DSCHG
0.1 μF
VE
+
–
VDD2 13
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
8
VLED1-*
VSS
VRL
VO
0.1 μF
IOLF
3 kΩ
30 V
RL
+
–
10 nF
9
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 40. Low Level Output Current During Fault Conditions (IOLF), Blanking Capacitor Charge Current (ICHG),
Blanking Capacitor Discharging Current (IDSCHG) and DESAT Threshold (VDESAT) Test Circuit
0.1 μF
5V
+
–
FOD8316
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
8
VLED1-*
VSS
VDD2 13
DC Sweep
0 to 15 V
(100 steps)
Parameter
Analyzer
VO
0.1 μF
+
–
9
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 41. Under Voltage Lockout Threshold (VUVLO) Test Circuit
F = 10 kHz
DC = 50%
+
–
0.1 μF
5V
+
–
FOD8316
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
8
VLED1-*
VSS
0.1 μF
VE
+
–
VDD2 13
VCL
VO
0.1 μF
30 V
+
–
RL
3 kΩ
10 nF
9
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 42. Propagation Delay (tPLH, tPHL), Pulse Width Distortion (PWD),
Rise Time (tR) and Fall Time (tF) Test Circuit
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.1
www.fairchildsemi.com
17
FOD8316 — 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Test Circuits (Continued)
Low to High
+
–
5V
0.1 μF
+
–
FOD8316
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
8
VLED1-*
VSS
100 pF
0.1 μF
+
–
VE
VDD2 13
VO
+
–
30 V
0.1 μF
RL
3 kΩ
VFAULT
10 nF
9
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 43. DESAT Sense (tDESAT(90%), tDESAT(10%)), DESAT Fault (tDESAT(FAULT)), and (tDESAT(LOW)) Test Circuit
5V
0.1 μF
+
–
3 kΩ
FOD8316
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
–
8
VLED1-*
VSS
Strobe 8 V
0.1 μF
+
–
VE
VDD2 13
VO
0.1 μF
+
–
30 V
RL
+
VFAULT
VE 16
1
10 nF
9
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 44. Reset Delay (tRESET(FAULT)) Test Circuit
0.1 μF
5V
+
–
FOD8316
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
8
VLED1-*
VSS
0.1 μF
VE
+
–
VDD2 13
VO
+
3 kΩ
0.1 μF
VDD2**
–
9
**1.0 ms ramp for tUVLO
10 μs ramp for tGP
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 45. Under Voltage Lockout Delay (tUVLO) and Time to Good Power (tGP) Test Circuit
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.1
www.fairchildsemi.com
18
FOD8316 — 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Test Circuits (Continued)
5V
0.1 μF
1 kΩ
FOD8316
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
25 V
0.1 μF
VDD2 13
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
8
VLED1-*
VSS
SCOPE
10 Ω
300 pF
10nF
9
VCM
Floating GND
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 46. Common Mode Low (CML) Test Circuit @ LED1 Off
5V
FOD8316
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
10 Ω
8
VLED1-*
VSS
10 nF
0.1 μF
25 V
VDD2 13
0.1 μF
1 kΩ
300 pF
Floating GND
9
SCOPE
VCM
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 47. Common Mode High (CMH) Test Circuit @ LED1 On
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.1
www.fairchildsemi.com
19
FOD8316 — 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Test Circuits (Continued)
FOD8316 — 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Test Circuits (Continued)
5V
0.1 μF
FOD8316
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
10 Ω
8
VLED1-*
VSS
10 nF
25 V
VDD2 13
0.1 μF
1 kΩ
SCOPE
300 pF
9
VCM
Floating GND
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 48. Common Mode High (CMH) Test Circuit @ LED2 Off
5V
0.1 μF
FOD8316
VE 16
1
VIN+
2
VIN–
VLED2+ 15
3
VDD1
DESAT 14
4
GND1
25 V
750 Ω
VDD2 13
0.1 μF
1 kΩ
SCOPE
300 pF
5
RESET
VS 12
6
FAULT
VO 11
7
VLED1+
VSS 10
10 Ω
8
VLED1-*
VSS
10 nF
VCM
9
+
–
9V
Floating GND
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 49. Common Mode Low (CML) Test Circuit @ LED2 On
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.1
www.fairchildsemi.com
20
VIN+
2.5 V
VIN–
0V
2.5 V
tR
tF
90%
50%
10%
VO
tPLH
tPHL
Figure 50. Propagation Delay (tPLH, tPHL), Rise Time (tR) and Fall Time (tF) Timing Diagram
RESET
50%
7V
VDESAT
tDESAT (LOW)
tRESET (FAULT)
50%
tDESAT (90%)
90%
VO
10%
tDESAT (10%)
50% (0.5 x VDD1)
FAULT
tDESAT (FAULT)
Figure 51. Definitions for Fault Reset Input (RESET), Desaturation Voltage Input (DESAT), Output Voltage (VO)
and Fault Output (FAULT) Timing Waveforms
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.1
www.fairchildsemi.com
21
FOD8316 — 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Timing Diagrams
Micro
Controller
5V +
–
1 kΩ
1
VIN+
2
VE
16
VIN–
VLED2+
15
3
VDD1
DESAT
14
4
GND1
VDD2
13
5
RESET
VS
12
6
FAULT
VO
11
7
VLED1+
VSS
10
8
VLED1-
VSS
9
0.1 μF
330 pF
FOD8316
C2
1 μF
C3
10 μF
100 pF
100 Ω
C1
1 μF
+
–
+
–
VF
VDD2 = 15 V
+
Q1
VCE
Rg
+
–
D1
DDESAT
VSS = –8 V
–
3-Phase
Output
Q2
+
VCE
–
*Pin 8 (VLED1-) is internally connected to pin 4 (GND1).
Figure 52. Recommended Application Circuit
Functional Description
The relationship between the inputs and output are
illustrated in the Figure 54.
The typical application circuit is shown in Figure 52 and
the functional behavioral of the FOD8316 is illustrated by
the detailed internal schematic shown in Figure 53. This
helps explain the interaction and sequence of internal
and external signals, together with the timing diagrams.
1. Non-Inverting and Inverting Inputs
During normal operation, when no fault is detected, the
FAULT output, which is an open-drain configuration, will
be latched to HIGH state. This allows the gate driver to
be controlled by the input logic signal.
There are two CMOS/TTL compatible inputs, VIN+ and
VIN- to control the IGBT, in non-inverting and inverting
configurations respectively. When VIN- is set to LOW,
VIN+ controls the driver output, VO, in non-inverting configuration. When VIN+ is set to HIGH, VIN- controls the
driver output in inverting configuration.
When a fault is detected, the FAULT output will be
latched to LOW state. This condition will remain until the
RESET pin is also pulled low for a period longer than
PWRESET. While setting the RESET pin to a low state,
the input pins must be pulled to low to ensure an output
state (VIN+ is low or VIN- is HIGH).
250 μA
+
–
VLED+
VDD1 3
7
VIN+ 1
VIN– 2
FAULT
14
Gate Drive
Optocoupler
16
UVLO Comparator
6
–
+
13
12 V
12
4
GND1
VLED1–
VE
VDD2
VS
Delay
8
11
Q
R S
RESET
DESAT
VDESAT
5
Fault Sense
Optocoupler
VO
50x
5μs Pulse
Generator
1x
9,10
VSS
15
VLED2+
Figure 53. Detailed Internal Schematic
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.1
www.fairchildsemi.com
22
FOD8316 — 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Application Information
4. “Soft” Turn-Off
A pair of PMOS and NMOS transistors made up the
output driver stage, which facilitates close to rail-to-rail
output swing. This feature allows a tight control of gate
voltage during on-state and short circuit condition. The
output driver is typically capable of sinking 2 A and
sourcing 2 A at room temperature. Due to the low
RDS(ON) of the MOSFETs, the power dissipation is
reduced as compared to those bipolar-type driver output
stages. The absolute maximum rating of the output peak
current, IO(PEAK) is 3 A, thus the careful selection of the
gate resistor, Rg, is required to limit the short circuit
current of the IGBT.
The soft turn-off feature ensures the safe turn off of the
IGBT under fault condition. This reduces the voltage
spike on the collector of the IGBT. Without this, the IGBT
would see a heavy spike on the collector, resulting in a
permanent damage to the device when it’s turned off
immediately.
5. Under Voltage Lockout (UVLO)
Under voltage detection prevents the application of
insufficient gate voltage to the IGBT. This could be
dangerous, as it would drive the IGBT out of saturation
and into the linear operation where the losses are very
high and quickly overheats. This feature ensures proper
operating of the IGBTs. The output voltage, VO, remains
LOW irregardless of the inputs, as long as the supply
voltage, VDD2 – VE, is less than VULVO+. When the
supply voltage falls below VULVO- , VO goes LOW, as
illustrated in Figure 56.
As shown in Figure 53, the gate driver output is influenced by signals from the photodetector circuitry, the
UVLO comparator, and the DESAT signals. Under no
fault condition, normal operation resumes while the
supply voltage is above the UVLO threshold, the output
of the photodetector will drive the MOSFETs of the
output stage.
6. Time to Good Power
At initial power up, the LED is off and the output of the
gate driver should be in the LOW or OFF state.
Sometimes race conditions exist that cause the output to
follow VD (assuming VDD2 and VE are connected
externally), until all of the circuits in the output IC have
stabilized. This condition can result in output transitions
or transients that are coupled to the driven IGBT. These
transients can cause the high- and low-side IGBTs to
conduct shoot-through current that can damage power
semiconductor devices.
The logic circuitry of the output stage will ensure that the
push-pull devices will never be turned “ON” simultaneously. When the output of the photodetector is HIGH,
the output, VO will be pulled to HIGH state by turning on
the PMOS. When the output of the photodetector is
LOW, VO will be pulled to LOW state by turning on the
NMOS.
When VDD2 supply goes below VUVLO, which is the
designated ULVO threshold at the comparator, VO will
be pulled down to LOW state regardless of photodetector output.
Fairchild has introduced an initial turn-on delay, called
“time to good power”. This delay, typically 30 µs, is only
present during the initial power-up of the device. Once
powered, the “time to good power” delay is determined
by the delay of the UVLO circuitry. If the LED is ON
during the initial turn-on activation, low-to-high transition
at the output of the gate driver will only occur 30 µs after
the VDD2 power is applied.
When desaturation is detected, VO will turn off slowly as
it is pulled low by the NMOS1X device, the input to the
Fault Sense circuitry will be latched to HIGH state and
turns on the LED. When VO goes below 2 V, the
NMOS50X device turns on again, clamping the IGBT
gate firmly to VSS. The Fault Sense signal will remain
latched in the HIGH state until the LED of the gate driver
circuitry turns off.
7. Dual Supply Operation – Negative Bias at VSS
3. Desaturation Protection, FAULT Output
The IGBT’s off-state noise immunity can be enhanced by
providing a negative gate-to-emitter bias when the IGBT
is in the OFF state. This static off-state bias can be
supplied by connecting a separate negative voltage
source between the VE (pin 16) and VSS (pin 9 &10).
Figure 53 illustrates the two distinct grounds. The
primary ground reference is the IGBT’s emitter
connection. VE (pin 16). The under-voltage threshold
and desaturation voltage detection are referenced to the
IGBT’s emitter (VE) ground.
Desaturation detection protection ensures the protection
of the IGBT at short circuit by monitoring the collectoremitter voltage of the IGBT in the half bridge. When the
DESAT voltage goes up and reaches above the
threshold voltage, a short circuit condition is detected
and the driver output stage will execute a “soft” IGBT
turn-off and will be eventually driven low. This sequence
is illustrated in Figure 55. The FAULT open-drain output
is triggered active low to report a desaturation error. It
could only be cleared by activating active low by the
external controller to the RESET input.
The recommended application circuit, Figure 52, shows
the interconnection of the VDD2 and VE supplies. The
IGBT’s gate to emitter voltage is the absolute value sum
of the VDD2 supply and the VSS reverse bias. The
negative voltage supply at VSS appears at the gate drive
input, VO, when the FOD8316 is in the LOW state.
When the input drives the output high, the output
voltage, VO, will have the potential of the VDD2 and VSS.
The DESAT fault detector should be disabled for a short
time period (blanking time) before the IGBT turns on to
allow the collector voltage to fall below DESAT threshold. This blanking period protects against false trigger of
the DESAT while the IGBT is turning on.
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.1
www.fairchildsemi.com
23
FOD8316 — 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
2. Gate Driver Output
VIN–
VIN+
VO
Figure 54. Input/Output Relationship
Normal
Operation
VIN–
VIN+
RESET
Fault Condition
Reset
0V
5V
0V
Blanking
Time
7V
VDESAT
VO
FAULT
Figure 55. Timing Relationship Among Desatuation Voltage (DESAT), Fault Output (FAULT) and
Fault Reset Input (RESET)
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.1
www.fairchildsemi.com
24
FOD8316 — 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
available output current. C3 is a low ESR 1812 style,
10 µF, multilayer ceramic capacitor. This capacitor is the
primary filter for the Vss and VDD2 supplies. C1 and C2
are also low ESR capacitors. They provide the primary
gate charge and discharge paths. The Schottky diode,
D1, is connected between VE and VSS to protect against
a reverse voltage greater than 0.5 V.
Figure 52 shows the operation with a dual or split power
supply. The Vss supply provides the negative gate bias,
and VDD2 + VSS supplies power to the output IC. The
VSS and VDD2 supplies require three power supply
bypass capacitors. These capacitors provide the low
equivalent series resistant (ESR) paths for the
instantaneous gate charging and discharging currents.
Selecting capacitors with low ESR will optimize the
5V
VIN+
0V
VUVLO+
VUVLO–
VDD2 – VE
VO
Figure 56. Under Voltage Lockout (UVLO) for Output Side
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.1
www.fairchildsemi.com
25
FOD8316 — 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
VIN–
Part Number
Package
Packing Method
FOD8316
SO 16-Pin
Tube (50 units per tube)
FOD8316R2
SO 16-Pin
Tape and Reel (750 units per reel)
FOD8316V
SO 16-Pin, DIN EN/IEC 60747-5-5 option
Tube (50 units per tube)
FOD8316R2V
SO 16-Pin, DIN EN/IEC 60747-5-5 option
Tape and reel (750 units per reel)
All packages are lead free per JEDEC: J-STD-020B standard.
Marking Information
1
2
3
8316 V
D X YY KK
4
6
5
J
8
7
Definitions
1
Fairchild logo
2
Device number, e.g., ‘8316’ for FOD8316
3
DIN EN/IEC60747-5-5 Option (only appears on
component ordered with this option)
4
Plant code, e.g., ‘D’
5
Last digit year code, e.g., ‘E’ for 2014
6
Two digit work week ranging from ‘01’ to ‘53’
7
Lot traceability code
8
Package assembly code, e.g., ‘J’
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.1
www.fairchildsemi.com
26
FOD8316 — 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Ordering Information
FOD8316 — 2.5 A Output Current, IGBT Drive Optocoupler with Desaturation Detection and Isolated Fault Sensing
Reflow Profile
Temperature (°C)
TP
260
240
TL
220
200
180
160
140
120
100
80
60
40
20
0
Max. Ramp-up Rate = 3°C/S
Max. Ramp-down Rate = 6°C/S
tP
Tsmax
tL
Preheat Area
Tsmin
ts
120
240
360
Time 25°C to Peak
Time (seconds)
Figure 57. Relow Profile
Profile Freature
Pb-Free Assembly Profile
Temperature Minimum (Tsmin)
150°C
Temperature Maximum (Tsmax)
200°C
Time (tS) from (Tsmin to Tsmax)
60 to 120 seconds
Ramp-up Rate (tL to tP)
3°C/second maximum
Liquidous Temperature (TL)
217°C
Time (tL) Maintained Above (TL)
60–150 seconds
Peak Body Package Temperature
260°C +0°C / –5°C
Time (tP) within 5°C of 260°C
30 seconds
Ramp-Down Rate (TP to TL)
6°C/second maximum
Time 25°C to Peak Temperature
©2010 Fairchild Semiconductor Corporation
FOD8316 Rev. 1.2.1
8 minutes maximum
www.fairchildsemi.com
27
0.20 C A-B
1.27 TYP
2X
10.30
16
A
0.64 TYP
9
D
9
7.31
9.47
11.63
16
3.75
10.30
7.50
(2.16)
0.10 C D
2X
8
1
PIN ONE
INDICATOR
0.33 C
2X 8 TIPS
1.27
0.51 (16X)
0.31
B
0.51 TYP
0.25
1
8
LAND PATTERN
RECOMMENDATION
C A-B D
A
0.10 C
3.0 MAX
2.35±0.10
0.10 C
16X
SEATING PLANE
0.30±0.15
C
NOTES: UNLESS OTHERWISE SPECIFIED
(1.42)
(R0.17)
(R0.17)
GAUGE
PLANE
0.25
0.19
8°
0°
0.25
SEATING
PLANE
1.27
0.40
C
SCALE: 3:1
A) DRAWING REFERS TO JEDEC MS-013,
VARIATION AA.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF
BURRS, MOLD FLASH AND TIE BAR
PROTRUSIONS
D) DRAWING CONFORMS TO ASME
Y14.5M-1994
E) LAND PATTERN STANDARD:
SOIC127P1030X275-16N
F) DRAWING FILE NAME: MKT-M16FREV2
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intended to be an exhaustive list of all such trademarks.
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Sync-Lock™
®*
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Advance Information
Formative / In Design
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
Definition
Datasheet contains the design specifications for product development. Specifications may change
in any manner without notice.
Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild
Semiconductor reserves the right to make changes at any time without notice to improve design.
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make
changes at any time without notice to improve the design.
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The datasheet is for reference information only.
Rev. I77
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