IntelliMAX™ Dual-Input Single-Output Advanced Power
Switch with True Reverse-Current Blocking
Features
Description
DISO Load Sw itches
Input Supply Operating Range: 1.5 V ~ 5.5 V
RON 50 mΩ at V IN=3.3 V Per Channel (Typical)
True Reverse-Current Blocking (TRCB)
Fixed Slew Rate Controlled 130 µs for < 1 µF COUT
ISW: 1.5 A Per Channel (Maximum)
Quick Discharge Feature on FPF1321
Logic CMOS IO Meets JESD76 Standard for GPIO
Interface and Related Pow er Supply Requirements
ESD Protected:
-
Human Body Model: >6 kV
-
Charged Device Model: >1.5 kV
-
IEC 61000-4-2 Air Discharge: >15 kV
-
IEC 61000-4-2 Contact Discharge: >8 kV
Applications
The FPF1320/21 is a Dual- Input Single-Output ( DISO)
load sw itch consisting of tw o sets of slew -rate
controlled, low on-resistance, P-channel MOSFET
sw itches and integrated analog features. The slew -ratecontrolled turn-on character istic prevents inrush current
and the resulting excessive voltage droop on the pow er
rails. The input voltage range operates from 1.5 V to
5.5 V to align w ith the requirements of low -voltage
portable device pow er rails. FPF1320/21 perfor ms
seamless pow er-source transitions betw een tw o input
pow er rails using the SEL pin w ith advanced breakbefore-make operation.
FPF1320/21 has a TRCB function to bloc k unw anted
reverse current from output to input during ON/OFF
states. The sw itch is controlled by logic inputs of the
SEL and EN pins, w hich are capable of interfacing
directly w ith low -voltage control signals (GPIO).
FPF1321 has 65 Ω on-chip load resistor for output quick
discharge w hen EN is LOW.
FPF1320/21 is available in 1.0 mm x 1.5 mm WLCSP,
6-bump, w ith 0.5 mm pitch. FPF1321B is available in
1.0 mm x 1.5 mm WLCSP, 6-bump, 0.5 mm pitch w ith
backside laminate.
Smart phones / Tablet PCs
Portable Devices
Near Field Communication (NFC) Capable
SIM Card Pow er Supply
Ordering Information
Switch Per
Reverse
Output
Rise
Part Number Top Channel Channel (Typ.) Current
Mark
Discharge Time (tR)
at 3.3 VIN
Blocking
FPF1320UCX
QS
DISO
50 mΩ
Yes
NA
130 µs
FPF1321UCX
QT
DISO
50 mΩ
Yes
65 Ω
130 µs
FPF1321BUCX
QT
DISO
© 2011 Semiconductor Components Industries,LLC.
October-2017,Rev 2
50 mΩ
Yes
65 Ω
130 µs
Package
1.0 mm X 1.5 mm
Wafer-Level ChipScale Package
(WLCSP) 6-Bumps,
0.5 mm Pitch
1.0 mm X 1.5 mm
Wafer-Level ChipScale Package
(WLCSP) 6-Bumps,
0.5 mm Pitch w ith
Backside Laminate
Publication Order Number:
FPF1321/D
FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output Advanced Power Switch
FPF1320 / FPF1321
VINA
VIN_A
VOUT
CIN1
COUT
FPF1320/21
VIN_B
VINB
CIN2
GND
SEL
Figure 1.
EN
Typical Application
Block Diagram
TRCB
VOUT
VINA
Output Discharge
(Optinal)
FPF1320/21
Turn-On Slew Rate
Controlled Driver
TRCB
VINB
Turn-On Slew Rate
Controlled Driver
SEL
CONTROL
LOGIC
GND
EN
Figure 2.
Functional Block Diagram (Output Discharge Path for FPF1321 Only)
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2
FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output Advanced Power Switch
Application Diagram
Figure 3.
Pin Configuration in Package View w ith Pin 1 Indicator
EN
VIN A
VIN A
EN
A1
A2
A2
A1
SEL
VOUT
VOUT
SEL
B1
B2
B2
B1
GND
VIN B
C1
C2
VIN B
C2
Top View
GND
C1
Bottom View
Figure 4.
Pin Assignm ents
Pin Description
Pin #
Name
A1
EN
Enable input. Active HIGH. There is an internal pull-dow n resistor at the EN pin.
B1
SEL
Input pow er selection inputs. See Table 1. There are internal pull-dow n resistors at the
SEL pins.
A2
V INA
Supply Input. Input to the pow er sw itch A.
B2
V OUT
Sw itch output
C1
GND
Ground
C2
V INB
Supply Input. Input to pow er sw itch B.
Table 1.
Description
Truth Table
SEL
EN
Switch A
Switch B
VOUT
Status
LOW
HIGH
ON
OFF
V INA
V INA Selected
HIGH
HIGH
OFF
ON
V INB
V INB Selected
X
LOW
OFF
OFF
Floating for FPF1320
GND for FPF1321
Both Sw itches are OFF
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3
FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output Advanced Power Switch
Pin Configuration
Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameters
Min.
Max.
Unit
-0.3
6
V
V IN
V INA, V INB, V SEL, V EN, V OUT to GND
ISW
Maximum Continuous Sw itch Current per Channel
1.5
A
PD
Total Pow er Dissipation at TA=25°C
1.2
W
150
°C
TSTG
Operating and Storage Junction Temperature
-65
(1)
ΘJA
ESD
85
Thermal Resistance, Junction-to-Ambient
2
(1 in. Pad of 2-oz. Copper)
Electrostatic Discharge
Capability
(2)
°C/W
110
Human Body Model, JESD22-A114
6.0
Charged Device Model, JESD22-C101
1.5
Air Discharge (V INA , V INB to GND),
IEC61000-4-2 System Level
15.0
Contact Discharge (V INA , V INB to
GND), IEC61000-4-2 System Level
8.0
kV
Notes:
1. Measured using 2S2P JEDEC std. PCB.
2. Measured using 2S2P JEDEC PCB cold-plate method.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet spec ifications. ON Semiconductor
does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Min.
Max.
Unit
V IN
Input Voltage on V INA, V INB
Parameters
1.5
5.5
V
TA
Ambient Operating Temperature
-40
85
°C
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FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output Advanced Power Switch
Absolute Maximum Ratings
V INA=V INB=1.5 to 5.5 V, TA=-40 to 85°C unless otherw ise noted. Typical values are at V INA=V INB=3.3 V and TA=25°C.
Symbol
Parameters
Condition
Min.
Typ. Max. Unit
1.5
5.5
V
5
µA
μA
Basic Operation
V INA, V INB
Input Voltage
ISD
Shutdow n Current
SEL=HIGH or LOW, EN=GND,
V OUT=GND, V INA=V INB=5.5 V
IQ
Quiescent Current
IOUT=0mA, SEL=HIGH or LOW,
EN=HIGH, V INA=V INB=5.5 V
12
22
V INA=V INB=5.5 V, IOUT=200 mA,
TA=25°C
42
60
V INA=V INB=3.3 V, IOUT=200 mA,
TA=25°C
50
V INA=V INB=1.8 V, IOUT=200 mA,
TA=25°C to 85°C
80
RON
On-Resistance
mΩ
V INA=V INB=1.5 V, IOUT=200 mA,
TA=25°C
V IH
V IL
V DROOP_OUT
ISEL/IEN
170
SEL, EN Input Logic High
Voltage
V INA, V INB=1.5 V – 5.5 V
SEL, EN Input Logic Low
Voltage
V INA , V INB=1.8 V – 5.5 V
0.65
SEL, EN Input Logic Low
Voltage
V INA , V INB=1.5 V – 1.8 V
0.60
1.15
V
Output Voltage Droop w hile
Channel Sw itching from
V INA=3.3 V, V INB=5 V, Sw itching from
Higher Input Voltage Low er V INA V INB, RL=150 Ω, COUT=1 µF
(3)
Input Voltage
100
mV
Input Leakage at SEL and
EN Pin
1.2
μA
RSEL_PD/REN_PD Pull-Dow n Resistance at
SEL or EN Pin
RPD
V
Output Pull-Dow n
Resistance
7
MΩ
SEL=HIGH or LOW, EN=GND,
IFORCE=20 mA, TA=25°C, FPF1321
65
Ω
True Reverse Current Blocking
V T_RCB
RCB Protection Trip Point
V OUT - V INA or V INB
45
mV
V R_RCB
RCB Protection Release
Trip Point
V INA or V INB -V OUT
25
mV
IRCB
V INA or V INB Current During
RCB
V OUT=5.5 V, V INA or V INB=Short to
GND
9
tRCB_ON
RCB Response Time w hen
(3)
Device is ON
V INA or V INB=5 V, V OUTV INA,B=100 mV
5
15
μA
µs
Continued on the following page…
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FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output Advanced Power Switch
Electrical Characteristics
V INA=V INB=1.5 to 5.5 V, TA=-40 to 85°C unless otherw ise noted. Typical values are at V INA=V INB=3.3 V and TA=25°C.
Symbol
Parameters
Condition
Min.
Typ. Max. Unit
Dynam ic Characteristics
(4)
tDON
Turn-On Delay
tR
V OUT Rise Time
tON
tDOFF
(4)
(6)
Turn-On Time
Turn-Off Delay
tF
V OUT Fall Time
Turn-Off Time
tDOFF
tF
tOFF
tTRANR
tSLH
tTRANF
tSHL
(7)
Turn-Off Delay
120
μs
130
μs
250
μs
V INA or V INB=3.3 V, RL=150 Ω,
CL=1 µF, TA=25°C, SEL: HIGH,
EN: HIGH LOW
15
μs
320
μs
335
μs
6
μs
110
μs
116
μs
3
μs
1
μs
45
μs
5
μs
(4)
(4)
tOFF
V INA or V INB=3.3 V, RL=150 Ω,
CL=1 µF, TA=25°C, SEL: HIGH,
EN: LOW HIGH
(4,5)
V INA or V INB =3.3 V, RL=150 Ω,
CL=1 µF, TA=25°C, SEL: HIGH,
EN: HIGH LOW,
Output Discharge Mode, FPF1321
(4,5)
V OUT Fall Time
(5,7)
Turn-Off Time
Transition Time
(4)
LOW HIGH
Sw itch-Over Rising Delay
(4)
Transition Time
(4)
HIGH LOW
Sw itch-Over Falling Delay
(4)
V INA=3.3 V, V INB=5 V,
Sw itching from V INA V INB,
SEL: LOW HIGH, EN: HIGH,
RL=150 Ω, CL=1 µF, TA=25°C
V INA=3.3 V, V INB=5 V,
Sw itching from VINB V INA,
SEL: HIGH LOW, EN: HIGH,
RL=150 Ω, C=1 µF, TA=25°C
Notes:
3. This parameter is guaranteed by design and characterization; not production tested.
4. tDON/tDOFF/tR/tF/tTRANR/tTRANF/tSLH/tSHL are defined in Figure 5.
5. FPF1321 output discharge is enabled during off.
6. tON=tR + tDON.
7. tOFF=tF + tDOFF.
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FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output Advanced Power Switch
Electrical Characteristics (Continued)
5V
VINA
3.3V
VINB
HI
50%
50%
SEL
LO
LO
HI
50%
EN
50%
LO
tR
tDON
90%
tSHL tTRANF
5V
5V
VOUT
90%
3.3V
tDOFF
90%
tF
90%
10%
10%
GND
Shutdown
LO
tSLH tTRANR
10%
VDROOP
Turn-on and VINA
Figure 5.
Switching from VINA
to VINB
Output discharge
of FPF1321
Switching from VINB
to VINA
Dynam ic Behavior Tim ing Diagram
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7
Shutdown
GND
FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output Advanced Power Switch
Timing Diagram
Figure 6.
Figure 8.
Supply Current vs. Tem perature
Shutdow n Current vs. Tem perature
Figure 7.
Figure 9.
Figure 10. RON vs. Tem perature
Supply Current vs. Supply Voltage
Shutdow n Current vs. Supply Voltage
Figure 11. RON vs. Supply Voltage
Continued on the following page…
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FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output Advanced Power Switch
Typical Characteristics
Figure 12. V IL vs. Tem perature
Figure 13. V IL vs. Supply Voltage
Figure 14. V IH vs. Tem perature
Figure 15. V IH vs. Supply Voltage
Figure 16. V IH / V IL vs. Supply Voltage
Figure 17. RSEL_PD and REN_PD vs. Tem perature
Continued on the following page…
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FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output Advanced Power Switch
Typical Characteristics
Figure 18. RSEL_PD and REN_PD vs. Supply Voltage
Figure 19. t DON and t DOFF vs. Tem perature
Figure 20. t R and t F w ith FPF1320 vs. Tem perature
Figure 21. t R and t F w ith FPF1321 vs. Tem perature
Figure 22. Transition Tim e vs. Tem perature
Figure 23. Sw itch Over Tim e vs. Tem perature
Continued on the following page…
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FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output Advanced Power Switch
Typical Characteristics
Figure 24. TRCB Trip and Release vs. Tem perature
Figure 25. IRCB vs. Tem perature
Figure 26. RPD w ith FPF1321 vs. Tem perature
Figure 28. Turn-Off Response w ith FPF1320
(V INA=3.3 V, CIN=1 µF, COUT=1 µF, RL=150 Ω,
SEL=LOW)
Figure 27. Turn-On Response
(V INA=3.3 V, CIN=1 µF, COUT=1 µF, RL=150 Ω,
SEL=LOW)
Figure 29. Turn-Off Response w ith FPF1321
(V INA=3.3 V, CIN=1 µF, COUT=1 µF, RL=150 Ω,
SEL=LOW)
Continued on the following page…
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11
FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output Advanced Power Switch
Typical Characteristics
Figure 30. Pow er Source Transition from 3.3 V to 5 V Figure 31. Pow er Source Transition from 5 V to 3.3 V
(V INA=3.3 V, V INB=5 V, CIN=1 µF, COUT=1 µF,
(V INA=3.3 V, V INB=5 V, CIN=1 µF, COUT=1 µF,
RL=150 Ω)
RL=150 Ω)
Figure 32. TRCB During Off (V INA=V INB=Floating,
V OUT=5V, CIN=1 µF, COUT=1 µF, EN=LOW, No RL)
Figure 33. TRCB During On (V INA=5 V, V OUT=6 V,
CIN=1 µF, COUT=1 µF, EN=HIGH, No RL)
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FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output Advanced Power Switch
Typical Characteristics
The FPF1320 and FPF1321 are dual- input single-output
pow er multiplexer sw itches w ith controlled turn-on and
seamless pow er source transition. The core is a 50 mΩ
P-channel MOSFET and contr oller capable of
functioning over a w ide input operating range of 1.5 V to
5.5 V per channel. The EN and SEL pins are activeHIGH, GPIO/CMOS-compatible input. They control the
state of the sw itch and input pow er source selection,
respectively. TRCB functionality blocks unw anted
reverse current during both ON and OFF states w hen
higher V OUT than V INA or V INB is applied. FPF1321 has a
65 Ω output discharge path during off.
Input Capacitor
To limit the voltage drop on the input supply caused by
transient inrush current w hen the sw itch turns on into a
discharged load capac itor; a capacitor must be placed
betw een the V INA or V INB pins to the GND pin. At least
1 µF ceramic capacitor, CIN, placed c lose to the pins, is
usually sufficient. Higher-value CIN can be used to
reduce more the voltage drop.
Power Source Selection
Input pow er source selection can be controlled by the
SEL pin. When SEL is LOW, output is pow ered from
V INA w hile SEL is HIGH, V INB is pow ering output. The
SEL signal is ignored during device OFF.
Output Voltage Drop during Transition
Output voltage drop usually occurs during input pow er
source transition per iod from low voltage to high
voltage. The drop is highly dependent on output
capacitance and load current.
FPF1320/1 adopts an advanced break-before-make
control, w hich can result in minimized output voltage
drop during the transition time.
Output Capacitor
Capacitor COUT of at least 1 µF is highly recommended
betw een the V OUT and GND pins to achieve minimized
output voltage drop during input pow er source transition.
This capacitor also prevents parasitic board inductance.
Inrush Current
True Reverse-Current Blocking
Inrush current occurs w hen the dev ice is turned on.
Inrush current is dependent on output capac itance and
slew rate control capability, as expressed by:
The true reverse-current blocking feature protects the
input source against current flow from output to input
regardless of w hether the load sw itch is on or off.
I INRUSH = COUT ×
VIN − VINITIAL
+ I LOAD
tR
Board Layout
(1)
w here:
COUT:
Output capacitance;
tR:
Slew rate or rise time at V OUT;
V IN:
Input voltage, V INA or V INB;
For best performance, all traces should be as short as
possible. To be most effective, the input and output
capacitors should be placed close to the device to
minimize the effect that parasitic trace inductance on
nor mal and short-circuit operation. Wide traces or large
copper planes for pow er pins (V INA, V INB, V OUT and
GND) minimize the parasitic electrical effects and the
thermal impedance.
V INITIAL: Initial voltage at COUT, usually GND; and
ILOAD:
Load current.
Higher inrush current causes higher input voltage drop,
depending on the distributed input resistance and input
capacitance. High inrush current can cause problems.
FPF1320/1 has a 130 µs of slew rate capability under
3.3 V IN at 1 µF of COUT and 150 Ω of RL so inrush
current and input voltage drop can be minimized.
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FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output Advanced Power Switch
Operation and Application Description
0.03 C
E
2X
F
A
(Ø0.250)
Cu Pad
(Ø0.350)
SOLDER MASK
OPENING
B
A1
(1.00)
BALL A1
INDEX AREA
D
(0.50)
0.03 C
2X
TOP VIEW
RECOMMENDED LAND PATTERN
(NSMD PAD TYPE)
0.06 C
0.625
0.539
0.05 C
C
0.332±0.018
0.250±0.025
E
SEATING PLANE
D
SIDE VIEWS
NOTES:
A. NO JEDEC REGISTRATION APPLIES.
0.005
Ø0.315 +/- .025
6X
0.50
C
1.00
B
A
0.50
(Y) ±0.018
1 2
F
(X) ±0.018
BOTTOM VIEW
C A B
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCE
PER ASMEY14.5M, 1994.
D. DATUM C IS DEFINED BY THE SPHERICAL
CROWNS OF THE BALLS.
E. PACKAGE NOMINAL HEIGHT IS 582 MICRONS
±43 MICRONS (539-625 MICRONS).
F. FOR DIMENSIONS D, E, X, AND Y SEE
PRODUCT DATASHEET.
G. DRAWING FILNAME: MKT-UC006AFrev2.
Figure 34. 6-Ball, 1.0 x 1.5 m m , Wafer-Level Chip-Scale Package (WLCSP)
Product-Specific Dimensions
Product
D
E
X
Y
FPF1320UCX
1460 µm ±30 µm
960 µm ±30 µm
230 µm
230 µm
FPF1321UCX
1460 µm ±30 µm
960 µm ±30 µm
230 µm
230 µm
FPF1321BUCX
1460 µm ±30 µm
960 µm ±30 µm
230 µm
230 µm
Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change in
any manner without notice. Please note the revision and/or date on the drawing and contact a ON Semiconductor representative to
verify or obtain the most recent revision. Package specifications do not expand the terms of ON Semiconductor’s worldwide terms and
conditions, specifically the warranty therein, which covers ON Semiconductor products.
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14
FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output Advanced Power Switch
Physical Dimensions
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Or der Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
FPF1320 / FPF1321 — IntelliMAX™ Dual-Input Single-Output Advanced Power Switch
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