FPF2260ATMX

28 V Rated OVLO/UVLO Controller with Negative Stress Protection FPF2260ATMX Description FPF2260ATMX is an OVP and UVLO controller with reverse / negative voltage protection. The device controls and drives a pair of external N−MOSFET that can operate over an input voltage range of 2.8 V to 23 V. In that way, with OVP feature implemented, the system can allow huge current as long as the external MOSFET can handle. When the input voltage exceeds the over−voltage threshold or lower than under−voltage threshold, the external FET is turned off immediately to prevent damage to the protected downstream components. When the input voltage is stressed a negative voltage, the external FET will also be turned off and prevent OUT dropping to negative voltage. FPF2260ATMX is available in a small X2QFN12 package and operate over the free−air temperature range of −40°C to +85°C. www.onsemi.com X2QFN12 1.6x1.6, 0.4P CASE 722AG MARKING DIAGRAM Features • Over−voltage Protection Up to ±28V • Programmable Over−voltage Lockout (OVLO) 1 Externally Adjustable via OVLO Pin Default OVLO Level without Additional Components Programmable Under−voltage Lockout (UVLO) ♦ Externally Adjustable via UVLO Pin Active−high Enable Pin (EN) for Device Super−fast OVLO Response Time: Typical 150 ns Negative Voltage Blocking Short Circuit Protection and Auto−restart Selectable Gate Driver Voltage USB OTG Support Mode Open−Drain Output Indicators ♦ OVFLGB for Over Voltage Stress ♦ UVFLAG for Under Voltage Lockout Robust ESD Performance ♦ 2 kV Human Body Model (HBM) ♦ 1 kV Charged Device Model (CDM) 6BKK _XYZ ♦ GT_CON EN 12 11 10 9 1 8 OVFLGB OVLO 2 7 UVFLAG IN Mobile Phones PDAs Notebooks Desktops 4 5 6 OUT GND 3 Typical Applications • • • • UVLO PIN CONNECTIONS GT2 • = Specific Device Code = 2−Digits Lot Run Traceability Code = Pin 1 Identifier = 2−Digit Date Code = Assembly Pant Code GT1 • • • • • • • 6B KK _ XY Z TRCB • ♦ (Top View) ORDERING INFORMATION See detailed ordering and shipping information on page 7 of this data sheet. © Semiconductor Components Industries, LLC, 2020 July, 2020 − Rev. 3 1 Publication Order Number: FPF2260ATMX/D FPF2260ATMX HV Battery Charger NTTFSC02N VBUS Travel Adapter NTTFSC02N 1 mF Legacy USB / USB Type C connector 1 mF GT2 IN GT1 OUT R1 UVLO FPF2260A R2 EN OVFLGB Processor UVFLAG OVLO GT_CON TRCB RPU GND RPU R3 VIO VIO Figure 1. Schematic − Adjustable Option OUT IN GT1 Gate Driver, Charge Pump, Bandgap, Oscillator UVLO GT2 UVLO OVFLGB LOGIC OVLO UVFLAG OVP EN GT_CON TRCB GND Figure 2. Simplified Block Diagram www.onsemi.com 2 FPF2260ATMX PIN FUNCTION DESCRIPTION Pin No. Name 1 GND Ground Description 2 OVLO OVLO Input: Over Voltage Lockout Adjustment Input 3 IN Power Input: External FET Input and Device Supply 4 GT1 Gate 1 Output: 5 GT2 Gate 2 Output: 6 OUT Power Output: External FET Output and Device Supply(More Description) 7 UVFLAG UVLO Flag Output: Open−drain output, turn ON the internal MOS to pull down this pin to indicate no Under−Voltage condition on IN 8 OVFLGB OVP Flag Output: Open−drain output, turn ON the internal MOS to pull down this pin to indicate Over−Voltage condition on IN 9 EN 10 GT_CON 11 UVLO UVLO Input: Under Voltage Lockout Adjustment Input 12 TRCB True RCB Enable Input: 0: no TRCB; 1/floating: Block Reverse Current Entirely with internal 500 kW pull up resistor Enable Input: Active HIGH with internal 500 kW pull down resistor Gate Voltage Control Input: VGS select Pin 0: Vgs = 12 V; 1/floating: Vgs = 6V with internal 500 kW pull up resistor MAXIMUM RATINGS Symbol Value Unit Input Voltage Range (Note 1) −28 to +28 V Output Voltage Range −0.3 to +28 V Standard I/O Range (UVFLAG, OVFLGB, TRCB, GT_CON) −0.3 to +6 V VHVIO HV I/O Range (OVLO, UVLO, EN) −0.3 to +28 V TJ(max) Maximum Junction Temperature 150 °C TSTG Storage Temperature Range −65 to 150 °C VIN VOUT VI/O Parameter ESDHBM ESD Capability, Human Body Model (Note 2) ±2 kV ESDCDM ESD Capability, Charged Device Model (Note 2) ±1 kV Lead Temperature Soldering Reflow (SMD Styles Only), Pb−Free Versions (Note 3) 260 °C TSLD Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe Operating parameters. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114) ESD Charged Device Model tested per AEC−Q100−011 (EIA/JESD22−C101) Latch−up Current Maximum Rating: v150 mA per JEDEC standard: JESD78 3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D THERMAL CHARACTERISTICS Symbol RqJA Rating Thermal Characteristics, X2QFN12 (Note 4) Thermal Resistance, Junction−to−Air (Note 5) Value Unit 139.3 °C/W 4. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe Operating parameters. 5. Values based on 2S2P JEDEC std. PCB. www.onsemi.com 3 FPF2260ATMX RECOMMENDED OPERATING CONDITIONS Symbol Parameter Vin Supply Voltage on VIN (GT_CON floating) Min Max Unit 4.0 22 V Supply Voltage on VIN (GT_CON grounded) VOVLO, UVLO, EN, 16 I/O pins 0 5.5 V Cin IN Capacitor 1 − mF Cout OUT Capacitor 1 − mF −40 85 °C TRCB, GT_CON, OVFLAG, UVFLAG TA Ambient Temperature Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN = 2.9 to 23 V, CIN = 0.1 mF, COUT = 0.1 mF, TA = −40 to 85°C; For typical values VIN = 5.0 V, IIN ≤ 3 A, CIN = 0.1 mF, TA = 25°C, for min/max values TA = −40°C to 85°C; unless otherwise noted. (Note 6) Parameter Symbol Test Condition Min Typ Max Unit VIN = 5 V, VOVLO = 1 V, TRCB = 0, VOUT floating − 160 − mA VIN = 20 V, VOVLO = 1 V, TRCB = 0, VOUT floating − 400 − LEAKAGE AND QUIESCENT CURRENTS IQ Input Quiescent Current on VIN IOFF Device turned off current VIN = 5 V, VEN = 0 V, VOUT = 0 V − 120 − mA IIN_Q Supply Current during Over Voltage VIN = 20 V, VOVLO = 1.8 V, VOUT = 0 V − 180 − mA IOVLO OVLO Input Leakage Current VOVLO = VOVLO_TH −100 − 100 nA OVER VOLTAGE AND UNDER VOLTAGE LOCKOUT VDEF_OVLO Default Over−Voltage Trip Level VIN rising, TA = −40 to 85°C 5.9 6.1 6.3 V VDEF_UVLO Default Under−Voltage Trip Level VIN falling, TA = −40 to 85°C 1.8 2.0 2.2 V VOVLO_TH VOVLO rising from 1.1 V to 1.3 V, the OVLO voltage to switch off power FET 1.15 1.19 1.23 V − 2 − % 1.15 1.17 1.23 V − 2 − % 4 − 22 V OVLO set threshold VHYS_OVLO OVLO threshold hysteresis VUVLO_TH UVLO set threshold VUVLO falling from 1.3 V to 1.1 V, the UVLO voltage to switch off power FET VHYS_UVLO UVLO threshold hysteresis VOV_RNG Adjustable OVLO range VOVLO > 0.5 V TRCB (IN TRCB MODE ONLY, I.E. VTRCB = HIGH/FLOAT) VDROP TRCB trigger level VIN = 5 V, ILOAD = 100 mA − 35 − mV tREL TRCB release time VIN = 5 V − 1 − ms 0.3 − − − 0.15 V V V I/O THRESHOLDS VIH_OVLO VIL_OVLO OVLO Input Threshold Voltage Voltage Increasing, Logic High Voltage Decreasing, Logic Low High Low GATE DRIVER VGS IGS Turn on status gate positive voltage over OUT (Note 8) VIN = VOUT = 5 V, VGT_CON = 0 V − 12 − VIN = VOUT = 5 V, VGT_CON = 1.8 V − 6 − Turn on status gate positive current VTRCB = 0 V, VIN = VOUT = 5 V, VGT_CON = 1.8 V, ILOAD = 10 mA − − 10 mA OVP turn off gate current (Note 9) VIN = 5 V, VGT_CON = 1.8 V, VOVLO from 1.1 V to 1.3 V − − 3 A www.onsemi.com 4 FPF2260ATMX ELECTRICAL CHARACTERISTICS (VIN = 2.9 to 23 V, CIN = 0.1 mF, COUT = 0.1 mF, TA = −40 to 85°C; For typical values VIN = 5.0 V, IIN ≤ 3 A, CIN = 0.1 mF, TA = 25°C, for min/max values TA = −40°C to 85°C; unless otherwise noted. (Note 6) (continued) Symbol Parameter Test Condition Min Typ Max Unit 1.2 − − V − − 0.5 V − − 0.4 V I/O AND LOGIC CONTROL Pins: EN, TRCB, GT_CON VIH I/O Logic High Voltage VIL I/O Logic Low Voltage VOL Output Low Voltage of Open−Drain pins VI/O = 3.3 V, ISINK = 1 mA, Pins: UVFLAG, OVFLGB ILKG Leakage Current of I/O pins VI/O = 3.3 V, Logic de−asserted, Pins: UVFLAG, OVFLGB, GT_CON −0.5 − 0.5 mA tSW_DEB De−bounce Time of Power FET turned on Time from 2.5 V < VIN < VIN_OVLO to VOUT = 0.1 x VIN − 15 − ms tOTG_DEB De−bounce Time of OTG turned on Time from VOUT > 2.8 V to VIN = 0.1 x VOUT − 15 − ms tUV_DEB De−bounce Time of UVFLAG flag Time from VIN > VIN_UVLO to UVFLAG < 0.4 V − 130 − ms tOV_DEB De−bounce Time of OVFLGB flag Time from VIN < VIN_OVLO to OVFLGB > 1.8 V − 1 − ms Switch Turn−On rising Time (Note 9) VIN = 5 V, RL = 100 W, CL = 22 mF, VOUT from 0.1 x VIN to 0.9 x VIN − 2 − ms Switch Turn−Off Time (Note 8, 9) RL = 10 W, CL = 0 μF, time from VIN > VOVLO to VOUT = 0.9 x VIN Internal OVP level External OVP level (Note 10) − − 50 100 − − ns ns TIMING tR tOFF Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TJ = TA = 25°C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 7. Refer to the APPLICATION INFORMATION section. 8. Based on the recommended MOSFET devices. 9. Values based on design and/or characterization 10. Depends on the capacitance on OVLO pin. www.onsemi.com 5 FPF2260ATMX TYPICAL CHARACTERISTICS Figure 3. Quiescent Current over Temperature Figure 4. Quiescent Current over VIN Figure 5. Power−Up Transient (VIN = 5 V, COUT = 0.1 mF) Figure 6. Power−Down Transient (VIN = 5 V, COUT = 0.1 mF) www.onsemi.com 6 FPF2260ATMX FUNCTION DESCRIPTION The external resistor ladder can be decided according to the following equation: General V IN_UVLO + V UVLO_TH FPF2260A is an OVP controller to drive external N−type MOSFETs. The device can protect next stage system which is optimized to lower voltage working condition, especially with ultra−high charging current. The device includes multi−functions including OVP, Advanced TRCB, and Negative Stress protection. [1 ) R1 ń (R2 ) R3)] (eq. 1) where R1, R2 and R3 are the resistors in figure 1. Over Voltage Lockout The power FET will be turned off whenever IN voltage higher than VIN_OVLO. The value of VIN_OVLO can be set by external resistor ladder or just be default value VIN_OVLO. When VOVLO ≤ 0.3 V, VOVLO is decided by default value. When VOVLO > 0.3 V, the power switch will be turned off once VOVLO > VOVLO_TH. The external resistor ladder can be decided according to the following equation: Power MOSFET Driver The FPF2260A integrates charge pump driver to control external N−type MOSFET pair. The drive voltage can be configured by GPIO for different MOSFET. The drive voltage for MOSFET can be configured by GPIO pin GT_CON. VGS could be set to 6 V by pull GT_CON to high or floating. Or, VGS will be set to 12 V by pulling GT_CON to ground. V IN_OVLO + V OVLO_TH [1 ) (R1 ) R2) ń R3] (eq. 2) where R1, R2 and R3 are the resistors in figure 1. Negative Voltage Protection True Reverse Current Blocking and USB OTG FPF2260 support negative voltage protection to help system avoid unexpected negative stress. The gate of first external power FET, GT1, will be pulled down with the voltage on IN when it is negative. This behavior can keep the external FET at off status till −28 V. The FPF2260A support advanced TRCB mode by pulling TRCB pin to high or floating it. In the advanced TRCB mode, no reverse current will be seen from OUT to IN through the external MOSFETs if VOUT – VIN > 30 mV. When advanced TRCB mode is active, OTG operation is not supported. If OTG is needed, TRCB pin needs to be pulled down to ground. APPLICATIONS INFORMATION Input Decoupling (Cin) Enable Control A ceramic or tantalum at least 0.1 mF capacitor is recommended and should be put before and close the connection point of MOSFET and FPF2260A IN. Higher capacitance and lower ESR will improve the overall line and load transient response. The GPIO EN is an active high control pin. When the voltage is pulled low, FPF2260A will disable the external MOSFETs by connecting GT1 to IN and GT2 to OUT. When EN is logic high, FPF2260A will close external MOSFET if there are no over stressed condition. Under Voltage Lockout Output Decoupling (Cout) FPF2260A will turn the FETs off when the voltage on IN is lower than the UVLO threshold VIN_UVLO. Whenever IN voltage ramps up to higher than the threshold, the power FET will be turned on automatically after tDEB de−bounce time if there is no other over stressed condition. Hints for PCB Layout The FPF2260A is a stable component and does not require a minimum Equivalent Series Resistance (ESR) for the output capacitor. The minimum output decoupling value is 0.1 mF and can be augmented to fulfill stringent load transient requirements. The external MOSFET is an important part to FPF2260A. The connection of gate should be as short as possible to avoid parasitic resistance and inductance for better OVP performance. ORDERING INFORMATION Part Number Marking Package Shipping† FPF2260ATMX 6B X2QFN12 5000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 7 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS X2QFN12 1.6x1.6, 0.4P CASE 722AG ISSUE A DOCUMENT NUMBER: DESCRIPTION: 98AON13772G X2QFN12 1.6x1.6, 0.4P DATE 26 SEP 2017 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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