FQL40N50

QFET TM FQL40N50 500V N-Channel MOSFET General Description Features These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switch mode power supply, power factor correction, motor drive and welding machine. • • • • • • 40A, 500V, RDS(on) = 0.11Ω @VGS = 10 V Low gate charge ( typical 155 nC) Low Crss ( typical 95 pF) Fast switching 100% avalanche tested Improved dv/dt capability D ! " ! " " " G! G D S Absolute Maximum Ratings Symbol VDSS ID TO-264 ! FQL Series S TC = 25°C unless otherwise noted Parameter Drain-Source Voltage - Continuous (TC = 25°C) Drain Current - Continuous (TC = 100°C) IDM Drain Current - Pulsed FQL40N50 500 Units V 40 A 25 A (Note 1) 160 A VGSS Gate-Source Voltage ± 30 V EAS Single Pulsed Avalanche Energy (Note 2) 1780 mJ IAR Avalanche Current (Note 1) 40 A EAR Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TC = 25°C) (Note 1) 46 4.5 460 3.7 -55 to +150 mJ V/ns W W/°C °C 300 °C dv/dt PD TJ, TSTG TL (Note 3) - Derate above 25°C Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds Thermal Characteristics Symbol RθJC Parameter Thermal Resistance, Junction-to-Case Typ -- RθCS Thermal Resistance, Case-to-Sink RθJA Thermal Resistance, Junction-to-Ambient ©2001 Fairchild Semiconductor Corporation Max 0.27 Units °C/W 0.1 -- °C/W -- 30 °C/W Rev. A1. May 2001 FQL40N50 May 2001 Symbol TC = 25°C unless otherwise noted Parameter Test Conditions Min Typ Max Units 500 -- -- V -- 0.48 -- V/°C Off Characteristics BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA ∆BVDSS / ∆TJ Breakdown Voltage Temperature Coefficient ID = 250 µA, Referenced to 25°C IDSS IGSSF IGSSR VDS = 500 V, VGS = 0 V -- -- 1 µA VDS = 400 V, TC = 125°C -- -- 10 µA Gate-Body Leakage Current, Forward VGS = 30 V, VDS = 0 V -- -- 100 nA Gate-Body Leakage Current, Reverse VGS = -30 V, VDS = 0 V -- -- -100 nA 3.0 -- 5.0 V -- 0.085 0.11 Ω -- 29 -- S -- 5800 7500 pF -- 880 1150 pF -- 95 120 pF -- 140 290 ns -- 440 890 ns -- 350 700 ns -- 250 500 ns -- 155 200 nC Zero Gate Voltage Drain Current On Characteristics VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA RDS(on) Static Drain-Source On-Resistance VGS = 10 V, ID = 20 A gFS Forward Transconductance VDS = 50 V, ID = 20 A (Note 4) Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance VDS = 25 V, VGS = 0 V, f = 1.0 MHz Switching Characteristics td(on) Turn-On Delay Time tr Turn-On Rise Time td(off) Turn-Off Delay Time tf Turn-Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge VDD = 250 V, ID = 40 A, RG = 25 Ω (Note 4, 5) VDS = 400 V, ID = 40 A, VGS = 10 V (Note 4, 5) -- 37 -- nC -- 78 -- nC Drain-Source Diode Characteristics and Maximum Ratings IS Maximum Continuous Drain-Source Diode Forward Current -- -- 40 A ISM -- -- 160 A VSD Maximum Pulsed Drain-Source Diode Forward Current VGS = 0 V, IS = 40 A Drain-Source Diode Forward Voltage -- -- 1.4 V trr Reverse Recovery Time -- 520 -- ns Qrr Reverse Recovery Charge -- 8.0 -- µC VGS = 0 V, IS = 40 A, dIF / dt = 100 A/µs (Note 4) Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 2.0mH, IAS = 40A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C 3. ISD ≤ 40A, di/dt ≤ 200A/µs, VDD ≤ BVDSS, Starting TJ = 25°C 4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2% 5. Essentially independent of operating temperature ©2001 Fairchild Semiconductor Corporation Rev. A1. May 2001 FQL40N50 Electrical Characteristics FQL40N50 Typical Characteristics VGS 15 V 10 V 8.0 V 7.0 V 6.5 V 6.0 V Bottom : 5.5 V ID , Drain Current [A] ID , Drain Current [A] 2 10 Top : 2 10 1 10 150℃ 1 10 25℃ -55℃ 0 10 ※ Notes : 1. VDS = 50V 2. 250μ s Pulse Test ※ Notes : 1. 250μ s Pulse Test 2. TC = 25℃ 0 -1 10 -1 10 0 10 1 10 2 10 4 6 8 10 VGS , Gate-Source Voltage [V] VDS , Drain-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 0.4 2 0.3 IDR , Reverse Drain Current [A] RDS(on) [ Ω ], Drain-Source On-Resistance 10 VGS = 10V VGS = 20V 0.2 0.1 1 10 0 10 150℃ 25℃ ※ Notes : 1. VGS = 0 V 2. 250μ s Pulse Test ※ Note : TJ = 25℃ -1 0 30 60 90 120 150 180 10 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VSD , Source-Drain Voltage [V] Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature 12000 12 Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd VDS = 100V VDS = 250V 10 Ciss 8000 Coss 6000 4000 ※ Notes : 1. VGS = 0 V 2. f = 1 MHz Crss 2000 VGS, Gate-Source Voltage [V] 10000 Capacitance [pF] 0.2 ID , Drain Current [A] VDS = 400V 8 6 4 2 ※ Note : ID = 40 A 0 0 -1 10 0 10 1 10 VDS, Drain-Source Voltage [V] Figure 5. Capacitance Characteristics ©2001 Fairchild Semiconductor Corporation 0 30 60 90 120 150 180 QG, Total Gate Charge [nC] Figure 6. Gate Charge Characteristics Rev. A1. May 2001 FQL40N50 Typical Characteristics (Continued) 3.0 1.2 RDS(ON) , (Normalized) Drain-Source On-Resistance BV DSS , (Normalized) Drain-Source Breakdown Voltage 2.5 1.1 1.0 ※ Notes : 1. VGS = 0 V 2. ID = 250 μ A 0.9 0.8 -100 -50 0 50 100 2.0 1.5 1.0 ※ Notes : 1. VGS = 10 V 2. ID = 20 A 0.5 150 0.0 -100 200 -50 0 50 100 150 200 o o TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 3 40 10 Operation in This Area is Limited by R DS(on) 2 30 100 µs 1 ms 10 µs ID, Drain Current [A] ID, Drain Current [A] 10 10 ms DC 1 10 0 10 ※ Notes : 20 10 o 1. TC = 25 C o 2. TJ = 150 C 3. Single Pulse -1 10 0 1 10 2 10 0 25 3 10 10 50 ( t) , T h e r m a l R e s p o n s e Figure 9. Maximum Safe Operating Area 100 125 150 Figure 10. Maximum Drain Current vs. Case Temperature D = 0 .5 10 -1 ※ N o te s : 1 . Z θ J C ( t) = 0 .2 7 ℃ /W M a x . 2 . D u ty F a c to r , D = t 1 /t 2 3 . T J M - T C = P D M * Z θ J C ( t) 0 .2 0 .1 0 .0 5 10 PDM 0 .0 2 -2 t1 0 .0 1 t2 s i n g l e p u ls e Z θ JC 75 TC, Case Temperature [℃] VDS, Drain-Source Voltage [V] 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 t 1 , S q u a r e W a v e P u ls e D u r a t io n [ s e c ] Figure 11. Transient Thermal Response Curve ©2001 Fairchild Semiconductor Corporation Rev. A1. May 2001 FQL40N50 Gate Charge Test Circuit & Waveform VGS Same Type as DUT 50KΩ Qg 200nF 12V 10V 300nF VDS VGS Qgs Qgd DUT 3mA Charge Resistive Switching Test Circuit & Waveforms VDS RL VDS 90% VDD VGS RG VGS DUT 10V 10% td(on) tr td(off) t on tf t off Unclamped Inductive Switching Test Circuit & Waveforms BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD L VDS BVDSS IAS ID RG VDD DUT 10V tp ©2001 Fairchild Semiconductor Corporation ID (t) VDS (t) VDD tp Time Rev. A1. May 2001 FQL40N50 Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT + VDS _ I SD L Driver RG VGS VGS ( Driver ) Same Type as DUT VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop ©2001 Fairchild Semiconductor Corporation Rev. A1. May 2001 FQL40N50 Package Dimensions (8.30) (1.00) (2.00) (7.00) 20.00 ±0.20 2.50 ±0.10 4.90 ±0.20 (1.50) (1.50) 2.50 ±0.20 3.00 ±0.20 (1.50) 20.00 ±0.50 (7.00) (2.00) (11.00) 1.50 ±0.20 ) .20 .00 0 ±0 0) 2.0 (R (R1 (0.50) ø3.3 (9.00) (9.00) (8.30) (4.00) 20.00 ±0.20 6.00 ±0.20 TO-264 +0.25 1.00 –0.10 +0.25 ©2001 Fairchild Semiconductor Corporation 0.60 –0.10 2.80 ±0.30 (2.80) 5.45TYP [5.45 ±0.30] (0.15) (1.50) 3.50 ±0.20 5.00 ±0.20 5.45TYP [5.45 ±0.30] Rev. A1. May 2001 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOS™ EnSigna™ FACT™ FACT Quiet Series™ FAST® FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ PowerTrench® QFET™ QS™ QT Optoelectronics™ Quiet Series™ SLIENT SWITCHER® SMART START™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ UHC™ UltraFET® VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. ©2001 Fairchild Semiconductor Corporation Rev. H2