FQT1N60CTF_WS

MOSFET – N-Channel QFET) 600 V, 0.2 A, 11.5  FQT1N60CTF-WS Description www.onsemi.com This N−Channel enhancement mode power MOSFET is produced using ON Semiconductor’s proprietary planar stripe and DMOS technology. This advanced MOSFET technology has been especially tailored to reduce on−state resistance, and to provide superior switching performance and high avalanche energy strength. These devices are suitable for switched mode power supplies, active power factor correction (PFC), and electronic lamp ballasts. D S G Features SOT−223 CASE 318H−01 • 0.2 A, 600 V, RDS(on) = 9.3  (Typ.) @ VGS = 10 V, • • • • ID = 0.1 A Low Gate Charge (Typ. 4.8 nC) Low Crss (Typ. 3.5 pF) 100% Avalanche Tested These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant D G ABSOLUTE MAXIMUM RATINGS (TC = 25°C unless otherwise noted*) Symbol S Parameter Value Unit VDSS Drain to Source Voltage 600 V VGSS Gate to Source Voltage ±30 V Drain Current Continuous (TC = 25°C) Continuous (TC = 100°C) 0.2 0.12 ID A IDM Drain Current − Pulsed (Note 1) 0.8 A EAS Single Pulsed Avalanche Energy (Note 2) 33 mJ IAR Avalanche Current (Note 1) 0.2 A EAR Repetitive Avalanche Energy (Note 1) 0.2 mJ dv/dt Peak Diode Recovery dv/dt (Note 3) 4.5 V/ns 2.1 0.02 W W/°C −55 to +150 °C 300 °C PD TJ, TSTG TL Power Dissipation (TC = 25°C) Derate above 25°C Operating and Storage Temperature Range Maximum Lead Temperature for Soldering Purpose, 1/8″ from Case for 5 Seconds MARKING DIAGRAM Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. $Y&Z&3&K FQT1N60CG G 1 $Y &Z &3 &K FQT1N60C G = ON Semiconductor Logo = Assembly Plant Code = 3−Digit Date Code Format = 2−Digit Lot Run Traceability Code = Specific Device Code = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information on page 6 of this data sheet. 1. Repetitive Rating: Pulse width limited by maximum junction temperature. 2. L = 59 mH, IAS = 1.1 A, VDD = 50 V, RG = 25  Starting TJ = 25°C. 3. ISD ≤ 0.2 A, di/dt ≤ 200 A/s, VDD ≤ BVDSS, Starting TJ = 25°C. © Semiconductor Components Industries, LLC, 2007 April, 2021 − Rev. 5 1 Publication Order Number: FQT1N60CTF−WS/D FQT1N60CTF−WS THERMAL CHARACTERISTICS Symbol RJA Parameter Thermal Resistance, Junction−to−Ambient* Min Max Unit − 60 °C/W *When mounted on the minimum pad size recommended (PCB Mount) ELECTRICAL CHARACTERISTICS (TC = 25°C, unless otherwise noted) Symbol Parameter Test Conditions Min Typ Max Unit OFF CHARACTERISTIC Drain to Source Breakdown Voltage ID = 250 A, VGS = 0 V, TJ = 25°C 600 − − V BVDSS /TJ Breakdown Voltage Temperature Coefficient ID = 250 A, Referenced to 25°C − 0.6 − V/°C IDSS Zero Gate Voltage Drain Current VDS = 600 V, VGS = 0 V − − 25 A VDS = 480 V, TC = 125°C − − 250 VGS = ±30 V, VDS = 0 V − − ±100 nA 2.0 − 4.0 V − 9.3 11.5  − 0.75 − S − 130 170 pF BVDSS IGSS Gate to Body Leakage Current ON CHARACTERISTICS VGS(th) Gate Threshold Voltage VGS = VDS, ID = 250 A RDS(on) Static Drain to Source On−Resistance VGS = 10 V, ID = 0.1 A Forward Transconductance VDS = 40 V, ID = 0.1 A gFS (Note 4) DYNAMIC CHARACTERISTICS VDS = 25 V, VGS = 0 V, f = 1.0 MHz Ciss Input Capacitance Coss Output Capacitance − 19 25 pF Crss Reverse Transfer Capacitance − 3.5 6 pF − 4.8 6.2 nC − 0.7 − nC − 2.7 − nC − 7 24 ns − 21 52 ns Qg Total Gate Charge at 10 V Qgs Gate to Source Gate Charge Qgd Gate to Drain “Miller” Charge VDS = 480 V, ID = 1 A, VGS = 10 V (Note 4 and 5) SWITCHING CHARACTERISTICS td(on) Turn−On Delay Time tr Turn−On Rise Time td(off) Turn−Off Delay Time − 13 36 ns Turn−Off Fall Time − 27 64 ns Maximum Continuous Drain to Source Diode Forward Current − − 0.2 A ISM Maximum Pulsed Drain to Source Diode Forward Current − − 0.8 A VSD Drain to Source Diode Forward Voltage VGS = 0 V, ISD = 0.2 A − − 1.4 V trr Reverse Recovery Time − 190 − ns Qrr Reverse Recovery Charge − 0.53 − C tf VDD = 300 V, ID = 1 A, RG = 25  (Note 4 and 5) DRAIN−SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS VGS = 0 V, ISD = 1 A, dIF/dt = 100 A/s (Note 4) Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Pulse Test: Pulse width ≤ 300 s, Duty Cycle ≤ 2%. 5. Essentially Independent of Operating Temperature Typical Characteristics. www.onsemi.com 2 FQT1N60CTF−WS TYPICAL CHARACTERISTICS 100 Bottom: VGS 15.0 V 10.0 V 8.0 V 7.0 V 6.5 V 6.0 V 5.5 V 5.0 V 4.5 V ID, Drain Current (A) ID, Drain Current (A) Top: 10−1 100 150°C −55°C 25°C Notes: 1. 250 μs Pulse Test 2. TC = 25°C 10−2 10−1 100 Notes: 1. VDS = 40 V 2. 250 μs Pulse Test 10−1 101 2 VDS, Drain to Source Voltage (V) 4 6 8 10 VGS, Gate to Source Voltage (V) Figure 2. Transfer Characteristics Figure 1. On−Region Characteristics IDR, Reverse Drain Current (A) RDS(ON), Drain to Source On−Resistance () 30 25 VGS = 10 V 20 15 VGS = 20 V 10 5 Note: TJ = 25°C 0.5 1.0 1.5 2.0 150°C 2.5 0.4 VGS, Gate to Source Voltage (V) Capacitance (pF) CiSS COSS 100 Notes: 1. VGS = 0 V 2. f = 1 MHz COSS 50 0 100 1.2 1.4 101 VDS = 120 V 10 VDS = 300 V 8 VDS = 480 V 6 4 2 Note: ID = 1 A 0 10−1 1.0 12 CiSS = Cgs + Cgd (Cds = shorted) COSS = Cds + Cgd Crss = Cgd 150 0.8 Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature Figure 3. On−Resistance Variation vs. Drain Current and Gate Voltage 200 0.6 VSD, Source to Drain Voltage (V) ID, Drain Current (A) 250 Notes: 1. VGS = 0 V 2. 250 μs Pulse Test 25°C 10−1 0.2 0 0.0 100 0 1 2 3 4 5 VDS, Drain to Source Voltage (V) QG, Total Gate Charge (nC) Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics www.onsemi.com 3 6 FQT1N60CTF−WS 3.0 1.2 RDS(ON), (Normalized) Drain to Source On−Resistance BVDSS, (Normalized) Drain to Source Breakdown Voltage TYPICAL CHARACTERISTICS (Continued) 1.1 1.0 Notes: 1. VGS = 0 V 2. ID = 250 A 0.9 0.8 −100 −50 0 50 100 150 1.5 1.0 Notes: 1. VGS = 0 V 2. ID = 0.1 A 0.5 0.0 −100 −50 0 50 100 150 TJ, Junction Temperature (5C) TJ, Junction Temperature (5C) Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On−Resistance Variation vs. Temperature 0.18 ID, Drain Current (A) 1 ms 100 s 10 ms 10−1 100 ms 1s DC 10−2 200 0.20 100 Notes: 1. TC = 25°C 2. TJ = 150°C 3. Single Pulse 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 101 102 103 25 50 75 100 125 VDS, Drain to Source Voltage (V) TC, Case Temperature (5C) Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current vs. Case Temperature 102 Z JC (t), Thermal Response ID, Drain Current (A) 2.0 200 Operation in This Area is Limited by RDS(on) 10−3 100 2.5 D = 0.5 Notes: 1. Z JC (t) = 60°C/W Max. 2. Duty Factor, D = t1/t2 3. TJM − TC = PDM ∗ Z JC (t) 0.2 101 0.1 0.05 100 PDM 0.02 t1 0.01 t2 single pulse 10−1 10−5 10−4 10−3 10−2 10−1 100 101 t1, Square Wave Pulse Duration (sec) Figure 11. Transient Thermal Response Curve www.onsemi.com 4 102 103 150 FQT1N60CTF−WS VGS RL Qg 10 V 10V VDS VGS Qgs Qgd DUT 3mA 1 mA Charge Figure 12. Gate Charge Test Circuit & Waveforms VDS RG RL VDS 90% VDD VGS VGS DUT 10 V 10V 10% td(on) tr td(off) t on t off tf Figure 13. Resistive Switching Test Circuit & Waveforms VDS L 1 EAS = −−− LIAS2 2 BVDSS IAS ID RG 10 V V 10V VDD ID (t) VDS (t) VDD DUT tp tp Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms www.onsemi.com 5 Time FQT1N60CTF−WS DUT + VDS _ I SD L Driver RG Same Type as DUT VGS VDD Sdv/dt controlled by RG SI SD controlled by pulse period Gate Pulse Width D = −−−−−−−−−−−−−−− Gate Pulse Period VGS (Driver) 10V IFM , Body Diode Forward Current I SD (DUT) di/dt IRM Body Diode Reverse Current VDS (DUT) Body Diode Recovery dv/dt VDD VSD Body Diode Forward Voltage Drop Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms PACKAGE MARKING AND ORDERING INFORMATION Device Marking Device Package Reel Size Tape Width Quantity FQT1N60C FQT1N60CTF−WS SOT−223 330 mm 12 mm 4000 †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. QFET is a registered trademark of Semiconductor Components Industries, LLC. www.onsemi.com 6 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOT−223 CASE 318H ISSUE B DATE 13 MAY 2020 SCALE 2:1 GENERIC MARKING DIAGRAM* AYW XXXXXG G 1 A = Assembly Location Y = Year W = Work Week XXXXX = Specific Device Code G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98ASH70634A SOT−223 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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