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FSA4480
USB Type-C Analog Audio
Switch with Protection
Function
FSA4480 is a high performance USB Type−C port multimedia
switch which supports analog audio headsets. FSA4480 allows the
sharing of a common USB Type−C port to pass USB2.0 signal, analog
audio, sideband use wires and analog microphone signal. FSA4480
also supports high voltage on SBU port and USB port on USB Type−C
receptacle side.
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Features
• Power Supply: VCC, 2.7 V to 5.5 V
• USB High Speed (480 Mbps) Switch:
WLCSP25
CASE 567UZ
SDD21 −3dB bandwidth: 950 MHz
3 W RON Typical
Audio Switch
♦ Negative Rail Capability: −3 V to +3 V
♦ THD+N = −110 dB; 1 VRMS, f = 20 Hz 20 kHz, 32 W Load
♦ 1 W RON Typical
High Voltage Protection
♦ 20 V DC Tolerance on Connector Side Pins
♦ Over Voltage Protection: VTH = 5 V (Typ)
OMTP and CTIA Pinout Support
Support Audio Sense Path
25−Ball WLCSP Package (2.24 mm x 2.28 mm)
♦
•
•
•
•
•
♦
ORDERING INFORMATION
Part Number
Package
Marking
FSA4480UCX
WLCSP25
(Pb−Free)
6D
Applications
• Mobile Phone, Tablet, Notebook PC, Media Player
CC CC1
LogicCC2
SCL
SDA
GPIO1
GPIO2
AP
GPIO3
INT
VCC
SCL
SDA
ENN
ADDR CC_IN
DET
INT
L
DN
DN
DP
R
DP
GND
DN_L
DP_R
SENSE GSBU2
HPL
HPR
SENSE
MIC
Audio Codec
AUX+
AUX−
DP Controller
GSBU1
MIC
SBU2_H
USB Type−C
Receptacle
SBU2
GND
SSRXp1
SSTXp1
SSRXn1
SSTXn1
VBUS
VBUS
SBU2
CC1
DN
DP
DP
DN
CC2
SBU1
VBUS
VBUS
SSTXn2
SSRXn2
SSTXp2
SSRXp2
GND
GND
SBU1
SBU1_H
GND
AGND
Figure 1. Application Block Diagram
© Semiconductor Components Industries, LLC, 2018
November, 2019 − Rev. 3
1
Publication Order Number:
FSA4480/D
FSA4480
PIN CONFIGURATION
A
SBU 1_H
SBU 2
SBU 1
ENN
VCC
B
SBU 2_H
AGND
AGND
ADD R
GND
MIC
DET
INT
D
GSBU 1
CC_IN
E
GSBU 2
SENSE
C
1
SCL
SDA
2
3
L
R
DN _L
DP_R
DN
DP
4
Figure 2. Pin Assignment (Top Through View)
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2
5
FSA4480
Table 1. PIN DESCRIPTIONS
No.
Pin
Name
Description
1
A5
VCC
Power Supply (2.7 to 5.5 V)
2
B5
GND
Chip ground
3
D5
DP_R
USB/Audio Common Connector
4
D4
DN_L
USB/Audio Common Connector
5
E5
DP
USB Data (Differential +)
6
E4
DN
USB Data (Differential –)
7
C5
R
Audio – Right Channel
8
C4
L
Audio – Left Channel
9
A3
SBU1
Sideband use wire 1
10
A2
SBU2
Sideband use wire 2
11
C1
MIC
12
B2
AGND
Audio signal ground
13
B3
AGND
Audio signal ground
14
E2
SENSE
Audio ground reference output
15
C3
INT
I2C Interrupt output, active low (open drain)
16
D2
CC_IN
Audio accessory attachment detection input
17
D1
GSBU1
Audio sense path 1 to headset jack GND
18
E1
GSBU2
Audio sense path 2 to headset jack GND
19
C2
DET
Push−pull output. When CC_IN > 1.5 V, DET is low and CC_IN < 1.2 V, DET is high
20
D3
SCL
I2C clock
21
E3
SDA
I2C data
22
B1
SBU2_H
Host Side Sideband Use Wire 2
23
A1
SBU1_H
Host Side Sideband Use Wire 1
24
A4
ENN
25
B4
ADDR
Microphone signal
Chip Enable, active low, internal pull−down by 470 kW
I2C slave address pin
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3
FSA4480
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Min.
Max.
Unit
Supply Voltage from VCC
−0.5
6.5
V
VCC_IN
VCC_IN, to GND
−0.5
20
V
VSW_C
VDP_R to GND, VDN_L to GND
−3.5
20
V
VSW_USB
VDP to GND, VDN to GND
−0.5
6.5
V
VSW_Audio
VL to GND, VR to GND
−3.6
6.5
V
VSBU1 to GND, VSBU2 to GND, VGSBU1 to GND, VGSBU1 to GND
−0.5
20
V
VSBU1_H to GND, VSBU2_H to GND
−0.5
6.5
V
SENSE, MIC, DET, INT, to GND
−0.5
6.5
V
−0.5
6.5
V
Symbol
VCC
VV_SBU/GSBU
VVSBU_H
VI/O
VCNTRL
Control Input Voltage
SDA, SCL, ENN, ADDR
ISW_Audio
Switch I/O Current, Audio Path
−250
250
mA
ISW_USB
Switch I/O Current, USB Path
−
100
mA
ISW_MIC
Switch I/O Current, MIC to SBU1 or SBU2
−
50
mA
ISW_SBU
Switch I/O Current, SBUx to SBUx_H
−
50
mA
ISW_SENSE
Switch I/O Current, SENSE to GSBU1 or GSBU2
−
100
mA
ISW_AGND
Switch I/O Current, AGND to SBU1 or SBU2
−
500
mA
−50
−
mA
ESD
IIK
Human Body Model, ANSI/ESDA/JEDEC
JS−001−2012
Connector side and power pins: VCC,
SBU1, SBU2, DP_R, DN_L, GSBU1,
GSBU2, CC_IN
4
−
kV
ESD
Human Body Model, ANSI/ESDA/JEDEC
JS−001−2012
Host side pins: the rest pins
2
−
kV
ESD
Charged Device Model, JEDEC: JESD22−C101
1
−
kV
Absolute Maximum Operating Temperature
−40
85
°C
Storage Temperature
−65
150
°C
TA
TSTG
DC Input Diode Current
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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4
FSA4480
Table 3. RECOMMENDED OPERATING CONDITIONS
Parameter
Min.
Typ.
Max.
Unit
2.7
−
5.5
V
0
−
3.6
V
−3.6
−
3.6
V
VSBU1 to GND, VSBU2 to GND, VMIC to GND
0
−
3.6
V
VGSBU1 to GND, VGSBU2 to GND, VSENSE to GND
0
−
3.6
V
VSBU1 to GND, VSBU2 to GND, VSBU1_H to GND, VSBU2_H to
GND
0
−
3.6
V
VCC_IN, to GND
0
−
5.5
V
Symbol
POWER
VCC
Supply Voltage
USB SWITCH
VSW_USB
VDP to GND, VDN to GND, VDP_R to GND, VDN_L to GND
AUDIO SWITCH
VSW_Audio
VDP_R to GND, VDN_L to GND, VL to GND, VR to GND
MIC SWITCH
VVSBU_MIC
SENSE SWITCH
VVGSBU_SEN
SBU TO SBUX_H SWITCH
VVGSBU
CC_IN PIN
VCC_IN
CONTROL VOLTAGE (ENN/SDA/SCL)
VIH
Input Voltage High
1.3
−
VCC
V
VIL
Input Voltage Low
−
−
0.5
V
−40
25
+85
°C
OPERATING TEMPERATURE
TA
Ambient Operating Temperature
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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5
FSA4480
Table 4. DC ELECTRICAL CHARACTERISTICS
(VCC = 2.7 V to 5.5 V, VCC (Typ.) = 3.3 V, TA = −40°C to 85°C, and TA (Typ.) = 25°C, unless otherwise specified.)
Symbol
ICC
ICCZ
Parameter
Supply Current
Quiescent Current
Condition
Power
Min.
Typ.
Max.
Unit
VCC: 2.7 V to 5.5 V
−
−
65
mA
Audio switches on, MIC switch on
and Audio GND switch on
−
−
60
mA
ENN = L, 04H’b7 = 0
-
−
5
mA
USB switches on, SBUx to
SBUx_H switches on
USB/AUDIO COMMON PINS: DP/R, DN_L
IOZ
Off Leakage Current of DP_R
and DN_L
DN_L, DP_R = −3 V to 3.6 V
VCC: 2.7 V to 5.5 V
−3.0
−
3.0
mA
IOFF
Power−Off Leakage Current of
DP_R and DN_L
DN_L, DP_R = 0 V to 3.6 V
Power off
−3.0
−
3.0
mA
VOV_TRIP
Input OVP Lockout
Rising edge
VCC: 2.7 V to 5.5 V
4.5
5
5.3
V
VOV_HYS
Input OVP Hysteresis
−
0.3
−
V
AUDIO SWITCH
ION
On Leakage Current of Audio
Switch
DN_L, DP_R = −3 V to 3.0 V,
DP, DN, R, L = Float
VCC: 2.7 V to 5.5 V
−2.5
−
2.5
mA
IOFF
Power−Off Leakage Current of L
and R
L, R = 0 V to 3 V;
DP_R, DN_L = Float
Power off
−1.0
−
1.0
mA
Audio Switch On Resistance
ISW = 100 mA, VSW = −3 V to 3 V
VCC: 2.7 V to 5.5 V
−
1.0
2.1
W
Pull Down Resistor on R/L Pin
when Audio Switch is Off
L=R=3V
6
10
14
kW
ION
On Leakage Current of USB
Switch
DN_L, DP_R = 0 V to 3.6 V,
DP, DN, R, L = Float
−3.0
−
3.0
mA
IOZ
Off Leakage Current of DP and
DN
DN, DP = 0 V to 3.6 V
−3.0
−
3.0
mA
IOFF
Power−Off Leakage Current of
DP and DN
DN, DP = 0 V to 3.6 V
Power off
−3.0
−
3.0
mA
USB Switch On Resistance
ISW = 8 mA, VSW = 0.4 V
VCC: 2.7 V to 5.5 V
−
3.0
5.2
W
RON_AUDIO
RSHUNT
USB SWITCH
RON_USB
VCC: 2.7 V to 5.5 V
SENSE SWITCH
ION
Sense Path Leakage Current
GSBUx = 0 V to 1 V, SENSE is
floating
VCC: 2.7 V to 5.5 V
−2.0
−
2.0
mA
RON_SENSE
SENSE Switch On Resistance
ISW = 100 mA, VSW = 1 V
VCC: 2.7 V to 5.5 V
0.20
0.30
0.40
W
IOZ
Off Leakage Current of SENSE
Sense = 0 V to 1.0 V
−2.0
−
2.0
mA
Off Leakage Current of GSBUx
GSBUx = 0 V to 1.0 V
−2.0
−
2.0
mA
GSBUx = 1 V to 3.6 V
−3.0
−
3.0
−2.0
−
2.0
−3.0
−
3.0
IOFF
Power−Off Leakage Current of
SENSE
Sense = 0 V to 1.0 V
Power−Off Leakage Current of
GSBUx
GSBUx = 0 V to 3.6 V
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6
Power off
mA
FSA4480
Table 4. DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.7 V to 5.5 V, VCC (Typ.) = 3.3 V, TA = −40°C to 85°C, and TA (Typ.) = 25°C, unless otherwise specified.)
Symbol
Parameter
Condition
Power
Min.
Typ.
Max.
Unit
VCC: 2.7 V to 5.5 V
4.5
5
5.3
V
−
0.3
−
V
SENSE SWITCH
VOV_TRIP
Input OVP Lockout on GSBUx
VOV_HYS
Input OVP Hysteresis of GSBUx
Rising edge
SBUX PINS
IOZ
Off Leakage Current of SBUx
SBUx = 0 V to 3.6 V
VCC: 2.7 V to 5.5 V
−3.0
−
3.0
mA
IOFF
Power−Off Leakage Current
Port SBUx
SBUx = 0 V to 3.6 V
Power off
−3.0
−
3.0
mA
VOV_TRIP
Input OVP Lockout
Rising edge
VCC: 2.7 V to 5.5 V
4.5
5
5.3
V
VOV_HYS
Input OVP Hysteresis
−
0.3
−
V
−3.0
−
3.0
mA
−1.0
−
1.0
mA
MIC SWITCH
ION
On Leakage Current of MIC
Switch
SBUx = 0 V to 3.6 V,
MIC is floating
IOZ
Off Leakage Current of MIC
MIC = 0 V to 3.6 V
IOFF
Power Off Leakage Current of
MIC
MIC = 0 V to 3.6 V
Power off
−1.0
−
1.0
mA
MIC Switch On Resistance
Isw = 30 mA, VSW = 3.6 V
VCC: 2.7 V to 5.5 V
1.7
3.0
3.9
W
VCC: 2.7 V to 5.5 V
−3.0
−
3.0
mA
−1
−
1
mA
RON_MIC
VCC: 2.7 V to 5.5 V
SBUX_H SWITCH
ION
On Leakage Current of SBUx_H
Switch
SBUx = 0 V to 3.6 V, SBUx_H is
floating
IOZ
Off Leakage of SBUx_H
SBUx_H =0 V to 3.6 V
IOFF
Power Off Leakage Current of
SBUx_H
SBUx_H = 0 V to 3.6 V
Power off
−1.0
−
1.0
mA
SBUx_H Switch On Resistance
Isw = 30 mA, VSW = 0 V to 3.6 V
VCC: 2.7 V to 5.5 V
1.5
3.0
3.5
W
VCC: 2.7 V to 5.5 V
30
50
90
mW
VCC: 2.7 V to 5.5 V
−
1.2
−
V
−
1.5
−
V
−
−
1.0
mA
1.5
1.8
2
V
−
−
0.4
V
RON_SBU
AUDIO GROUND SWITCH: PIN: AGND TO SBUX
RON_AGND
AGND Switch On Resistance
ISOURCE = 100 mA on SBUx
CC_IN PIN
VTH_L
Input Low Threshold
VTH_H
Input High Threshold
IIN
Input Leakage of CC_IN
CC_IN = 0 V to 5.5 V
INT, DET PINS
VOH
Output High for DET
Io = −2 mA
VOL
Output Low for DET and INT
Io = 2 mA
VCC: 2.7 V to 5.5 V
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7
FSA4480
Table 4. DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.7 V to 5.5 V, VCC (Typ.) = 3.3 V, TA = −40°C to 85°C, and TA (Typ.) = 25°C, unless otherwise specified.)
Symbol
Parameter
Condition
Power
Min.
Typ.
Max.
Unit
VCC: 2.7 V to 5.5 V
1.3
−
−
V
−
−
0.45
V
−1
−
1
mA
1.3
−
−
V
ADDR PIN
VIH
Input voltage High
VIL
Input voltage Low
IIN
Control Input Leakage
ADDR = 0 V to VCC
ENN PIN
VIH
Input Voltage High
VIL
Input Voltage Low
−
−
0.45
V
RPD
Internal Pull Down Resistor
−
470
−
kW
−
−
0.4
V
1.2
−
−
V
VCC: 2.7 V to 5.5 V
SDS, SCL PINS
VILI2C
Low−Level Input Voltage
VIHI2C
High−Level Input Voltage
II2C
VCC: 2.7 V to 5.5 V
Input Current of SDA and SCL
Pins
SCL/SDA = 0 V to 3.6 V
−2
−
2
mA
VOLSDA
Low−Level Output Voltage
IOL = 2 mA
−
−
0.3
V
IOLSDA
Low−Level Output Current
VOLSDA = 0.2 V
10
−
−
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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8
FSA4480
Table 5. AC ELECTRICAL CHARACTERISTICS
(VCC = 2.7 V to 5.5 V, VCC (Typ.) = 3.3 V, TA = −40°C to 85°C, and TA (Typ.) = 25°C, unless otherwise specified.)
Symbol
Parameter
Condition
Power
Min.
Typ.
Max.
Unit
VCC = 3.3 V
−
65
−
ms
AUDIO SWITCH
tdelay
Audio Switch Turn On Delay Time
DP_R = DN_L = 1 V,
RL = 32 W
trise
Audio Switch Turn On Rising Time
(Note 1)
DP_R = DN_L = 1 V,
RL = 32 W
−
240
−
ms
tOFF
Audio Switch Turn Off Time
DP_R = DN_L = 1 V,
RL = 32 W
−
15
−
ms
Cross Talk (Adjacent)
f = 1 kHz, RL = 50 W,
VSW = 1 VRMS
−
−100
−
dB
BW
−3 dB Bandwidth
RL = 50 W
−
600
−
MHz
OIRR
Off Isolation
F = 1 kHz, RL = 50 W,
CL = 0 pF, VSW = 1 VRMS
−
−100
−
dB
Total Harmonic Distortion + Noise
Performance with A−weighting Filter
RL = 600 W, f = 20 Hz~20 kHz,
VSW = 2 VRMS
−
−110
−
dB
RL = 32 W, f = 20 Hz~20 kHz,
VSW = 1 VRMS
−
−110
−
dB
RL = 16 W, f = 20 Hz~20 kHz,
VSW = 0.5 VRMS
−
−108
−
dB
−
60
−
ms
XTALK
THD+N
USB SWITCH
VCC = 3.3 V
tON
USB Switch Turn−on Time
DP_R = DN_L = 1.5 V,
RL = 50 W
tOFF
USB Switch Turn −off Time
DP_R = DN_L = 1.5 V,
RL = 50 W
−
15
−
ms
BW
−3 dB Bandwidth
RL = 50 W
−
850
−
MHz
SDD21 −3 dB Bandwidth
−
950
−
OIRR
Off Isolation between DP, DN and Common Node Pins
f = 1 kHz, RL = 50 W, CL = 0 pF,
VSW = 1 VRMS
−
−100
−
dB
tOVP
DP_R and DN_L pins OVP Response
Time
Vsw = 3.5 V to 5.5 V
−
1
1.5
ms
−
100
−
ms
−
250
−
−
100
−
−
1500
−
MIC/AUDIO GROUND SWITCH
tdelay_MIC
MIC Switch Turn On Delay Time
trise_MIC
MIC Switch Turn On Rising Time
(Note 1)
tdelay_AGND
AGND Switch Turn On Time
SBUx = 1 V, RL = 50 W
SBUx pulled up to 0.5 V by
16 W, AGND connect to GND
VCC = 3.3 V
VCC = 3.3 V
trise_AGND
AGND Switch Turn On Rising Time
(Note 1)
tOFF_MIC
MIC Switch Turn Off Time
SBUx = 2.5 V, RL = 50 W
−
15
−
AGND Switch Turn Off Time
SBUx: Isource = 10 mA,
clamp to 2.5 V
−
15
−
MIC Switch Bandwidth
RL = 50 W
−
50
−
tOFF_Audio GND
BW
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9
ms
MHz
FSA4480
Table 5. AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.7 V to 5.5 V, VCC (Typ.) = 3.3 V, TA = −40°C to 85°C, and TA (Typ.) = 25°C, unless otherwise specified.)
Symbol
Parameter
Condition
Power
Min.
Typ.
Max.
Unit
VCC = 3.3 V
−
35
−
ms
−
15
−
SBUX_H SWITCH
tON
SBUx_H Switch Turn On Time
tOFF
SBUx_H Switch Turn Off Time
BW
Bandwidth
RL = 50 W
−
50
tOVP
SBUx Pins OVP Response Time
Vsw = 3.5 V to 5.5 V
−
0.5
1
ms
tdelay
Sense Switch Turn On Delay Time
GSBUx = 1 V, RL = 50 W
−
65
−
ms
trise
Sense Switch Turn On Rising Time
(Note 1)
−
260
−
ms
tOFF
Sense Switch Turn Off Time
−
15
−
ms
tOVP
GSBUx Pins OVP Response Time
VSW: 3.5 V to 5.5 V
−
0.7
1.5
ms
BW
Bandwidth
RL = 50 W
−
150
−
MHz
DET Response Delay
Transition from 0 to 1.8 V
−
1
−
ms
−
5
−
SBUx = 2.5 V, RL = 50 W
MHz
SENSE SWITCH
VCC = 3.3 V
DET DELAY
tDELAY_DET
Transition from 1.8 to 0 V
1. Turn on timing can be controlled by
I2C
register.
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10
VCC = 3.3 V
FSA4480
Table 6. I2C SPECIFICATION
(VCC = 2.7 V to 5.5, VCC (Typ.) = 3.3 V ,TA = −40°C to 85°C. TA (Typ.) = 25°C, unless otherwise specified)
Fast Mode
Parameter
Symbol
fSCL
tHD; STA
tLOW
tHIGH
I2C_SCL Clock Frequency
Hold Time (Repeated) START Condition
Low Period of
I2C_SCL
High Period of
I2C_SCL
ms
Clock
0.6
ms
tSU; DAT
Data Set−up Time (Note 3)
tf
tSU; STO
Fall Time of
kHz
1.3
Data Hold Time (Note 2)
I2C_SDA
400
Clock
Set−up Time for Repeated START Condition
Rise Time of
Unit
ms
tSU; STA
I2C_SDA
Max.
0.6
tHD; DAT
tr
Min.
0
and
and
0.6
ms
0.9
100
I2C_SCL
I2C_SCL
Signals (Note 3)
Signals (Note 3)
ms
ns
20 + 0.1Cb
300
ns
20 + 0.1Cb
300
ns
Set−up Time for STOP Condition
0.6
tBUF
Bus−Free Time between STOP and START Conditions
1.3
tSP
Pulse Width of Spikes that Must Be Suppressed by the Input Filter
0
ms
ms
50
ns
2. Guaranteed by design, not production tested.
3. A fast−mode I2C−bus device can be used in a standard−mode I2C−bus system, but the requirement tSU;DAT ≥ ±250 ns must be met. This
is automatically the case if the device does not stretch the LOW period of the I2C_SCL signal. If such a device does stretch the LOW period
of the I2C_SCL signal, it must output the next data bit to the I2C_SDA line tr_max + tSU;DAT = 1000 + 250 = 1250 ns (according to the
standard−mode I2C bus specification) before the I2C_SCL line is released.
Figure 3. Definition of Timing for Full−Speed Mode Devices on the I2C Bus
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11
FSA4480
Table 7. CAPACITANCE
(VCC= 2.7 V to 5.5 V, VCC (Typ.) = 3.3 V, TA = −40°C to 85°C, and TA (Typ.) = 25°C)
TA =− 40°C to +85°C
Symbol
Parameter
Condition
(6)
CON_USB/Audio
On Capacitance
(Common Port)
COFF_ USB/Audio
Off Capacitance(6)
(Common Port)
COFF_USB
Power
Min.
VCC = 3.3 V
f = 1 MHz, 100 mVPK−PK, 100 mV DC
bias
Typ.
Max.
Unit
9
pF
f = 1 MHz, 100 mVPK−PK, 100 mV DC
bias
7.5
pF
Off Capacitance
(Non−Common Ports) (6)
f = 1 MHz, 100 mVPK−PK, 100 mV DC
bias
3
pF
CON_SENSE_SW
On Capacitance −
(Common Ports) (6)
f = 1 MHz, 100 mVPK−PK, 100 mV
DC bias
55
pF
COFF_SENSE_SW
Off Capacitance −
(Common Ports) (6)
f = 1 MHz, 100 mVPK−PK, 100 mV
DC bias
88
pF
CON_MIC_SW
On Capacitance −
(Common Ports) (6)
f = 1 MHz, 100 mVPK−PK, 100 mV
DC bias
170
pF
COFF_MIC_SW
Off Capacitance −
(Common Ports) (6)
f = 1 MHz, 100 mVPK−PK, 100 mV
DC bias
10
pF
CON_AGND_SW
On Capacitance (6)
(Common Port)
f = 1 MHz, 100 mVPK−PK, 100 mV
DC bias
125
pF
CON_SBUx_H_SW
On Capacitance (6)
(Common Port)
f = 1 MHz, 100 mVPK−PK, 100 mV
DC bias
160
pF
CCNTRL
Control Input Pin
Capacitance (6)
f = 1 MHz,
100 mVPP, 100 mV
DC bias
3
pF
ENN
Table 8. REGISTER MAPS
ADDR
Register Name
Type
Reset
Value
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
00H
Device ID
R
0x09
0
0
0
0
1
0
0
1
01H
OVP
Interrupt Mask
R/W
0x00
Reserved
Mask
OVP
interrupt
Mask
OVP
Mask
OVP
Mask
OVP
Mask
OVP
Mask
OVP
Mask
OVP
/DP_R
/DN_L
/SBU1
/SBU2
/GSBU1
/GSBU2
02H
OVP interrupt
flag
R/C
0x00
Reserved
DP_R
DN_L
SBU1
SBU2
GSBU
GSBU2
03H
OVP status
R
0x00
Reserved
OVP/
OVP/
OVP/SB
U2
OVP/
DN_L
OVP/SB
U1
OVP/
DP_R
GSBU1
GSBU2
04H
Switch settings
Enable
R/W
0x98
Device
control
SBU1_H
to SBUx
SBU2_H
to SBUx
DN_L to
DN or L
DP_R to
DP or R
Sense to
GSBUx
MIC to
SBUx
Audio
Ground
to SBUx
05H
Switch select
R/W
0x18
Reserved
SBU1_H
to SBUx
SBU2_H
to SBUx
DN_L to
DN or L
DP_R to
DP or R
Sense to
GSBUx
MIC to
SBUx
Audio
Ground
to SBUx
06H
Switch Status0
R
0x00
Reserved
Reserved
Sense Switch Status
DP_R Switch Status
07H
Switch Status1
R
0x00
08H
Audio Switch Left
Channel turn on
Control
R/W
0x01
Audio switch left channel slow control [7:0]
SBU2 Switch Status
09H
Audio Switch
Right Channel
turn on Control
R/W
0x01
Audio switch right channel slow control [7:0]
0AH
MIC switch turn
on control
R/W
0x01
MIC switch right channel slow control [7:0]
0BH
Sense switch
turn on control
R/W
0x01
Sense switch right channel slow control [7:0]
0CH
Audio Ground
Switch turn on
Control
R/W
0x01
Audio ground switch right channel slow control [7:0]
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12
DN_L Switch Status
SBU1 Switch Status
FSA4480
Table 8. REGISTER MAPS
ADDR
Register Name
Type
Reset
Value
0DH
Timing Delay
between R
switch enable
and L switch
enable
R/W
0x00
Timing Delay between R switch enable and L switch enable control [7:0]
0EH
Timing Delay
between MIC
switch enable
and L switch
enable
R/W
0x00
Timing Delay between MIC switch enable and L switch enable control [7:0]
0FH
Timing Delay
between Sense
switch enable
and L switch
enable
R/W
0x00
Timing Delay between Sense switch enable and L switch enable control [7:0]
10H
Timing Delay
between Audio
ground switch
enable and L
switch enable
R/W
0x00
Timing Delay between Audio ground switch enable and L switch enable control [7:0]
11H
Audio accessory
status
R
0x02
12H
Function enable
R/W
0x08
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
Reserved
Reserved
DET I/O
Control
GIPO
RES
control
detection
range
setting
SLOW
TURN−O
N
CONTR
OLL
MIC auto
control
13H
RES detection
pin setting
R/W
0x00
Reserved
14H
RES detection
value
R
0xFF
R detection value [7:0]
15H
RES detection
interrupt
R/W
0x16
R detection Interrupt resistance threshold [7:0]
16H
RES detection
interval
R/W
0X00
17H
Audio jack Status
RO
0x01
18H
Detection
interrupt
R/C
0x00
Detection
interrupt Mask
R/W
BIT0
CC_IN
DET
RES
Audio
jack
detection
: auto
clear
detection
: auto
clear
Detection pin select [2:0]
threshold
19H
Reserved
Reserved
Detection interval [1:0]
4pole,SB
U2 MIC
Reserved
0x00
Reserved
1AH
Audio detection
RGE1
RO
0xFF
audio detection value REG1 [7:0]
1BH
Audio detection
RGE2
RO
0xFF
audio detection value REG2 [7:0]
1CH
MIC Threshold
DATA0
R/W
0x20
MIC Threshold value DATA0 [7:0]
1DH
MIC Threshold
DATA1
R/W
0xFF
MIC Threshold value DATA1 [7:0]
1EH
I2C Reset
W/C
0x00
1FH
Current Source
Setting
R/W
0x07
4pole,SB
U1 MIC
3pole
No audio
Audio
detection
done
RES
detection
occurred
detection
done
Audio
detection
done
mask
RES
detection
occurred
mask
Reserved
RES
RES
detection
done
mask
I2C reset
Reserved
Current Source setting [3:0]
Table 9. I2C SLAVE ADDRESS
ADDR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADDR = L
1
0
0
0
0
1
0
R/W
ADDR = H
1
0
0
0
0
1
1
R/W
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13
FSA4480
DEVICE ID
Address: 00h
Reset Value: 8’b 0000_1001
Type: Read
Bits
Name
Size
Description
7:6
Vendor ID
2
Vendor ID
5:3
Version ID
3
Device Version ID
2:0
Revision ID
3
Revision History ID
Description
OVP INTERRUPT MASK
Address: 01h
Reset Value: 8’b 0000_0000
Type: Read/Write
Bits
Name
Size
7
Reserved
1
Do Not Use
6
OVP Interrupt mask control
1
OVP Interrupt function Enable/Disable
0: Controlled by [5:0] bit
1: Mask all connector side pins OVP interrupt
5
DP_R OVP Interrupt mask control
1
0: Do not mask OVP interrupt
1: Mask OVP interrupt
4
DN_L OVP Interrupt mask control
1
0: Do not mask OVP interrupt
1: Mask OVP interrupt
3
SBU1 OVP Interrupt mask control
1
0: Do not mask OVP interrupt
1: Mask OVP interrupt
2
SBU2 OVP Interrupt mask control
1
0: Do not mask OVP interrupt
1: Mask OVP interrupt
1
GSBU1 OVP Interrupt mask control
1
0: Do not mask OVP interrupt
1: Mask OVP interrupt
0
GSBU2 OVP Interrupt mask control
1
0: Do not mask OVP interrupt
1: Mask OVP interrupt
OVP INTERRUPT FLAG
Address: 02h
Reset Value: 8’b 0000_0000
Type: Read Clear
Bits
Name
Size
[7:6]
Reserved
2
Do Not Use
5
DP_R OVP
1
0: OVP event has not occurred
1: OVP event has occurred
4
DN_L OVP
1
0: OVP event has not occurred
1: OVP event has occurred
3
SBU1 OVP
1
0: OVP event has not occurred
1: OVP event has occurred
2
SBU2 OVP
1
0: OVP event has not occurred
1: OVP event has occurred
1
GSBU1 OVP
1
0: OVP event has not occurred
1: OVP event has occurred
0
GSBU2 OVP
1
0: OVP event has not occurred
1: OVP event has occurred
Description
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14
FSA4480
OVP STATUS
Address: 03h
Reset Value: 8’b 0000_0000
Type: Read
Bits
Name
Size
[7:6]
Reserved
2
Do Not Use
5
OVP on DP_R PIN
1
0: OVP event has not occurred
1: OVP event has occurred
4
OVP on DN_L PIN
1
0: OVP event has not occurred
1: OVP event has occurred
3
OVP on SBU1 PIN
1
0: OVP event has not occurred
1: OVP event has occurred
2
OVP on SBU2 PIN
1
0: OVP event has not occurred
1: OVP event has occurred
1
OVP on GSBU1 PIN
1
0: OVP event has not occurred
1: OVP event has occurred
0
OVP on GSBU2 PIN
1
0: OVP event has not occurred
1: OVP event has occurred
Description
SWITCHING SETTING ENABLE
Address: 04h
Reset Value: 8’b 1001_1000
Type: Read/Write
Bits
Name
Size
7
Device Enable
1
0: Device Disable; L, R pull down by 10 k and other switch
nodes will be high−Z for positive input.
1: Device Enable.
Device Enable = 1 Device enable = 0
ENN = 1 Device Disable
Device Disable
ENN = 0 Device Enable
Device Disable
6
SBU1_H to SBUx switches
1
0: Switch Disable; SBU1_H will be high−Z for positive input
1: Switch Enable
5
SBU2_H to SBUx switches
1
0: Switch Disable; SBU2_H will be high−Z for positive input
1: Switch Enable
4
DN_L to DN or L switches
1
0: Switch Disable; DN_L,DN will be high−Z for positive input. L
pull down by 10 kohm
1: Switch Enable
3
DP_R to DP or R switches
1
0: Switch Disable; DP_R,DP will be high−Z for positive input.
R pull down by 10 kohm
1: Switch Enable
2
Sense to GSBUx switches
1
0: Switch Disable; Sense,GSBU1 and GSBU2 will be high−Z for
positive input
1: Switch Enable
1
MIC to SBUx switches
1
0: Switch Disable: MIC will be high−Z for positive input.
1: Switch Enable
0
AGND to SBUx switches
1
0: Switch Disable: AGND will be high−Z for positive input.
1: Switch Enable
Description
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15
FSA4480
SWITCH SELECT
Address: 05h
Reset Value: 8’b 0001_1000
Type: Read/Write
Bits
Name
Size
7
Reserved
1
Do Not Use
6
SBU1_H switches
1
0: SBU1_H to SBU1 switch ON
1: SBU1_H to SBU2 switch ON
5
SBU2_H switches
1
0: SBU2_H to SBU2 switch ON
1: SBU2_H to SBU1 switch ON
4
DN_L to DN or L switches
1
0: DN_L to L switch ON
1: DN_L to DN switch ON
3
DP_R to DP or R switches
1
0: DP_R to R switch ON
1: DP_R to DP switch ON
2
Sense to GSBUx switches
1
0: Sense to GSBU1 switch ON
1: Sense to GSBU2 switch ON
1
MIC to SBUx switches
1
0: MIC to SBU2 switch ON
1: MIC to SBU1 switch ON
0
AGND to SBUx switches
1
0: AGND to SBU1 switch ON
1: AGND to SBU2 switch ON
Description
SWITCH STATUS0
Address: 06h
Reset Value: 8’b 0000_0000
Type: Read Only
Bits
Name
Size
[7:6]
Reserved
2
Do not use
[5:2]
Sense Switch Status
2
00: Sense switch is Open/Not Connected
01: Sense connected to GSBU1
10: Sense connected to GSBU2
11: Not Valid
[3:2]
DP_RSwitch Status
2
00: DP_R Switch Open/Not Connected
01: DP_Rconnected to DP
10: DP_Rconnected to R
11: Not Valid
[1:0]
DN_L switch Status
2
00: DN_L Switch Open/Not Connected
01: DN_L connected to DN
10: DN_L connected to L
11: Not Valid
Description
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16
FSA4480
SWITCH STATUS1
Address: 07h
Reset Value: 8’b 0000_0000
Type: Read Only
Bits
Name
Size
[7:6]
Reserved
2
Do not use
[5:3]
SBU2 Switch Status
3
000: SBU2 switch is Open/Not Connected
001: SBU2 connected to MIC
010: SBU2 connected to AGND
011: SBU2 connected to SBU1_H
100: SBU2 connected to SBU2_H
101: SBU2 connected both SBU1_H and SBU2_H
110…111: Do not use
[2:0]
SBU1 Switch Status
3
000: SBU1 switch is Open/Not Connected
001: SBU1 connected to MIC
010: SBU1 connected to AGND
011: SBU1 connected to SBU1_H
100: SBU1 connected to SBU2_H
101: SBU1 connected both SBU1_H and SBU2_H
110…111: Do not use
Description
AUDIO SWITCH LEFT CHANNEL SLOW TURN−ON
Address: 08h
Reset Value: 8’b 0000_0001
Type: Read/Write
Bits
Name
Size
[7:0]
Switch turn on rising time setting
8
Description
11111111: 25600 mS
…
00000001: 200 mS
00000000: 100 mS
AUDIO SWITCH RIGHT CHANNEL SLOW TURN−ON
Address: 09h
Reset Value: 8’b 0000_0001
Type: Read/Write
Bits
Name
Size
[7:0]
Switch turn on rising time setting
8
Description
11111111: 25600 mS
…
00000001: 200 mS
00000000: 100 mS
MIC SWITCH SLOW TURN−ON
Address: 0Ah
Reset Value: 8’b 0000_0001
Type: Read/Write
Bits
Name
Size
[7:0]
Switch turn on rising time setting
8
Description
11111111: 25700 mS
…
00000010: 350 mS
00000001: 250 mS
00000000: Not Valid
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17
FSA4480
SENSE SWITCH SLOW TURN−ON
Address: 0Bh
Reset Value: 8’b 0000_0001
Type: Read/Write
Bits
Name
Size
[7:0]
Switch turn on rising time setting
8
Description
11111111: 25600 mS
…
00000001: 200 mS
00000000: 100 mS
AUDIO GROUND SWITCH SLOW TURN−ON
Address: 0Ch
Reset Value: 8’b 0000_0001
Type: Read/Write
Bits
Name
Size
[7:0]
Switch turn on rising time setting
8
Description
11111111: 179000 mS
…
00000001: 1400 mS
00000000: 700 mS
TIMING DELAY BETWEEN R SWITCH ENABLE AND L SWITCH ENABLE
Address: 0Dh
Reset Value: 8’b 0000_0000
Type: Read/Write
Bits
Name
Size
[7:0]
Delay timing setting
8
Description
11111111: 25500 mS
11111110: 25400 mS
…
00000001: 100 mS
00000000: 0 mS
TIMING DELAY BETWEEN MIC SWITCH ENABLE AND L SWITCH ENABLE
Address: 0Eh
Reset Value: 8’b 0000_0000
Type: Read/Write
Bits
Name
Size
[7:0]
Delay timing setting
8
Description
11111111: 25500 mS
11111110: 25400 mS
…
00000001: 100 mS
00000000: 0 mS
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18
FSA4480
TIMING DELAY BETWEEN SENSE SWITCH ENABLE AND L SWITCH ENABLE
Address: 0Fh
Reset Value: 8’b 0000_0000
Type: Read/Write
Bits
Name
Size
[7:0]
Delay timing setting
8
Description
11111111: 25500 mS
11111110: 25400 mS
…
00000001: 100 mS
00000000: 0 mS
TIMING DELAY BETWEEN AUDIO GROUND SWITCH ENABLE AND L SWITCH ENABLE
Address: 10h
Reset Value: 8’b 0000_0000
Type: Read/Write
Bits
Name
Size
[7:0]
Delay timing setting
8
Description
11111111: 25500 mS
11111110: 25400 mS
…
00000001: 100 mS
00000000: 0 mS
AUDIO ACCESSORY STATUS
Address: 11h
Reset Value: 8’b 0000_0010
Type: Read
Bits
Name
Size
[7:2]
Reserved
6
Do not use
1
CC_IN
1
0: CC_IN < 1.2 V
1: CC_IN > 1.5 V
0
DET
1
0: DET output is low
1: DET is output is high
Description
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19
FSA4480
FUNCTION ENABLE
Address: 12h
Reset Value: 8’b 0000_1000
Type: Read/Write
Bits
Name
Size
7
Reserved
1
Do not use
6
DET I/O Control
1
1: DET pin is in Open/Drain Configuration
0: DET pin is in Push/Pull Configuration
5
RES detection range setting
1
1: 10k to 2560 k
0: 1k to 256 k
4
GPIO control enable
1
1: enable
0: disable
3
Slow turn on control enable
1
1: enable
0: disable
2
MIC auto break out control enable
1
1: enable
0: disable
1
RES detection enable
1
1: enable; will be changed to ‘0’ after low resistance detection
0: disable
0
Audio jack detection and
configuration enable
1
1: enable; will be changed to ‘0’ after audio jack detection and
configuration
0: disable
Description
When GPIO control mode (manual switch control) is enable. ‘Switch control’ register is changed to read only. It will reflect
switch status. I2C slave address is
RES DETECTION PIN SETTING
Address: 13h
Reset Value: 8’b 0000_0000
Type: Read
Bits
Name
Size
[7:3]
Reserved
5
Do not use
[2:0]
Pin selection
3
000: CC_IN
001: DP/R
010: DN_L
011: SBU1
100: SBU2
101: Do not use
…
111: Do not use
Description
If RES detection pin is enable before setting PIN selection it will always do the CC_IN first. Recommend user to select the
pin first before setting the RES detection pin enable.
RES VALUE
Address: 14h
Reset Value: 8’b 1111_1111
Type: Read
Bits
Name
Size
[7:0]
Detected resistance value
8
Description
0000_0000 : R < 1 k
…
1111_1111: R > 300 K
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20
FSA4480
RES DETECTION THRESHOLD
Address: 15h
Reset Value: 8’b 0001_0110
Type: Read
Bits
Name
Size
[7:0]
RES detection threshold
8
Description
Selection by 1 KW per step if Reg 12h [5] = 0
Selection by 10 KW per step if Reg 12h [5] = 0
Default Value = 22 KW
0000_0000: 1 KW /10 KW
…
1111_1111: 256 KW / 2560 KW
RES DETECTION INTERVAL
Address: 16h
Reset Value: 8’b 0000_0000
Type: Read
Bits
Name
Size
[7:2]
Reserved
6
Do not use
[1:0]
RES detection interval
2
00: Single
01: 100 mS
10: 1 S
11: 10 S
Description
AUDIO JACK STATUS
Address: 17h
Reset Value: 8’b 0000_0001
Type: Read
Bits
Name
Size
[7:3]
Reserved
4
Do not use
3
4pole
1
1: 4 Pole SBU2 to MIC, SBU1 to audio ground
0: others
2
4pole
1
1: 4 Pole SBU1 to MIC, SBU2 to audio ground
0: others
1
3 pole
1
1: 3 pole
0: others
0
No audio accessory
1
1: No audio accessory
0: Audio accessory attached
Description
RES DETECTION /AUDIO JACK DETECTION INTERRUPT FLAG
Address: 18h
Reset Value: 8’b 0000_0000
Type: Read Clear
Bits
Name
Size
[7:3]
Reserved
5
Do Not Use
2
Audio jack detection and
configuration
1
0: Audio jack detection and configuration has not occurred
1: Audio jack detection and configuration has occurred
1
Low resistance occurred
1
0: Low resistance has not occurred
1: Low resistance has occurred
0
Low resistance detection
1
0: Low resistance has not occurred
1: Low resistance has occurred
Description
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21
FSA4480
RES /AUDIO JACK DETECTION INTERRUPT MASK
Address: 19h
Reset Value: 8’b 0000_0000
Type: Read Clear
Bits
Name
Size
[7:3]
Reserved
5
Do Not Use
2
Audio jack detection and
configuration
1
1: Mask Audio jack detection and configuration has occurred
interrupt
1
Low resistance occurred
1
1: Low resistance has occurred interrupt
0
Low resistance detection
1
1: Low resistance detection has occurred interrupt
Description
AUDIO JACK DETECTION REG1 VALUE
Address: 1Ah
Reset Value: 8’b 1111_1111
Type: Read
Bits
Name
Size
[7:0]
Audio jack detection value
8
Description
Resistance between SBU1 to SBU2
AUDIO JACK DETECTION REG2 VALUE
Address: 1Bh
Reset Value: 8’b 1111_1111
Type: Read
Bits
Name
Size
[7:0]
Audio jack detection value
8
Description
Resistance between SBU2 to SBU1
MIC DETECTION THRESHOLD DATA0
Address: 1Ch
Reset Value: 8’b 0010_0000
Type: Read/Write
Bits
Name
Size
[7:0]
MIC detection threshold DATA0
8
Description
MIC detection threshold DATA0
0010_0000: 300 mV
MIC DETECTION THRESHOLD DATA1
Address: 1Dh
Reset Value: 8’b 1111_1111
Type: Read/Write
Bits
Name
Size
[7:0]
MIC detection threshold DATA1
8
Description
MIC detection threshold DATA1
1111_1111: 2.4 V
I2C RESET
Address: 1Eh
Reset Value: 8’b 0000_0000
Type: W/C
Bits
Name
Size
[7:1]
Reserved
7
Reserved
0
I2C reset
1
0: default
1: I2C reset
Description
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FSA4480
CURRENT SOURCE SETTING
Address: 1Fh
Reset Value: 8’b 0000_0111
Type: Write
Bits
Name
Size
[7:4]
Reserved
4
Reserved
[3:0]
Current Source Setting
4
1111: 1500 mA
0111: 700 mA
0001: 100 mA
0000: invalid
Description
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23
FSA4480
APPLICATION INFORMATION
Over−Voltage Protection
Headset Detection
FSA4480 features over−voltage protection (OVP) on
receptacle side pins that switches off the internal signal
routing path if the input voltage exceeds the OVP threshold.
If OVP is occurred, interrupt signal can be send by INT
signal and FLAG data will provide information that which
pin had OVP event.
FSA4480 integrates headset unplug detection function by
detecting the CC_IN voltage. The function is always active
when device is enabling. DET will be high when CC_IN is
low (CC_IN < 1.2 V). When CC_IN = High (CC_IN > 1.5
V), DET will be released to low.
Device Disable
Device Enable
CC_IN < VTH_L = 1.2 V
DET = 0
DET = 1
CC_IN > VTH_H = 1.5 V
DET = 0
DET = 0
MIC Switch Auto−off Function
Audio Ground Detection and Configuration
The function is active during control bit 0x12h bit[2] = 1.
When CC_IN is high (CC_IN > 1.5 V) and L,R, Audio
ground switches are under on status, MIC switch will be off
and receptacle side pin will be connected to ground for 50 mS
first. Then it shows high−Z status under MIC switch is set on
status.
The function is active when control bit 0x12h bit[0] = 1
and R, L AGND switches are set to be on status. For type−C
interface analog headset, the audio ground could be SBU1
pin or SBU2 pin. The function will provide autonomous
detection and configuration to route MIC and audio ground
signal accordingly.
Audio Jack detection
and configuration Start
REG2>= DATA1
and
REG1>=DATA1
REG2>REG1>DATA0
&& REG1DATA0>REG1
REG1>REG2>DATA0
&& REG2DATA0>RGE2
Hold current setting
MIC to SBU2,
Audio ground to SBU1
Sense to GSBU1
send INT
MIC to SBU1,
Audio ground to SBU2
Sense to GSBU2
send INT
DATA0>=REG1
and
DATA0>=REG2
Audio ground to SBU1
Sense to GSBU1
SBU2 switch open
Figure 4.
During detection and configuration, the R, L, Sense, MIC
and Audio ground switch will be off. After detection and
configuration, R and L switches will turn on according to
switch configuration and timing setting. MIC, Sense and
Audio ground will turn on according to detection results and
timing control setting.
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24
FSA4480
Resistance Detection
in the resistance flag register. The measurement could be
from 1 kW to 2.56 MW which is controlled by internal
register. The detection interval can be set at 100 ms, 1 s or
10 s by register 0x16h.
The function is active during control bit 0x12h bit[1] = 1.
It will monitor the resistance between receptacle side pins
and ground. During resistance detection, the switch which
is monitored will be off. The detection result will be saved
RES Detection Start
Enable RES Detection on
SBU2
Enable RES Detection on
SBU1
Enable RES Detection on
DP/R
Enable RES Detection on
CC_IN
Update RES value
register
And compare with
threshold
>threshold
If interval reg
=0
Yes
Enable RES Detection on
DP/L
Wait timer that set by
interval reg
and check
0x12 bit[2]= 1?
No
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