FSA7830BUCX

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Input Voltage Range, 0 to 5.4 V Up to 8-Channel Inputs Integrated 1/3, 2/3 Voltage Divider Integrated Over-Voltage Protection and Assertion Total Introduced Offset < ±10 mV ICC < 100 µA, Ishutdown < 1 µA 2 1.8 V I C Interface, Addr to Set Address for Multi Chip Solution It integrates 8 analog switches for input voltage selection, and voltage dividers to provide 1/3, 2/3 fraction of selected voltage. With another 3 analog switches, FSA7830 provides feasibility to choose 1/3, 2/3 or 1 times of selected voltage. FSA7830 also contains output buffer to enhance driving capability. It features over-voltage protection to ensure output less than 2 V, interrupt will be alerted at the same time. FSA7830 supports 1.8 V I2C interface to communicate with processor, and 2 address pins to provide multi-chip solution. Applications   Cell Phones Tablets Ordering Information Part Number Top Mark Operating Temperature Range FSA7830BUCX GT -40 to +85°C © 2016 Fairchild Semiconductor Corporation FSA7830 • Rev. 1.0 Package 16-Ball, 0.4 mm Pitch Wafer Level Chip Scale Package (WLCSP) Package (1.56 x 1.56 mm) www.fairchildsemi.com FSA7830 — 8-Channel Voltage MUX with Integrated Voltage Divider and OVP May 2016 1.8V VBAT INT SCL SDA VCC I2C controller I2C ADDR SW1 V1 SW2 V2 Vint Buffer &Clamping V3 12 bits ADC V4 V5 2/3 Vint VO 100KO V6 V7 V8 100nF 1/3 Vint SW3 GND Figure 1. © 2016 Fairchild Semiconductor Corporation FSA7830 • Rev.1.0 Application Diagram 10pF FSA7830 — 8-Channel Voltage MUX with Integrated Voltage Divider and OVP Typical Application www.fairchildsemi.com 2 Figure 2. 16 Ball WLCSP Package(Top View) Pin Definitions Pin# Name A1 V5 Input Port 5 A2 V6 Input Port 6 A3 V7 Input Port 7 A4 V8 Input Port 8 B1 V4 Input Port 4 B2 VCC B3 ADDR B4 VO Output Voltage C1 V3 Input Port 3 C2 ADDR C3 GND Ground C4 \INT I2C Interrupt D1 V2 Input Port 2 D2 V1 Input Port 1 D3 SCL I2C Clock D4 SDA I2C Data © 2016 Fairchild Semiconductor Corporation FSA7830 • Rev.1.0 Description Voltage Supply Address Pin, Bit 0 Address Pin, Bit 1 FSA7830 — 8-Channel Voltage MUX with Integrated Voltage Divider and OVP Pin Configuration www.fairchildsemi.com 3 Symbol Fast Mode Parameter fSCL I2C_SCL Clock Frequency tHD;STA Min. Max. Unit 0 400 kHz Hold Time (Repeated) START Condition 0.6 µs tLOW LOW Period of I2C_SCL Clock 1.3 µs tHIGH HIGH Period of I2C_SCL Clock 0.6 µs tSU;STA Set-up Time for Repeated START Condition 0.6 µs tHD;DAT Data Hold Time 0 (1) tSU;DAT Data Set-up Time tr Fall Time of I2C_SDA and I2C_SCL Signals tSU;STO µs 100 Rise Time of I2C_SDA and I2C_SCL Signals tf 0.9 (1) (1) ns 20+0.1Cb 300 ns 20+0.1Cb 300 ns Set-up Time for STOP Condition 0.6 µs tBUF BUS-Free Time between STOP and START Conditions 1.3 µs tSP Pulse Width of Spikes that Must Be Suppressed by the Input Filter 0 50 ns Note: 1. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU;DAT ≥ ns must be met. This is automatically the case if the device does not stretch the LOW period of the I2C_SCL signal. If such a device does stretch the LOW period of the I2C_SCL signal, it must output the next data bit to the I2C_SDA line tr_max + tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the I2C_SCL line is released. Figure 1. 2 TM Table 1. I C FSA7830 — 8-Channel Voltage MUX with Integrated Voltage Divider and OVP I2C Specifications Definition of Timing for Full-Speed Mode Devices on the I2C Bus Slave Address ADDR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 1 0 0 0 0 1 0 R/W 01 1 0 0 0 0 1 1 R/W 10 1 0 0 0 1 0 1 R/W 11 1 0 1 0 1 0 0 R/W © 2016 Fairchild Semiconductor Corporation FSA7830 • Rev.1.0 www.fairchildsemi.com 4 The FSA7830 includes a full I2C slave controller. The I2C slave fully complies with the I2C specification version 2.1 requirements. This block is designed for fast mode, 400 kHz, signals. Examples of an I2C write and read sequence are shown in below Figure 3 and Figure 4 respectively. 8bits 8bits 8bits S Slave Address WR A Register Address K A Write Data A Write Data K+1 A Write Data K+2 A Note: A P Single Byte read is initiated by Master with P immediately following first data byte Figure 3. I2C Write Example 8bits 8bits 8bits 8bits S Slave Address WR A Register Address K A S Slave Address RD A Register address to Read specified Note: Write Data K+N-1 Read Data K A Read Data K+1 A Read Data K+N-1 NA P Single or multi byte read executed from current register location (Single Byte read is initiated by Master with NA immediately following first data byte) If Register is not specified Master will begin read from current register. In this case only sequence showing in Red bracket is needed From Master to Slave S Start Condition NA NOT Acknowledge (SDA High) RD Read =1 From Slave to Master A Acknowledge (SDA Low) WR Write=0 P Stop Condition Figure 4. © 2016 Fairchild Semiconductor Corporation FSA7830 • Rev.1.0 I2C Read Example FSA7830 — 8-Channel Voltage MUX with Integrated Voltage Divider and OVP I2C Interface www.fairchildsemi.com 5 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Min. Max. Unit Supply Voltage -0.5 6 V Input Voltage -0.5 6 V DC Input Diode Current -50 TSTG Storage Temperature -65 MSL Moisture Sensitivity Level (JEDEC J-STD-020A) ESD Human Body Model, JEDEC: JESD22A114 VCC V1~8 IIK Parameter All Pins 2 I/O to GND 2 Power to GND 2 Charged Device Model, JEDEC: JESD22-C101 mA +150 °C 1 Level kV 500 V Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VCC Parameter Supply Voltage Min. Max. Unit 2.7 5.5 V V1~8 Input Voltage 0 5.4 V VADDR Address Pin Voltage 0 VCC V VSCL,SDA,\INT I2C Bus Voltage Swing 0 1.8 V TA Operating Temperature -40 +85 °C © 2016 Fairchild Semiconductor Corporation FSA7830 • Rev.1.0 FSA7830 — 8-Channel Voltage MUX with Integrated Voltage Divider and OVP Absolute Maximum Ratings www.fairchildsemi.com 6 All typical value are for VCC=3.7 V at TA=25°C, with 100 KΩ and 100 nF+10 pF loading at VO, unless otherwise specified. Symbol VIK Parameter Condition Clamp Diode Voltage VCC (V) TA=- 40°C to +85°C Min. IIN=-18 mA -0.7 VIHI2C High-Level Input Voltage 2.7 to 5.5 VILI2C Low-Level Input Voltage 2.7 to 5.5 Hysteresis of Schmitt Trigger Inputs 2.7 to 5.5 0.09 2.7 to 5.5 -10 VHYSI2C II2C Typ. Max. Input Current of SDA, SCL and \INT Input Voltage 0.26 V to 2 V 1.26 Unit V V 0.54 V V 10 µA 1 µA ICCTI2C VCC current when SDA or SCL is Input Voltage 1.8 V HIGH VIHADDR High-Level Input Voltage 2.7 to 5.5 VILADDR Low-Level Input Voltage 2.7 to 5.5 VHYSADDR Hysteresis of Schmitt Trigger Inputs 2.7 to 5.5 VOLSDA Low-Level Output Voltage of SDA Pin 4 mA Sink Current (Open-Drain) 2.7 to 5.5 0.36 V VOLINTN Low-Level Output Voltage of \INT 4 mA Sink Current (Open-Drain) 2.7 to 5.5 0.36 V RON1 Switch1 On Resistance (2) RON2 Switch2 On Resistance RVD Voltage Divider On Resistance ICC Quiescent Supply Current ICCZ Disable Mode Leakage Current (2) 5.5 V 0.54 0.09 V V 2.7 to 5.5 100 200 Ω 2.7 to 5.5 100 200 Ω 2.7 to 5.5 All blocks in Enable Mode 1.26 1 MΩ 2.7 to 5.5 2.7 to 5.5 -1 100 µA 3.9 µA ILEAK,ON Leakage Current of each channel from V1~8 to GND in Enable Mode 2 µA ILEAK,OFF Leakage Current of each channel from V1~8 to GND in Disable Mode 1 µA VOFFSET Offset Voltage introduced by FSA7830, referring to VO 10 mV 2.15 V VOVP Over-Voltage Protection Threshold (Low to High) VOVP,HYS Over-Voltage Assertion Hysteresis VCLAMPING Clamping Voltage on VO when OVP happens VO,DYNAMIC VO Dynamic Range Register 06h set to „00‟ 2.7 to 5.5 -10 2.7 to 5.5 1.87 2.7 to 5.5 2.00 50 Register 06h set to „00‟ 2.7 to 5.5 1.87 100 KΩ between VO to 0.9 V, output buffer has the ability to drive the target value with maximum 1% mismatch 2.7 to 5.5 0.5 2.00 FSA7830 — 8-Channel Voltage MUX with Integrated Voltage Divider and OVP DC Electrical Characteristics mV 2.15 V 2.1 V Note: 2. Guaranteed by Design. © 2016 Fairchild Semiconductor Corporation FSA7830 • Rev.1.0 www.fairchildsemi.com 7 All typical value are for VCC=4.2 V at TA=25°C, with 100 KΩ and 100 nF+10 pF loading at VO, unless otherwise specified. Symbol Parameter Condition VCC (V) TA=- 40°C to +85°C Min. Typ. Max. Unit CI Input Capacitance on (3) V1~8 F=1 MHz 2.7 to 5.5 50 pF tSETTLING VO Settling Time after (3) each Switching RS=50 Ω, CO=100 nF+10 pF, RO=100 KΩ, VO reaches 99% of target value 2.7 to 5.5 200 µs Loading on VO switches from VO Buffer Load Response, 100 nF to CO=100 nF+10 pF, Settling Time of Load RO=100 K. (3) Change VO reaches 99% of target value 2.7 to 5.5 150 ns tLOADRESPONSE PSRR Power Supply Rejection Ratio of VO from VCC Power supply noise, F=217 Hz, 2.7 to 5.5 Vpp=50 mV, CO=100 nF+10 pF, RO=100 KΩ 70 dB Xtalk Cross Talk between V1~8 F=500 KHz, Vpp=50 mV, 2.7 to 5.5 CO=100 nF+10 pF, RO=100 KΩ 80 dB Note: 3. Guaranteed by characterization and not tested in production. © 2016 Fairchild Semiconductor Corporation FSA7830 • Rev.1.0 FSA7830 — 8-Channel Voltage MUX with Integrated Voltage Divider and OVP AC Electrical Characteristics www.fairchildsemi.com 8 Subsequent to the initial power up or reset; if the processor writes a “1” to one of interrupt mask bits when the system is already powered up, the \INT pin stays HIGH-Z and ignores corresponding interrupt until the interrupt mask bit is cleared. If an event happens that would ordinarily cause an interrupt when the interrupt mask bit is set, the \INT pin goes LOW when the interrupt mask is cleared. Interrupt operation The \INT pin is an active low, open drain output which indicates to the host processor that an interrupt has occurred in the FSA7830 which needs attention. The \INT pin is HIGH-Z by default after power-up or device reset. The \INT pin stays HIGH-Z in preparation of future interrupts. When an interruptible event occurs, \INT is driven LOW and is HIGH-Z again when the processor clears the interrupt by reading the interrupt registers. VCC POR I2C Chip Enable Config Reg 02h Reg 02h,06h SW1/2/3 Enable &Config1 Reg 03h Output Enable Interrupt Mask SW1/2/3 Enable &Config2 SW1/2/3 Enable &Config3 Reg 02h Reg 05h Reg 03h Reg 03h Buffer Enable VO HiZ As Config 1 Figure 5. As Config 2 Typical Application Sequence Buffer & Clamping Enable Truth Table To prevent non-ideal waveforms on VO node, enable of Output Buffer and Clamping circuitry depends on status of multi-internal register values. Table 2. Register Map Registers Chip Enable SW1 Enable SW2 Enable SW3 Enable Output Enable Buffer & Clamping Enable 0 x x x x 0 1 0 x x x 0 1 x 0 x x 0 1 1 1 x 0 0 1 1 1 x 1 1 © 2016 Fairchild Semiconductor Corporation FSA7830 • Rev.1.0 FSA7830 — 8-Channel Voltage MUX with Integrated Voltage Divider and OVP Application Information www.fairchildsemi.com 9 Table 3. Register Map Address Register Name Type Rst Val Description 0x01 Device ID RO 08 Device Version and Revision 0x02 Control RW 00 Device Control 0x03 SWCTL RW 00 Switch Status Control 0x04 INT RO 00 Interrupt 0x05 INT_MASK RW 80 Interrupt Mask 0x06 OVP RW 00 OVP Threshold Notes: 4. Do not use registers that are blank. 5. Values read from undefined register bits are not defined and invalid. Do not write to undefined registers. Table 4. Register Device ID Address: 01h Reset Value: 0x0000_1000 Type: Read Bits Name Size Description 7:6 Vendor ID 2 Vendor ID 5:3 Version ID 3 Device Version ID 2:0 Revision ID 3 Revision History ID Table 5. Control Address: 02h Reset Value: 0x0000_0000 Type: Read/Write Bits Name Size Description 7 Chip Enable 1 FSA7830 Enable/Shutdown 0: Shutdown (all other registers, including bits of this register, reset to default value) 1: Enable 6 Output Enable 1 Output Buffer Enable 0: Disable, VO maintains HiZ 1: Enable OVP action 2 Actions after OVP 00: Clamp output voltage to 2 V (based on register 06h) 01: Pull VO to 0V 10: No Action Reserved 4 Do Not Use © 2016 Fairchild Semiconductor Corporation FSA7830 • Rev.1.0 FSA7830 — 8-Channel Voltage MUX with Integrated Voltage Divider and OVP Register Definitions www.fairchildsemi.com 10 Address: 03h Reset Value: 0x0000_0000 Type: Read/Write Bits Name Size Description 7 SW1 Enable 1 Switch 1 Enable 0: All Switches Off 1: One switch on, status based on SW1 Control 3 Switch 1 Control 000: V1 to Vint 001: V2 to Vint 010: V3 to Vint 011: V4 to Vint 100: V5 to Vint 101: V6 to Vint 110: V7 to Vint 111: V8 to Vint 3 SW2 Enable 1 Switch 2 Enable 0: All Switches Off 1: One switch on, status based on SW2 Control 2 Switch 2 Control 00: VO to Vint 01: VO to 1/3Vint 10: VO to 2/3Vint 11: Reserved 0 SW3 Control 1 Switch 3 Control 0: SW3 OFF 1: SW3 ON Table 7. INT Address: 04h Reset Value: 0x0000_0000 Type: Read/Clear Bits Name Size 7 OVP 1 0: OVP event has not occurred 1: OVP event has occurred Reserved 7 Do Not Use FSA7830 — 8-Channel Voltage MUX with Integrated Voltage Divider and OVP Table 6. SWCTL Description Table 8. INT_MASK Address: 05h Reset Value: 0x1000_0000 Type: Read/Write Bits Name Size 7 OVP 1 0: Do not mask OVP interrupt 1: Mask OVP interrupt Reserved 7 Do Not Use © 2016 Fairchild Semiconductor Corporation FSA7830 • Rev.1.0 Description www.fairchildsemi.com 11 FSA7830 — 8-Channel Voltage MUX with Integrated Voltage Divider and OVP Table 9. OVP Address: 06h Reset Value: 0x0000_0000 Type: Read/Write Bits Name Size Reserved 5 Do Not Use 3 Over-voltage protection threshold 000: Default 001: +50 mV 010: +100 mV 011: -250 mV 100: -50 mV 101: -100 mV 110: -150 mV 111: -200 mV OVP Threshold Description The table below pertains to the WLCSP package information on the following page. Physical Dimensions Product D E X Y FSA7830BUCX 1.56 mm 1.56 mm 0.18 mm 0.18 mm © 2016 Fairchild Semiconductor Corporation FSA7830 • Rev.1.0 www.fairchildsemi.com 12 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. 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