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FSA8069
Audio Jack IC Featuring Impedance and Moisture Detection
Features
Description
The FSA8069 is an audio jack detection switch for
3.5 mm and 2.5 mm headsets. The FSA8069 features
impedance detection and moisture sensing, which
prevents false detection of accessories in the audio
jack. An integrated MIC switch allows a processor to
configure attached accessories. An LDO provides DC
bias to microphone and remote key circuit in accessory.
The FSA8069 detects seven headset impedance steps
and supports configurable gain in the amplifier
according to the type of load. The architecture is
designed to allow headphones to be used for listening to
music from mobile handsets, personal media players,
and portable peripheral devices.
Detection:
Accessory Plug-In
Send / End Key Press
Impedance Detection
Prevents False Detection due to Moisture
VDD: 3.0 V to 4.5 V
VIO: 1.6 V to VDD
THD (MIC): 0.01% Typical
15 kV Air Gap ESD
Detects 7 Steps of Headset Impedance
Integrates LDO for MIC Bias Circuit
MIC Switch Removes Audio Jack “Pop” and “Click”
Caused by MIC Bias
Applications
Any Device with 3.5 mm and 2.5 mm Audio Jack
Cellular Phones, Smart Phones, and Tablets
MP3, GPS, and PMP
FSA8069
Processor
I2C
/ Control
Impedance
/ Moisture
Detection
Power
+
Audio Jack
-
MICBIAS
LDO
Audio
Codec
Figure 1.
Block Diagram
Ordering Information
Part Number
(1)
FSA8069UCX
Operating
Temperature Range
Top Mark
Package
Packing
Method
-40°C to 85°C
MX
12-Ball WLCSP, 1.415 mm x 1.615 mm,
0.4 mm Pitch
Tape & Reel
Notes:
1. Includes backside lamination.
© 2014 Fairchild Semiconductor Corporation
FSA8069 • Rev. 1.3
www.fairchildsemi.com
FSA8069 — Audio Jack IC Featuring Impedance and Moisture Detection
February 2015
FSA8069
µP
(AP or CP)
/INT
/INT
SCL
SDA
SCL
SDA
I2C / Control
Impedance/
Moisture
Detection
K/P
K/P
0.1-1µF
VIO
1µF
VDD
Power
LDO
ADCIN
2.2k
(Note #2)
LDO
2.8V, 5mA
Key-Press
Detection
C1
(Note #3)
L
R G
M
220nF
(Note #3)
J_MIC
MIC
MICIN
Audio
Codec
J_DET
Internal
Regulator
GND
GND
HPOUT_L
HPOUT_R
10k
(Note #4)
Figure 2.
System Diagram
Notes:
2. 2.2 kΩ can generally be used in applications to bias the accessory microphone. Two separate resistors totaling
2.2 k with a large capacitor between them can improve noise rejection performance, as shown in Figure 7.
3. A DC-blocking capacitor (typically 1 µF) should be used when the codec requires AC-coupled input only. This
capacitor can be removed and be tied to directly without C1 if the MICIN of the codec supports DC-coupled input.
4. A pull-down resistor allows the FSA8069 to detect Hi-Z (open cable) type accessories due to J_DET contact to
left when an accessory is inserted.
© 2014 Fairchild Semiconductor Corporation
FSA8069 • Rev. 1.3
www.fairchildsemi.com
2
FSA8069 — Audio Jack IC Featuring Impedance and Moisture Detection
Typical Application Diagram
VDD
INTB
SCL
A
LDO
K/P
SDA
B
GND
GND
VIO
C
MIC
J_MIC
J_DET
D
1
Figure 3.
2
3
Pin Assignment (Through View)
Pin Definitions
Name Pin #
Type
Description
VDD
A1
Power
Device supply (3.0 V to 4.5 V)
VIO
C3
Power
I/O supply (1.6 V to VDD)
LDO output (2.8 V)
LDO
B1
Power
J_DET
D3
Detection Input
MIC
D1
Signal Path
Microphone switch path that connects to the microphone input of the codec
J_MIC
D2
Signal Path
Microphone switch path that connects to the audio jack
SDA
B3
DATA
I C data
SCL
A3
DATA
I C clock
INTB
A2
Output
Interrupt output
LOW: interrupt is asserted (active)
HIGH: interrupt is not asserted
K/P
B2
Output
Indicates state of headset key for a 4-pole jack when a key is being pressed
HIGH: Key is being pressed
LOW: Key is not being pressed
GND
C1, C2
Power
Device ground
© 2014 Fairchild Semiconductor Corporation
FSA8069 • Rev. 1.3
Input from the audio jack; plug insert / removal detection pin
2
2
www.fairchildsemi.com
3
FSA8069 — Audio Jack IC Featuring Impedance and Moisture Detection
Pin Configuration
Moisture Detection
Headset Impedance Detection Range
Moisture in the audio jack can cause the phone to
incorrectly route audio signals to the audio jack rather
than the phone speaker or microphone. Users perceive
this as a dropped call or muted phone. The FSA8069
protects against this type of false plug insertion
notification and asserts a Moisture Change interrupt in
Interrupt1 (0x04h) Register.
FSA8069 detects jack insertion and removal by
monitoring impedance on the J_DET pin. The accessory
types is updated in the Status (03H) register.
Figure 4.
Moisture Impedance Detection
Table 1.
Impedance Detection Range
Accessory Type
Impedance
Step
Target Range
[Ω]
Headset #1
Step 0
0 to 24
Headset #2
Step 1
24 to 42
Headset #3
Step 2
42 to 100
Headset #4
Step 3
100 to 200
Headset #5
Step 4
200 to 450
Headset #6
Step 5
450 to 1,000
Line_In/Out (CarKit)
Step 6
1000 to 15,000
Music Mode
When a 4-pole headset is inserted into the audio jack
and a music/listening application is used, the MIC bias
is normally enabled for headset button press detection
(i.e. mute, volume change, etc.). This consumes power
due to a constant path from the MIC bias resistor and
microphone in the headset to GND. Fairchild has
developed a Music Mode to enable the MIC switch
periodically to monitor for a pressed button. This results
in a power savings for battery-sensitive devices, such as
cell phones or MP3 players. The FSA8069 enters Music
Mode when the Music Mode Enable bit in
CONTROL(02h) is set and a plug is inserted,. Music
Mode reduces MIC bias current by approximately 90%
with the default Music Mode timing (0Bh) register value.
MIC
BIAS
Audio
CODEC
R
L
2.2K
LDO Operation
The integrated microphone bias LDO is set to 2.8 V.
The LDO can be used to bias a microphone accessory
2
and is enabled / disabled by the I C register bit LDO
ENABLE in the COLTROL register(02h)). This LDO
requires a 0.22 µF to 1 µF coupling capacitor on the
output. The coupling capacitor should be placed close to
the LDO pin.
Headset Key-Press Operation
The headset key-press comparator threshold is a
function of the MIC bias voltage, MIC bias resistor, and
the MIC impedance. All of these variables must be
considered when calculating the key-press resistor
value. Figure 6 is an example of how to calculate the
key-press resistor value.
MIC
MIC
1uF
MIC Bias Current Flow
Figure 5.
MIC Bias Leakage Path
RBIAS
Key Press
VBIAS
1
VTH_SE=0.69 V
VBIAS=2.8 V
RBIAS=2.2 kΩ
RMIC=2 kΩ
RMIC
Figure 6.
© 2014 Fairchild Semiconductor Corporation
FSA8069 • Rev. 1.3
-
VTH_SE
VTH_SE
RKEY
Key Press
Resistor
1
1
RKEY ≤
VBIAS-VTH_SE
/
RMIC
RBIAS
RKEY ≤ 1100 Ω
Example Key-Press Resistor Calculations and Values
www.fairchildsemi.com
4
FSA8069 — Audio Jack IC Featuring Impedance and Moisture Detection
Application Information
PCB layout can degrade the audio quality and be a
contributory factor in audible noise coupling issues,
high-frequency noise (ESD/ EMI) issues, and signal
losses. To avoid unexpected noise issues and to
achieve stable regulator output, all external components
should be placed as close to the FSA8069 as possible.
Decrease the spacing between the traces for MIC and
ground signals between the audio jack to increase the
inductive coupling of these signals. In effect, this creates
a low-frequency band-pass filter that shunts ESD
energy to ground before it reaches internal components.
Where feasible, lay the MIC trace as a shielded stripline;
as shown in Figure 9.
FSA8069
MICBIAS_2.8V
LDO
GND
LDO
2.8V, 5mA
C1
R1
C2
~3-4 mils
GND
R2
MIC
J_MIC
Codec MICIN
~3-4 mils
Audio Jack
Figure 7.
MIC Bias and MIC Switch Circuit
R1
C1
A1
A2
A3
B1
B2
B3
C1
C2
C3
D1
D2
D3
MIC
GND
~3-4 mils
GND
Figure 9.
MIC PCB Trace as Shield Strip Line
R2
Audio Jack
C2
Codec MICIN
GND
Figure 8.
Recommended PCB Layout Placement
© 2014 Fairchild Semiconductor Corporation
FSA8069 • Rev. 1.3
www.fairchildsemi.com
5
FSA8069 — Audio Jack IC Featuring Impedance and Moisture Detection
Recommended LDO Bias Circuit and MIC Switch PCB Layout
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VDD, VIO
Parameter
Min.
Max.
Unit
Supply Voltage from Battery
-0.5
6.0
V
VSW
Switch I/O Voltage (MIC, J_MIC)
-0.5
VDD+0.5
V
VJD
Input Voltage for J_DET Input
-1.5
VDD+0.5
V
IIK
Input Clamp Diode Current
-50
ISW
Switch I/O Current
TSTG
Storage Temperature Range
-65
mA
50
mA
+150
C
TJ
Maximum Junction Temperature
+150
C
TL
Lead Temperature (Soldering, 10 Seconds)
+260
C
IEC 61000-4-2 System ESD
ESD
Human Body Model,
ANSI/ESDA/JEDEC JS-001-2012
Charged Device Model,
JEDEC JESD22-C101
Air Gap
15
Contact
8
J_DET, J_MIC, VDD, VIO, GND
8
All Other Pins
2
All Pins
1
kV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Unit
VDD
Battery Supply Voltage
3.0
4.5
V
VIO
Parallel I/O Supply Voltage
1.6
VDD
V
VSW
Switch Input Voltage (J_MIC, MIC)
0
3.0
V
-40
+85
ºC
-1.4
+1.4
V
TA
Operating Temperature
J_DETAudioV Audio Voltage Range on J_DET Pin
COUT
RJ_DET
LDO Output Capacitance
220
Resistance on Audio Accessory Left Channel to Generate Valid Attach
© 2014 Fairchild Semiconductor Corporation
FSA8069 • Rev. 1.3
nF
15.75
kΩ
www.fairchildsemi.com
6
FSA8069 — Audio Jack IC Featuring Impedance and Moisture Detection
Absolute Maximum Ratings
All typical values are at TA=25°C, CIN_VDD=1.0 µF, CIN_VIO=0.1 µF, and COUT_LDO=0.22 µF unless otherwise specified.
Symbol
Parameter
VDD (V)
Conditions
TA = -40 to +85°C
Min.
Typ.
Max.
Unit
MIC Switch
RON
RFLAT(ON)
MIC Switch On Resistance
3.8
IOUT=30 mA,
VIN=2.2 V
0.50
On Resistance Flatness
3.8
IOUT=30 mA,
VIN=1.6 V to VDD
0.30
0
MIC, J_MIC Ports
VA=4.3 V
IOFF
Power-Off Leakage Current
Through Switch
ION
Input Leakage Current MIC,
J_MIC switch ON
IOZ
Off Leakage Current
Ω
Inputs VMIC,
VJMIC=3.0 V, Other
3.0 to 4.5
Side of Switch
Port Floating
4.5
MIC and J_MIC
Port VIN=3.0 V
Comparator Threshold for Key
Detection
3.0 to 4.5
Detection
Threshold (0Fh)
[3:0]=1001
(790 mV)
0.79
Tolerance between Impedance
Detection Steps (see Table 1)
3.0 to 4.5
Impedance
Detection Mode
5%
1.50
3
µA
1
µA
1
µA
Key Press
VCOMP
V
J_DET
J_DETTolerance
Parallel I/O (KP, INTB)
VOH
Output High Voltage
IOH=-100 µA
VOL
Output Low Voltage
IOL=+100 µA
0.8 × VIO
0.2 × VIO
V
2
I C Controller DC Characteristics Fast Mode (400 kHz)
VIL
Low-Level Input Voltage
VIH
High-Level Input Voltage
0.3 × VIO
0.7 × VIO
VOL1
Low-Level Output Voltage at 3 mA Sink
Current (Open-Drain)
Ii2C
Input Current of I2C_SDA and I2C_SCL Pins,
Input Voltage 0.26 V to 2.34 V
VIO>2 V
V
V
0
VIO
