FSA831AL10X-F131

ON Semiconductor Is Now To learn more about onsemi™, please visit our website at www.onsemi.com onsemi and       and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as-is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others. Features USB Detection Description USB Battery Charging Rev. 1.2 Supports Data Contact Detect (DCD) Dead Battery Provision (DBP) w ith 30-Minute Timer Isolation Sw itch Closes for Charging Dow nstream Port (CDP) Standard Dow nstream Port (SDP) Sw itch Type 28 V Over-Voltage Tolerance -2 V Under-Voltage Tolerance V BUS 10-Lead MicroPak™ 1.6 x 2.1 mm, 0.5 mm Pitch Package Ordering Information FSA831AL10X Applications The FSA831A is a charger-detection IC w ith an integrated isolation sw itch for use w ith a micro/mini USB port. The FSA831A detects battery chargers and is compliant w ith USB Battery Charging Specification, Rev 1.2 (BC1.2). The algorithm incorporates Data Contact Detection (DCD), w hich ensures that the shorter, inner pins of the USB connector are making contact prior to continuing w ith battery charger detection. The device determines if a Dedicated Charging Port (DCP), Charging Dow nstream Port (CDP), or a typical PC host, called a Standard Dow nstream Port (SDP), is connected. If a charger is detected, the FSA831A determines w hether the charger is a DCP or CDP. For SDP and CDP detection, an internal isolation sw itch is closed to connect the D+/D- lines of the USB cable to the resident USB transceiver w ithin the portable device. The FSA831A conforms to all the constraints for the Dead Battery Provision (DBP) w ithin the BC1.2 specification, including a 30-minute timer that cannot exceed 45 minutes, per BC1.2.  MP3, Mobile Internet Device (MID), Cell Phone, PDA, Digital Camera, Notebook and Netbook Typical Application CHG_AL Baseband Processor USB PHY GOOD_BAT FSA831A Regulator and Switch Control USB Port VBUS OVT DM_HOST DM_CON DP_HOST DP_CON VBUS_IN DD+ SW_OPEN ID Charger Detect GND Li+ Bat Charger GND CHG_DET Figure 1. Mobile Phone Exam ple © 2012 Semiconductor Components Industries, LLC December-2017, Rev 2. Publication Order Number: FSA831A/D FSA831A — USB2.0 High-Speed (480Mbps) Charger Detector with Isolation Switch FSA831A — USB2.0 High-Speed (480Mbps) Charger Detection with Isolation Switch CHG_DET 10 9 VBUS 2 8 DM_CON DP_HOST 3 7 DP_CON CHG_AL_N 4 6 GND SW_OPEN 1 DM_HOST Control 5 GOOD_BAT Figure 2. Pin Assignm ents (Top View ) Pin Descriptions Name Pin # Description USB Interface DP_HOST 3 D+ signal connected to the resident USB transceiver on the phone DM_HOST 2 D- signal connected to the resident USB transceiver on the phone V BUS 9 Input voltage supply pin to be connected to the V BUS pin of the USB connector GND 6 Ground DP_CON 7 Connected to the USB connector D+ pin DM_CON 8 Connected to the USB connector D- pin CHG_DET 10 CMOS push/pull output connected to charger IC for indicating if a charger has been detected (LOW=charger not detected, HIGH=DCP or CDP charger has been detected). SW_OPEN 1 Open-drain output pin; requires pull-up resistor to I/O voltage supply (LOW=sw itch closed, Hi-Z=sw itch open). CHG_AL_N 4 CMOS open-drain output pin (LOW=V BUS is valid and charge is allow ed to be draw n from V BUS, Hi-Z=V BUS is not at a valid voltage). 5 Input that indicates if the battery is a good battery or a dead battery (LOW=dead battery, HIGH=good battery). Connector Interface Status Outputs Input Pin GOOD_BAT www.onsemi.com 2 FSA831A — USB2.0 High-Speed (480Mbps) Charger Detector with Isolation Switch Pin Configurations Device Detected GOOD_ SW_ CHG_ CHG_ BAT OPEN AL_N DET DP_HOST DM_HOST DP_CON DM_CON X Hi-Z LOW HIGH Hi-Z Hi-Z V DP_SRC CDP HIGH LOW LOW HIGH DP_CON DM_CON DP_HOST DM_HOST CDP LOW Hi-Z LOW HIGH Hi-Z Hi-Z V DP_SRC Hi-Z (2) HIGH LOW LOW LOW DP_CON DM_CON DP_HOST DM_HOST SDP (2) LOW Hi-Z LOW LOW Hi-Z Hi-Z V DP_SRC Hi-Z SDP, CDP, or DCP plugged in and after 30-minute timer expires LOW Hi-Z Hi-Z LOW Hi-Z Hi-Z Hi-Z Hi-Z V BUS < V BUS valid to V BUS > V BUS valid operation prior to completing detection of SDP, CDP, or DCP. Upon detection, all outputs sw itch as in row s above. X Hi-Z Hi-Z Hi-Z to LOW Hi-Z Hi-Z Hi-Z Hi-Z SDP Hi-Z (1) DCP Notes: 1. Hi-Z is the internal state of DM_CON. Since a DCP has been detected, DM_CON is shorted to DP_CON externally and DM_CON is shorted to V DP_SRC. 2. Proprietary chargers that leave DP_CON and DM_CON floating are detected as SDP. Proprietary chargers that force DP_CON=2V and DM_CON=2.7 V (or any other voltages) can be detected as CDP, DCP or SDP depending on the resistances of the resistor dividers on DP_CON and DM_CON used to create the voltages on those pins. www.onsemi.com 3 FSA831A — USB2.0 High-Speed (480Mbps) Charger Detector with Isolation Switch Table 1. Functionality Data Contact Detect (DCD) DCD relies on the D+ and D- lines being present. DCD w aits until the internal timeout (tDCD_TIMEOUT) has expired in the follow ing cases:  If a charger does not have a D+ pin on the USB connector  If the D+ pin is not shorted to D- pin on the connector  If D+ is pulled up to a supply  If D+ does not have a sufficient path to ground to defeat a pull-up IDP_SRC (10 µA typical) current source. The FSA831A proceeds w ith charger detection even though it is unlikely a charger is present. If there is no charger, the algorithm reports an SDP and closes the sw itch. If a device is pulling D+ HIGH, this voltage presents itself to the USB transceiver or Physical Layer Interface (PHY) block w ithin a System on Chip (SoC) after the sw itch is closed. If the DCD timeout w as insufficient and the PHY block is so equipped, DCD and the charging algorithm can be repeated in the PHY block. The stipulation is that the total time from V BUS valid to USB transceiver connection w ith a 1.5 kΩ pullup to 3.3 V must be one (1) second, per USB 2.0 standards (USB 2.0 connect timing), provided the portable device does not have a dead battery. A typical PS/2 port (old PC mouse / keyboard port) has a resistive pull-up to V BUS. This can cause the DCD to exceed the maximum w ait time (tDCD_TIMEOUT) and proceed to charger detection. The likely path through charger detection is classifying the PS/2 port as an SDP port. This results in closing the USB sw itches, w hich causes the voltage on the DP_CON and DM_CON pins to pass through the sw itch to DP_HOST and DM_HOST, respectively. Since voltages on the PS/2 port can go as high as the V BUS voltage, the DP_HOST and DM_HOST pins can be pulled up to V BUS. The USB PHY connected to DP_HOST and DM_HOST must be equipped to handle these higher voltages. CHG_AL_N Output and Output Timing CHG_AL_N output indicates that charge is allow ed to be draw n from V BUS w hen CHG_AL_N is LOW. When FSA831A first pow ers up and prior to detection, the CHG_AL_N pin can follow V BUS up to 28 V, w hich is the absolute maximum V BUS voltage allow ed. Whenever V BUS is at GND, the FSA831A is completely off and the sw itches and all I/Os are in the Hi-Z state. When V BUS climbs above the valid V BUS threshold, detection occurs automatically and CHG_DET, SW_OPEN, and CHG_AL_N all simultaneously sw itch to the states indicated in Table 1 if GOOD_BAT is HIGH (see Dead Battery Provision description for GOOD_BAT = LOW). Dead Battery Provision (DBP) BC1.2 and USB 2.0 allow a portable device (defined as a device w ith a battery) w ith a dead battery to take a maximum of 100 mA from the USB V BUS line for a maximum of 45 minutes as long as the portable device forces the D+ line to V DP_SRC (0.6 V typical). FSA831A starts detection w hen V BUS crosses the V BUSVLD threshold and, if it detects a CDP or SDP and GOOD_BAT is HIGH, automatically closes the sw itch and does not force the DP_CON pin to V DP_SRC. Once the charger detection is completed, the FSA831A starts a 30-minute timer and forces the DP_CON pin to V DP_SRC until the timer elapses. During the 30 minute period, if GOOD_BAT is LOW, V DP_SRC is applied to DP_CON and the D+/D- sw itches are opened, If GOOD_BAT is HIGH, V DP_SRC is not applied to DP_CON and the D+/D- sw itches are closed, If GOOD_BAT is LOW w hen 30 minute timer expires; regardless of w hether an SDP, CDP, or DCP w as previously detected; the FSA831A removes V DP_SRC from DP_CON and forces CHG_DET LOW and CHG_AL_N to HiZ (SW_OPEN remains Hi-Z) To exit this fault condition, remove V BUS, w ait for all the V BUS Printed Circuit Board (PCB) capacitance to discharge, and re-apply V BUS. Table 1 provides the functionality of the pins w hen the timer expires. When GOOD_BAT is HIGH and the battery is removed from the portable device w hile V BUS is valid, bringing GOOD_BAT LOW; the FSA831A opens the isolation sw itches on DP_CON and DM_CON and forces the DP_CON pin to V DP_SRC. In this scenario, the timer generally expires because the SoC does not have a supply to bring GOOD_BAT HIGH unless the battery that w as removed is re-inserted w ithin 30 minutes from w hen the USB plug is inserted. If an SDP or CDP is inserted w ith GOOD_BAT HIGH during the 30-minute timer, then GOOD_BAT changes to LOW; SW_OPEN changes to Hi-Z and the counter continues counting until the 30 minutes expires. If GOOD_BAT then returns to HIGH, SW_OPEN changes to LOW and finishes out the 30-minute time. GOOD_BAT has an internal pull-dow n resistor to ensure it is LOW w hen the SoC is pow ered dow n. This input is designed to have very low thresholds to interface w ith low -voltage SoCs driven w ith 1.2 V supplies. Proprietary Chargers Only legitimate USB chargers that force V DM_SRC (0.6V typical) on DM_CON w hen V DP_SRC is applied to DP_CON are detected by the FSA831A and cause CHG_DET signal to be asserted. Any charger that forces a HIGH on both DP_CON and DM_CON can be detected as CDP, DCP, or SDP (depending on the resistances of the resistor dividers on DP_CON and DM_CON) and used to create the HIGH voltages on those pins. Any charger that lets both DP_CON and DM_CON signals float is detected as an SDP and CHG_DET stays de-asserted. In cases w here the proprietary charger is detected as an SDP or CDP, since the sw itches are closed and access is made from the USB connector D+ and D- lines to the USB PHY block; the chargers can be detected w ithin the PHY if so equipped Ground Drops When a DCP is detected, V DP_SRC is forced on DP_CON provided GOOD_BAT is HIGH or if GOOD_BAT is LOW and the DBP timer has not expired. For current up to 1.5 A flow ing into the V BUS and GND lines of the USB cable, this can translate to substantial ground drops that lift the ground of the portable device. This drop adds to the voltage at the DP_CON pin as seen from the DCP D+ pin. For the maximum ground drop of 375 mV specified in the BC1.2 specification and for the maximum V DP_SRC of 0.7 V, the www.onsemi.com 4 FSA831A — USB2.0 High-Speed (480Mbps) Charger Detector with Isolation Switch Functional Description V BUS voltages up to 28 V can be tolerated by the V BUS pin. V BUS can tolerate voltages up to -2 V for cases w here a charger is plugged in backw ards. VBUS Tolerance Detection Flow When V BUS rises, an internal Pow er On Reset (POR) detects this voltage and prepares the FSA831A for charger detection. The flow diagram in Figure 3 show s how the FSA831A achieves battery charger detection consistent w ith BC1.2. Check VBUS Else VBUS>VBUSVLD Start Timer Enable DCD Else D+ < VLGC for tDCD_DBNC AND tDCD_TIMEOUT Primary detection D+ = VDP_SRC D- > VDAT_REF AND D- < VLGC ( D- < VDAT_REF OR D- > VLGC) • • • • Secondary Detection D- = VDM_SRC D+ > VDAT_REF • D+ < VDAT_REF If VBUS