FSA831L10X-F131

Features USB Detection Description USB Battery Charging Rev. 1.2 Supports Data Contact Detect (DCD) Dead Battery Provision (DBP) w ith 30-Minute Timer Isolation Sw itch Closes for Charging Dow nstream Port (CDP) Standard Dow nstream Port (SDP) Sw itch Type 28V Over-Voltage Tolerance -2V Under-Voltage Tolerance V BUS 10-Lead MicroPak™ 1.6 x 2.1mm, 0.5mm Pitch Package Ordering Information FSA831L10X Applications  MP3, Mobile Internet Device (MID), Cell Phone, PDA, Digital Camera, Notebook and Netbook The FSA831 is a charger-detection IC w ith an integrated isolation sw itch for use w ith a micro/mini USB port. The FSA831 detects battery chargers and is compliant w ith USB Battery Charging Specification, Rev 1.2 (BC1.2). The algorithm incorporates Data Contact Detection (DCD), w hich ensures that the shorter, inner pins of the USB connector are making contact prior to continuing w ith battery charger detection. The device determines if a Dedicated Charging Port (DCP), Charging Dow nstream Port (CDP), or a typical PC host, called a Standard Dow nstream Port (SDP), is connected. If a charger is detected, the FSA831 determines w hether the charger is a DCP or CDP. For SDP and CDP detection, an internal isolation sw itch is closed to connect the D+/D- lines of the USB cable to the resident USB transceiver w ithin the portable device. The FSA831 conforms to all the constraints for the Dead Battery Provision (DBP) w ithin the BC1.2 specification, including a 30-minute timer that cannot exceed 45 minutes, per BC1.2. Related Resources Typical Application CHG_AL_N System on Chip (SoC) USB PHY GOOD_BAT FSA831 Regulator and Sw itch OVT Control USB Port V BUS DM_HOST DM_CON DP_HOST DP_CON VBUS_IN DD+ SW_OPEN ID Charger Detect GND Li+ Bat Charger GND CHG_DET Figure 1. Mobile Phone Exam ple © 2011 Semiconductor Components Industries, LLC. October-2017, Rev. 2 Publication Order Number: FSA831/D FSA831 — USB2.0 High-Speed (480Mbps) Charger Detector with Isolation Switch FSA831 — USB2.0 High-Speed (480Mbps) Charger Detection with Isolation Switch Pin Configurations CHG_DET 10 9 VBUS 2 8 DM_CON DP_HOST 3 7 DP_CON CHG_AL_N 4 6 GND SW_OPEN 1 DM_HOST Control 5 GOOD_BAT Figure 2. Pin Assignm ents (Top View ) Pin Descriptions Name Pin # Description USB Interface DP_HOST 3 D+ signal connected to the resident USB transceiver on the phone DM_HOST 2 D- signal connected to the resident USB transceiver on the phone V BUS 9 Input voltage supply pin to be connected to the V BUS pin of the USB connector GND 6 Ground DP_CON 7 Connected to the USB connector D+ pin DM_CON 8 Connected to the USB connector D- pin CHG_DET 10 CMOS push/pull output connected to charger IC for indicating if a charger has been detected (LOW=charger not detected, HIGH=DCP or CDP charger has been detected). SW_OPEN 1 Open-drain output pin; requires pull-up resistor to I/O voltage supply (LOW=sw itch closed, Hi-Z=sw itch open). CHG_AL_N 4 CMOS open-drain output pin (LOW=V BUS is valid and charge is allow ed to be draw n from V BUS, Hi-Z=V BUS is not at a valid voltage). 5 Input that indicates if the battery is a good battery or a dead battery (LOW=dead battery, HIGH=good battery). Connector Interface Status Outputs Input Pin GOOD_BAT www.onsemi.com 2 Table 1. Functionality Device Detected GOOD_ SW_ CHG_ CHG_ DP_HOST DM_HOST DP_CON DM_CON BAT OPEN AL_N DET X Hi-Z LOW HIGH Hi-Z Hi-Z V DP_SRC CDP HIGH LOW LOW HIGH DP_CON DM_CON DP_HOST DM_HOST CDP LOW Hi-Z LOW HIGH Hi-Z Hi-Z V DP_SRC Hi-Z (2) HIGH LOW LOW LOW DP_CON DM_CON DP_HOST DM_HOST SDP (2) LOW Hi-Z LOW LOW Hi-Z Hi-Z V DP_SRC Hi-Z SDP, CDP, or DCP plugged in and after 30-minute timer expires LOW Hi-Z Hi-Z LOW Hi-Z Hi-Z Hi-Z Hi-Z V BUS < V BUS valid to V BUS > V BUS valid operation prior to completing detection of SDP, CDP, or DCP. Upon detection, all outputs sw itch as in row s above. X Hi-Z Hi-Z Hi-Z to LOW Hi-Z Hi-Z Hi-Z Hi-Z SDP Hi-Z (1) DCP Notes: 1. Hi-Z is the internal state of DM_CON. Since a DCP has been detected, DM_CON is shorted to DP_CON externally and DM_CON is shorted to V DP_SRC. 2. Proprietary chargers that leave DP_CON and DM_CON floating are detected as SDP. Proprietary chargers that force DP_CON=2V and DM_CON=2.7V (or any other voltages) can be detected as CDP, DCP or SDP depending on the resistances of the resistor dividers on DP_CON and DM_CON used to create the voltages on those pins. Functional Description  If a charger does not have a D+ pin on the USB connector DP_CON and DM_CON pins to pass through the sw itch to DP_HOST and DM_HOST, respectively. Since voltages on the PS/2 port can go as high as the V BUS voltage, the DP_HOST and DM_HOST pins can be pulled up to V BUS. The USB PHY connected to DP_HOST and DM_HOST must be equipped to handle these higher voltages.  If the D+ pin is not shorted to D- pin on the connector, CHG_AL_N Output and Output Timing  If D+ is pulled up to a supply CHG_AL_N output indicates that charge is allow ed to be draw n from V BUS w hen CHG_AL_N is LOW. When FSA831 first pow ers up and prior to detection, the CHG_AL_N pin can follow V BUS up to 28V, w hich is the absolute maximum V BUS voltage allow ed. Whenever V BUS is at GND, the FSA831 is completely off and the sw itches and all I/Os are in the Hi-Z state. When V BUS climbs above the valid V BUS threshold, detection occurs automatically and CHG_DET, SW_OPEN, and CHG_AL_N all simultaneously sw itch to the states indicated in Table 1 if GOOD_BAT is HIGH (see Dead Battery Provision description for GOOD_BAT = LOW). Data Contact Detect (DCD) DCD relies on the D+ and D- lines being present. DCD w aits until the internal timeout (450ms typical) has expired in the follow ing cases:  If D+ does not have a sufficient path to ground to defeat a pull-up IDP_SRC (10µA typical) current source. The FSA831 proceeds w ith charger detection even though it is unlikely a charger is present. If there is no charger, the algorithm reports an SDP and closes the sw itch. If a device is pulling D+ HIGH, this voltage presents itself to the USB transceiver or Physical Layer Interface (PHY) block w ithin a System on Chip (SoC) after the sw itch is closed If the DCD timeout w as insufficient and the PHY block is so equipped, DCD and the charging algorithm can be repeated in the PHY block. The stipulation is that the total time from V BUS valid to USB transceiver connection w ith a 1.5kΩ pullup to 3.3V must be one (1) second, per USB 2.0 standards (USB 2.0 connect timing), provided the portable device does not have a dead battery. A typical PS/2 port (old PC mouse / keyboard port) has a resistive pull-up to V BUS. This can cause the DCD to exceed the maximum w ait time (tDCD_TIMEOUT) and proceed to charger detection. The likely path through charger detection is classifying the PS/2 port as an SDP port. This results in closing the USB sw itches, w hich causes the voltage on the Dead Battery Provision BC1.2 and USB 2.0 allow a portable device (defined as a device w ith a battery) w ith a dead battery to take a maximum of 100mA from the USB V BUS line for a maximum of 45 minutes as long as the portable device forces the D+ line to V DP_SRC (0.6V typical). FSA831 starts detection w hen V BUS crosses the V BUSVLD threshold and, if it detects a CDP or SDP and GOOD_BAT is HIGH, automatically closes the sw itch and does not force the DP_CON pin to V DP_SRC. Once the charger detection is completed, the FSA831 starts a 30-minute timer and forces the DP_CON pin to V DP_SRC until the timer elapses. During the 30 minute period, if www.onsemi.com 3 GOOD_BAT is LOW, VDP_SRC is applied to DP_CON and the D+/D- sw itches are opened, If GOOD_BAT is HIGH, V DP_SRC is not applied to DP_CON and the D+/D- sw itches are closed, If GOOD_BAT is LOW w hen 30 minute timer expires; regardless of w hether an SDP, CDP, or DCP w as previously detected; the FSA831 removes V DP_SRC from DP_CON and forces CHG_DET LOW and CHG_AL_N to HiZ (SW_OPEN remains Hi-Z) To exit this fault condition, remove V BUS, w ait for all the V BUS Printed Circuit Board (PCB) capacitance to discharge, and re-apply V BUS. Table 1 provides the functionality of the pins w hen the timer expires. When GOOD_BAT is HIGH and the battery is removed from the portable device w hile V BUS is valid, bringing GOOD_BAT LOW; the FSA831 opens the isolation sw itches on DP_CON and DM_CON and forces the DP_CON pin to V DP_SRC. In this scenario, the timer generally expires because the SoC does not have a supply to bring GOOD_BAT HIGH unless the battery that w as removed is re-inserted w ithin 30 minutes from w hen the USB plug is inserted. If an SDP or CDP is inserted w ith GOOD_BAT HIGH during the 30-minute timer, then GOOD_BAT changes to LOW; SW_OPEN changes to Hi-Z and the counter continues counting until the 30 minutes expires. If GOOD_BAT then returns to HIGH, SW_OPEN changes to LOW and finishes out the 30-minute time. SDP (depending on the resistances of the resistor dividers on DP_CON and DM_CON) and used to create the HIGH voltages on those pins. Any charger that lets both DP_CON and DM_CON signals float is detected as an SDP and CHG_DET stays de-asserted. In cases w here the proprietary charger is detected as an SDP or CDP, since the sw itches are closed and access is made from the USB connector D+ and D- lines to the USB PHY block; the chargers can be detected w ithin the PHY if so equipped Ground Drops When a DCP is detected, V DP_SRC is forced on DP_CON provided GOOD_BAT is HIGH or if GOOD_BAT is LOW and the DBP timer has not expired. For current up to 1.5A flow ing into the V BUS and GND lines of the USB cable, this can translate to substantial ground drops that lift the ground of the portable device. This drop adds to the voltage at the DP_CON pin as seen from the DCP D+ pin. For the maximum ground drop of 375mV specified in the BC1.2 specification and for the maximum V DP_SRC of 0.7V, the voltage as seen by the DCP w ould be 1.075V. Smart DCPs that rely on this voltage detection to determine attach and detach detection need to take this into account. VBUS Tolerance When V BUS rises, an internal Pow er On Reset (POR) detects this voltage and prepares the FSA831 for charger detection. GOOD_BAT has an internal pull-dow n resistor to ensure it is LOW w hen the SoC is pow ered dow n. This input is designed to have very low thresholds to interface w ith low -voltage SoCs driven w ith 1.2V supplies. V BUS voltages up to 28V can be tolerated by the V BUS pin. V BUS can tolerate voltages up to -2V for cases w here a charger is plugged in backw ards. Proprietary Chargers Detection Flow Only legitimate USB chargers that force VDM_SRC (0.6V typical) on DM_CON w hen VDP_SRC is applied to DP_CON are detected by the FSA831 and cause CHG_DET signal to be asserted. Any charger that forces a HIGH on both DP_CON and DM_CON can be detected as CDP, DCP, or The flow diagram in Figure 3 show s how the FSA831 achieves battery charger detection consistent w ith BC1.2. www.onsemi.com 3 Check VBUS Else VBUS>VBUSVLD Start Timer Enable DCD Else D+ < VLGC for tDCD_DBNC OR tDCD_TIMEOUT Primary detection D+ = VDP_SRC, Wait TVDPSRC_ON D- > VDAT_REF AND D- < VLGC • ( D- < VDAT_REF OR D- > VLGC) • • • Secondary Detection D- = VDM_SRC, Wait TVDMSRC_ON D+ > VDAT_REF AND < VLGC • If VBUS VLGC D+ = VDP_SRC DCP IDCP CDP ICDP CHG_AL_N=L, CHG_DET=H SW_OPEN=Hi-Z SDP IUNIT CHG_AL_N=L, CHG_DET=H CHG_AL_N=L, CHG_DET=L GOOD_BAT=H ~tDBP SW_OPEN=L, Remove VDP_SRC on D+ GOOD_BAT=L tDBP ~tDBP SW_OPEN=Hi-Z D+=VDP_SRC GOOD_BAT=H GOOD_BAT=L ~tDBP tDBP SW_OPEN=Hi-Z, CHG_AL_N=Hi-Z, CHG_DET=L, Remove VDP_SRC on D+ Figure 3. Battery Charger Detection www.onsemi.com 5 tDBP Wait for VBUS < VBUSVLD Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit -2 28 V V BUS Voltage from USB Connector V SW USB Sw itch I/O Voltage (DP_CON, DM_CON, DP_HOST, DM_HOST) -0.5 6.0 V ISW USB Sw itch Current (DP_CON to DP_HOST, DM_CON to DM_HOST) -30 +30 mA V I/O Voltage from GOOD_BAT, CHG_AL_N, CHG_DET and SW_OPEN I/Os -0.5 6.0 V V CA Voltage from CHG_AL_N Output -0.5 28.0 V II/O CHG_AL_N, CHG_DET and SW_OPEN Outputs Sink/Source Current -5 +5 mA Storage Temperature Range -65 +150 °C TSTG TJ Maximum Junction Temperature +150 °C TL Lead Temperature (Soldering, 10 Seconds) +260 °C IEC 61000-4-2 System ESD USB Pins (DP_CON, DM_CON, V BUS) Air Gap 15 Contact 8 Human Body Model, JEDEC JESD22-A114 All Pins 6 Charged Device Model, JEDEC JESD22-C101 All Pins 2 kV Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter V BUS V BUS Input HIGH Voltage V SW Sw itch I/O Voltage for USB Path TA Operating Temperature www.onsemi.com 6 Min. Max. Unit 4 6 V 0 3.6 V -40 +85 ºC DC Electrical Characteristics Unless otherw ise indicated, V BUS=4V to 6V and TA=-40 to +85°C. Typical values are at TA=25ºC unless otherw ise specified. Symbol Parameter Condition Min. Typ. Max. Unit Status Outputs V OHCD Output HIGH Voltage (CHG_DET) IOH=-2mA V OL Output LOW Voltage (CHG_DET, CHG_AL_N, SW_OPEN) IOL=2mA tDIFF Skew Betw een Any Output (CHG_DET, CHG_AL_N, SW_OPEN) Sw itching Relative to II/O=±2mA, CHG_AL_N=20kΩ to 5V, SW_OPEN=10kΩ to 1.8V the Other Outputs Sw itching 2.0 V 0.4 V 100 ns 4.0 V V BUS Pin VBUSVLD IBUSIN IVBUSACT tOUT (1) V BUS Valid Detection Threshold 0.8 V BUS Input Leakage V BUS=0V to 0.8V 10 µA V BUS Active Mode Average Current USB Path Active, USB Sw itch Closed After Charger Detection 400 µA Time from V BUS Valid Asserted to CHG_DET, CHG_AL_N and SW_OPEN Outputs Valid DP_CON pulled dow n to GND, 15kΩ, all voltages forced on V BUS, DP_CON, DM_CON and GND simultaneously 250 ms Pow er Off Leakage Current USB Path V BUS=0V, V SW=0V or 3.6V, Figure 5 10 µA High-Speed USB Range Sw itch On (1) Resistance V DP_CON / V DM_CON=0V, 0.4V; ION=8mA; Figure 4; V BUS=4V to 6V 9.0 Ω 0.5 V Sw itch Characteristics IOFF RONUSB 6.5 Control Input V IH Input HIGH Voltage (GOOD_BAT) V IL Input LOW Voltage (GOOD_BAT) 1.1 V MΩ RPD Pull Dow n Resistance (GOOD_BAT) IIN Input Leakage Current (GOOD_BAT) V BUS=5V, GOOD_BAT=0V to 4.4V 1 10 µA IIOFF OFF State Leakage Current (GOOD_BAT) V BUS=0V, GOOD_BAT=0V to 4.4V 10 µA tDBP Dead Battery Provision (DBP) Timer 45 min tGB Time from GOOD_BAT Asserted to SW_OPEN De-Asserted, Sw itches Closed and Meet the RONUSB Specification 30 ms tDB Time from GOOD_BAT De-asserted to SW_OPEN Asserted, Sw itches Opened 65 ms 15 30 Battery Charger Detection Param eters from BC1.2 Specification V DAT_REF Data Detect Voltage V DM_SRC D- Source Voltage V DP_SRC D+ Source Voltage 0.5 0.7 V V LGC Logic Threshold 0.8 2.0 V IDM_SINK D- Sink Current 25 175 µA IDP_SINK D+ Sink Current 25 175 µA IDP_SRC Data Contact Detect Current Source 7 13 µA (2) (2) 0.25 0.40 V 0.5 0.7 V tDCD_DBNC Data Contact Detect Debounce 10 tDCD_TOUT Time for DCD to Timeout 300 ms tVDPSRC_ON D+ Voltage Source On Time 40 ms tVDMSRC_ON D- Voltage Source On Time 40 ms 450 900 ms Notes: 1. Guaranteed by characterization; not production tested. 2. The voltage source, V DP_SRC / V DM_SRC, is able to source at least 250µA w hen the output voltage is in the specified range. This voltage source should not pull DP_CON / DM_CON below 2.2V w hen DP_CON / DM_CON is pulled to a voltage of 3.0V minimum or 3.6V maximum w ith a resistance of 900Ω minimum or 1575Ω maximum. www.onsemi.com 7 AC Electrical Characteristics Unless otherw ise specified, values are at TA=-40 to +85°C; all typical values are for V CC=3.3V at TA=25°C. Symbol Parameter Condition Min. Typ. Max. Unit Figure Xtalk Active Channel Crosstalk, DP_CON to (3) DM_CON f=1MHz, RT=50Ω, CL=0pF -78 f=240MHz, RT=50Ω, CL=0pF -36 Off Isolation Rejection Ratio, DM_HOST to DM_CON, DP_HOST to (3) DP_CON f=1MHz, RT=50Ω, CL=0pF -84 OIRR f=240MHz, RT=50Ω, CL=0pF -34 dB Figure 7 dB Figure 6 Note: 3. Guaranteed by characterization; not production tested. Capacitance Unless otherw ise specified, values are at TA=-40 to +85°C. Symbol COFF CON Parameter Typical Unit Figure (4) V BIAS=0.2V, f=1MHz Condition 3.9 pF Figure 8 (4) V BIAS=0.2V, f=1MHz 7.2 pF Figure 9 DP_CON, DM_CON Off Capacitance DP_CON, DM_CON On Capacitance Note: 4. Guaranteed by characterization; not production tested. www.onsemi.com 8 Test Diagrams VON I A(OFF) NC nBn A nA V IN V IN I ON GND Select V Sel = RON = VON / ION Select GND GND VSel = 0 or Vcc 0 orVcc **Each switch port is tested separately. Figure 4. On Resistance Figure 5. Off Leakage Network Analyzer NC RS Network Analyzer RS VIN VS1, S2, S3 VSel GND GND GND GND RS and RT are functions of the application environment (see AC/DC tables). RT GND VOUT GND GND GND GND RS and RT are functions of the application environment (see AC tables for values). Figure 6. Channel Off Isolation Capacitance Meter nSn VSel = RT GND CROSSTALK = 20 Log (VOUT / VIN ) Figure 7. Active Channel Crosstalk nBn f = 1MHz VOUT RT Off-Isolation = 20 Log (VOUT / VIN ) - Capacitance Meter VS VS GND RT GND 0 or Vcc nBn nSn V Sel = f = 1MHz 0 orV cc nBn nBn Figure 8. Channel Off Capacitance Figure 9. Channel On Capacitance www.onsemi.com 9 Physical Dimensions 0.10 C 2.10 2X A 1.62 B KEEPOUT ZONE, NO TRACES OR VIAS ALLOWED (0.11) 0.56 1.12 1.60 PIN1 IDENT IS 2X LONGER THAN OTHER LINES 0.10 C 2X TOP VIEW (0.35) 10X (0.25) 10X 0.50 RECOMMENDED LAND PATTERN 0.55 MAX 0.05 C 0.05 C 0.05 0.00 (0.20) C 0.35 0.25 SIDE VIEW (0.15) D 0.65 0.55 DETAIL A 0.35 0.25 (0.36) 0.35 0.25 DETAIL A 2X SCALE 4 1 0.56 5 10 (0.29) 0.35 9X 0.25 6 9 0.50 0.25 9X 0.15 1.62 0.10 0.05 C A B C ALL FEATURES BOTTOM VIEW NOTES: A. PACKAGE CONFORMS TO JEDEC REGISTRATION MO-255, VARIATION UABD . B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. D. PRESENCE OF CENTER PAD IS PACKAGE SUPPLIER DEPENDENT. IF PRESENT IT IS NOT INTENDED TO BE SOLDERED AND HAS A BLACK OXIDE FINISH. E. DRAWING FILENAME: MKT-MAC10Arev5. Figure 10. 10-Lead, MicroPak™ Part Number Top Mark Operating Temperature Range Package Description Packing Method FSA831L10X KY -40 to 85°C 10-Lead, MicroPak™ 1.6 x 2.1mm, 0.5mm Pitch Tape & Reel Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a ON Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers ON Semiconductor products. www.onsemi.com 10 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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