FSB127AHN

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ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. FSB127AH mWSaver™ Fairchild Power Switch (FPS™) Features Description mWSaver™ Technology The FSB127AH next-generation, Green-Mode, Fairchild Power Switch (FPS™) incorporates Fairchild’s innovative mWSaver™ technology, which dramatically reduces standby and no-load power consumption, enabling conformance to all worldwide Standby Mode efficiency guidelines. It integrates an advanced currentmode Pulse Width Modulator (PWM) and an avalancherugged 700 V SenseFET in a single package, allowing auxiliary power designs with higher standby energy efficiency, reduced size, improved reliability, and lower system cost than previous solutions.  Achieves Low No-Load Power Consumption: < 40 mW at 230 VAC (EMI Filter Loss Included)  Meets 2013 ErP Standby Power Regulation (< 0.5 W Consumption with 0.25 W Load) for ATX Power and LCD TV Power  Eliminates X-Cap Discharge Resistor Loss with Ax-CAP® Technology  Linearly Decreases Switching Frequency at Light-Load Condition and Advanced Burst Mode Operation at No-Load Condition  700 V High-Voltage JFET Startup Circuit Eliminates Startup Resistor Loss Highly Integrated with Rich Features        Internal Avalanche-Rugged 700 V SenseFET Built-in 5 ms Soft-Start Peak-Current-Mode Control Cycle-by-Cycle Current Limiting Leading-Edge Blanking (LEB) Synchronized Slope Compensation Proprietary Asynchronous Jitter to Reduce EMI Advanced Protection        Internal Overload / Open-Loop Protection (OLP) Fairchild Semiconductor’s mWSaver™ technology offers best-in-class minimum no-load and light-load power consumption. An innovative Ax-CAP® method, one of the five proprietary mWSaver™ technologies, minimizes losses in the EMI filter stage by eliminating the X-Cap discharge resistors while still meeting IEC61010-1 safety requirements. mWSaver™ Green Mode gradually decreases switching frequency as load decreases to minimize switching losses. A new proprietary asynchronous jitter decreases EMI emission. Built-in synchronized slope compensation allows stable peak-current-mode control over a wide range of input voltage. The proprietary internal line compensation ensures constant-output power limit over the entire universal line voltage range. Requiring minimum external components, FSB127AH provides a solid platform for cost-effective flyback converter design with low standby power consumption. VDD Under-Voltage Lockout (UVLO) Applications VDD Over-Voltage Protection (OVP) Constant Power Limit (Full AC Input Range) General-purpose switched-mode power supplies (SMPS) and flyback power converters, including: Internal Auto-Restart Circuit (OLP, VDD OVP, OTP)  Auxiliary Power Supply for PC, Server, LCD TV, and Game Console  SMPS for VCR, SVR, STB, DVD, and DVCD Player, Printer, Facsimile, and Scanner   General Adapter Internal OTP Sensor with Hysteresis Adjustable Peak Current Limit LCD Monitor Power / Open-Frame SMPS Ordering Information Part Number SenseFET Operating Temperature Range Package Packing Method FSB127AHN 2 A 700 V -40°C to +105°C 8-Pin, Dual Inline Package (DIP) Tube © 2013 Fairchild Semiconductor Corporation FSB127AH • Rev. 1.0.0 www.fairchildsemi.com FSB127AH — mWSaver™ Fairchild Power Switch (FPS™) April 2014 Figure 1. Typical Flyback Application Output Power Table (1) Product 230 VAC ±15%(2) (3) Adapter FSB127AH 14 W 85-265 VAC (4) Open-Frame 20 W (3) Adapter 11 W Open-Frame(4) 16 W Notes: 1. The maximum output power can be limited by junction temperature. 2. 230 VAC or 100/115 VAC with voltage doublers. 3. Typical continuous power in a non-ventilated enclosed adapter, with sufficient drain pattern of printed circuit board (PCB) as a heat sink, at 50C ambient. 4. Maximum practical continuous power in an open-frame, design with sufficient drain pattern of printed circuit board (PCB) as a heat sink, at 50C ambient. Block Diagram Figure 2. Internal Block Diagram © 2013 Fairchild Semiconductor Corporation FSB127AH • Rev. 1.0.0 www.fairchildsemi.com 2 FSB127AH — mWSaver™ Fairchild Power Switch (FPS™) Application Diagram F – Fairchild Logo Z – Plant Code X – 1-Digit Year Code Y – 1-Digit Week Code TT – 2-Digit Die Run Code T – Package Type (N: DIP) M – Manufacture Flow Code Figure 3. Pin Configuration Pin Definitions Pin # Name 1 GND Ground. This pin internally connects to the SenseFET source and the signal ground of the PWM controller. 2 VDD Supply Voltage of the IC. Typically the hold-up capacitor connects from this pin to ground. A rectifier diode in series with the transformer auxiliary winding connects to this pin to supply bias during normal operation. 3 FB Feedback. The signal from the external compensation circuit connects to this pin. The PWM duty cycle is determined by comparing the signal on this pin and the internal current-sense signal. 4 IPK Adjust Peak Current. Typically a resistor connects from this pin to the GND pin to program the current-limit level. The internal current source (50 µA) introduces voltage drop across the resistor, which determines the current-limit level of pulse-by-pulse current limit. HV Startup. Typically, resistors in series with diodes from the AC line connect to this pin to supply internal bias and to charge the external capacitor connected between the VDD pin and the GND pin during startup. This pin is also used to sense the line voltage for brownout protection and AC line disconnection detection. 5 Description 6 7 Drain SenseFET Drain. This pin is designed to directly drive the transformer. 8 © 2013 Fairchild Semiconductor Corporation FSB127AH • Rev. 1.0.0 www.fairchildsemi.com 3 FSB127AH — mWSaver™ Fairchild Power Switch (FPS™) Pin Configuration Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDRAIN Parameter Min. (5,6) Drain Pin Voltage (7) Max. Unit 700 V IDM Drain Current Pulsed 8 A EAS Single Pulsed Avalanche Energy(8) 140 mJ VDD DC Supply Voltage 30 V VFB FB Pin Input Voltage -0.3 7.0 V VIPK IPK Pin Input Voltage -0.3 7.0 V VHV HV Pin Input Voltage 700 V PD Power Dissipation (TA＜50°C) 1.5 W TJ Operating Junction Temperature -40 Internally Limited(9) C Storage Temperature Range -55 +150 C +260 C TSTG TL Lead Soldering Temperature (Wave Soldering or IR, 10 Seconds) Electrostatic Discharge Capability, All Pins Except HV Pin ESD Electrostatic Discharge Capability, All Pins Including HV Pin Human Body Model: JESD22-A114 5.50 Charged Device Model: JESD22-C101 2.00 Human Body Model: JESD22-A114 3.00 Charged Device Model: JESD22-C101 1.25 kV Notes: 5. All voltage values, except differential voltages, are given with respect to the network ground terminal. 6. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 7. Non-repetitive rating: pulse width is limited by the maximum junction temperature. 8. L = 51 mH, starting TJ = 25C. 9. Internally limited by Over-Temperature Protection (OTP) (refer to TOTP). Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol RHV Parameter Resistor Connect to HV Pin for Full Range Input Detection Min. Max. Unit 150 250 kΩ Thermal Resistance Table Symbol θJA ψJT Parameter Junction-to-Air Thermal Resistance Junction-to-Package Thermal Resistance (10) Typ. Unit 86 C/W 20 C/W Note: 10. Measured on the package top surface. © 2013 Fairchild Semiconductor Corporation FSB127AH • Rev. 1.0.0 www.fairchildsemi.com 4 FSB127AH — mWSaver™ Fairchild Power Switch (FPS™) Absolute Maximum Ratings VDD=15 V and TA=25C unless otherwise specified. Symbol Parameter SenseFET Section Condition Min. Typ. Max. Unit (11) BVDSS Drain-Source Breakdown Voltage VDS = 700 V, VGS = 0 V 50 IDSS Zero-Gate-Voltage Drain Current VDS = 560 V, VGS = 0 V, TC = 125C 200 Drain-Source On-State Resistance(11) VGS = 10 V, ID = 0.5 A 6.0 7.2 Ω CISS Input Capacitance VGS = 0V , VDS = 25 V, f = 1 MHz 550 715 pF COSS Output Capacitance VGS = 0 V, VDS = 25 V, f = 1 MHz 38 50 pF CRSS Reverse Transfer Capacitance VGS = 0 V, VDS = 25 V, f = 1 MHz 17 26 pF td(on) Turn-On Delay VDS = 350 V, ID = 1.0 A 20 50 ns Rise Time VDS = 350 V, ID = 1.0 A 15 40 ns Turn-Off Delay VDS = 350 V, ID = 1.0 A 55 120 ns Fall Time VDS = 350 V, ID = 1.0 A 25 60 ns 13 V RDS(ON) tr td(off) tf VDS = 700 V, VGS = 0 V 700 V μA Control Section VDD Section VDD-ON UVLO Start Threshold Voltage 11 12 VDD-OFF1 UVLO Stop Threshold Voltage 5 6 7 V VDD-OFF2 IDD-OLP Enable Threshold Voltage 8 9 10 V VDD-OLP VDD Voltage Threshold for HV Startup Turn-On at Protection Mode 5 6 7 V IDD-ST Startup Supply Current VDD-ON – 0.16 V 30 µA IDD-OP1 Operating Supply Current with Normal Switching Operation VDD=15 V, VFB=3 V 3.8 mA IDD-OP2 Operating Supply Current without Switching Operation VDD=15 V, VFB=1 V 1.8 mA VDD-OLP + 0.1 V IDD-OLP Internal Sinking Current 30 60 90 µA VDD-OVP VDD Over-Voltage Protection 27 28 29 V tD-VDDOVP VDD Over-Voltage Protection Debounce Time 70 140 210 µs 5.0 mA 10 µA HV Section IHV Supply Current Drawn from HV Pin IHV-LC Leakage Current after Startup VAC-ON Brown-in Threshold Level (VDC) VAC-OFF Brownout Threshold Level (VDC) tUVP HV=120 VDC, VDD=0 V with 10 µF 1.5 HV=700 V, VDD=VDDV OFF1+1 DC Voltage Applied to HV Pin Through 200 kΩ Resistor Brownout Protection Time 110 114 118 V 93 99 105 V 0.8 1.2 1.6 s Continued on the following page… © 2013 Fairchild Semiconductor Corporation FSB127AH • Rev. 1.0.0 www.fairchildsemi.com 5 FSB127AH — mWSaver™ Fairchild Power Switch (FPS™) Electrical Characteristics VDD=15 V and TA=25C unless otherwise specified. Symbol Parameter Condition Min. Typ. Max. Center Frequency 94 100 106 Hopping Range ±4 ±6 ±8 20 23 Unit Oscillator Section fOSC Frequency in Nominal Mode tHOP Hopping Period(11) fOSC-G 20 Green-Mode Frequency kHz ms 26 kHz fDV Frequency Variation vs. VDD Deviation VDD=11 V to 22 V 5 % fDT Frequency Variation vs. Temperature Deviation(11) TA=-40 to 105°C 5 % Feedback Input Section AV Internal Voltage Dividing Factor of FB Pin(11) ZFB Pull-Up Impedance of FB Pin FB Pin Open 1/4.5 1/4.0 1/3.5 V/V 15 21 27 kΩ VFB-OPEN FB Pin Pull-Up Voltage 5.2 5.4 5.6 V VFB-OLP FB Voltage Threshold to Trigger Open-Loop Protection 4.3 4.6 4.9 V tD-OLP Delay of FB Pin Open-Loop Protection 46 56 66 ms VFB-N FB Voltage Threshold to Exit Green Mode VFB is Rising 2.4 2.6 2.8 V VFB-G FB Voltage Threshold to Enter Green Mode VFB is Falling VFB-ZDC FB Voltage Threshold to Enter ZeroDuty State VFB is Falling VFB-ZDCR FB Voltage Threshold to Exit ZeroDuty State VFB is Rising VFB-N0.2 1.95 2.05 V 2.15 VFB-ZDC +0.1 V V IPK Pin Section VIPK-OPEN IPK Pin Open Voltage 3.0 VIPK-H Internal Upper Clamping Voltage of (11) IPK Pin VIPK-L Internal Lower Clamping Voltage of (11) IPK Pin IPK Internal Current Source of IPK Pin TA=-40 to 105°C, VIPK=2.25 V ILMT-FL-H Flat Threshold Level of Current Limit for the Highest IPK Level VIPK=3 V, Duty>40% ILMT-VA-H Valley Threshold Level of Current Limit for the Highest IPK Level(11) VIPK=3 V, Duty=0% ILMT-FL-L Flat Threshold Level of Current Limit for the Lowest IPK Level VIPK=1.5 V, Duty>40% ILMT-VA-L Valley Threshold Level of Current Limit for the Lowest IPK Level(11) VIPK=1.5 V, Duty=0% 3.5 4.0 V 3 V V 1.5 45 50 55 µA 0.90 1.00 1.10 A ILMT-FL-H -0.25 0.45 0.50 ILMT-FL-L -0.12 A 0.55 A A Continued on the following page… © 2013 Fairchild Semiconductor Corporation FSB127AH • Rev. 1.0.0 www.fairchildsemi.com 6 FSB127AH — mWSaver™ Fairchild Power Switch (FPS™) Electrical Characteristics (Continued) VDD=15 V, TA=25C unless otherwise specified. Symbol Parameter Condition Min. Typ. Max. Unit 100 200 ns 280 330 (12) Current-Sense Section tPD Current Limit Turn-Off Delay tLEB Leading-Edge Blanking Time tSS Soft-Start Time(11) 230 5 ns ms GATE Section(12) DCYMAX Maximum Duty Cycle 70 % Over-Temperature Protection Section (OTP) TOTP Junction Temperature to trigger OTP(11) ∆TOTP (11) Hysteresis of OTP 135 142 25 150 °C °C Notes: 11. Guaranteed by design; not 100% tested in production. 12. Pulse test: pulse width ≤ 300 µs, duty ≤ 2%. 13. These parameters, although guaranteed, are tested in wafer-sort process. © 2013 Fairchild Semiconductor Corporation FSB127AH • Rev. 1.0.0 www.fairchildsemi.com 7 FSB127AH — mWSaver™ Fairchild Power Switch (FPS™) Electrical Characteristics (Continued) Figure 4. VDD-ON vs. Temperature Figure 5. VDD-OFF1 vs. Temperature Figure 6. VDD-OFF2 vs. Temperature Figure 7. VDD-OVP vs. Temperature Figure 8. VDD-LH vs. Temperature Figure 9. Figure 10. VAC-ON vs. Temperature © 2013 Fairchild Semiconductor Corporation FSB127AH • Rev. 1.0.0 IDD-OP1 vs. Temperature Figure 11. VAC-OFF vs. Temperature www.fairchildsemi.com 8 FSB127AH — mWSaver™ Fairchild Power Switch (FPS™) Typical Characteristics Figure 12. VFB-OPEN vs. Temperature Figure 14. ZFB vs. Temperature Figure 16. fOSC vs. Temperature © 2013 Fairchild Semiconductor Corporation FSB127AH • Rev. 1.0.0 Figure 13. VFB-OLP vs. Temperature Figure 15. IPK vs. Temperature Figure 17. fOSC-G vs. Temperature www.fairchildsemi.com 9 FSB127AH — mWSaver™ Fairchild Power Switch (FPS™) Typical Characteristics Startup Operation PWM Control The HV pin is typically connected to the AC line input through two external diodes and one resistor (RHV), as shown in Figure 18. When the AC line voltage is applied, the VDD hold-up capacitor is charged by the line voltage through the diodes and resistor. After VDD voltage reaches the turn-on threshold voltage (VDD-ON), the startup circuit charging the VDD capacitor is switched off and VDD is supplied by the auxiliary winding of the transformer. Once the FSB127AH starts, it continues operation until VDD drops below 6 V (VDD-OFF1). The IC startup time with a given AC line input voltage is: The FSB127AH employs current-mode control, as shown in Figure 19. An opto-coupler (such as the H11A817A) and shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the RSENSE resistor makes it possible to control the switching duty cycle. A synchronized positive slope is added to the SenseFET current information to guarantee stable current-mode control over a wide range of input voltage. The built-in slope compensation stabilizes the current loop and prevents sub-harmonic oscillation. VAC IN  tSTARTUP  RHV  CDD  ln VAC IN  2 2  2 2  6 7 8 5.4V Drain (1) VO ZF  VDD ON 3 FB OSC PWM 3R Comparator Gate Driver KA431 R + RSENSE Primary-Side + SecondarySide Slope Compensation Figure 19. Current Mode Control Figure 18. Startup Circuit Soft-Start Brown-in/out Function The internal soft-start circuit progressively increases the pulse-by-pulse current limit level of MOSFET during startup to establish the correct working conditions for transformers and capacitors, as shown in Figure 20. The current limit levels have nine steps, as shown in Figure 21. This prevents transformer saturation and reduces stress on the secondary diode during startup. The HV pin can detect the AC line voltage using a switched voltage divider that consists of external resistor (RHV) and internal resistor (RLS), as shown in Figure 18. The internal line-sensing circuit detects the real RMS value of the line voltage using a sampling circuit and peak-detection circuit. Because the voltage divider causes power consumption when it is switched on, the switching is driven by a signal with a very narrow pulse width to minimize power loss. The sampling frequency is adaptively changed according to the load condition to minimize power consumption in light-load condition. 6 VBROWN OUT (RMS )  RHV VAC OFF  200k 2 8 5.4V ZF PWM Comparator Drain OSC Based on the detected line voltage, brown-in and brownout thresholds are determined. Since the internal resistor (RLS) of the voltage divider is much smaller than RHV, the thresholds are given as: V R VBROWN IN (RMS )  HV  AC ON 200k 2 7 Gate Driver 3R SS Comparator VSS 3 FB R + VLMT Current Limit Comparator (2) + Slope Compensation RSENSE (3) Figure 20. Soft-Start and Current-Limit Circuit © 2013 Fairchild Semiconductor Corporation FSB127AH • Rev. 1.0.0 www.fairchildsemi.com 10 FSB127AH — mWSaver™ Fairchild Power Switch (FPS™) Functional Description Ax-CAP® Elimination of X-Cap Discharge Resistors The EMI filter in the front end of the switched-mode power supply (SMPS) typically includes a capacitor across the AC line connector, as shown in Figure 24. Most of the safety regulations, such as UL 1950 and IEC61010-1, require the capacitor be discharged to a safe level within a given time after being unplugged from the power outlet. Typically a discharge resistor across the capacitor is used to ensure the capacitor is discharged naturally, which introduces power loss. As power level increases, the EMI filter capacitor tends to increase, requiring a smaller discharge resistor to maintain the same discharge time. This typically results in more power dissipation in high-power applications. The innovative Ax-CAP technology intelligently discharges the filter capacitor only when the power supply is unplugged from the power outlet. Since the Ax® CAP discharge circuit is disabled in normal operation, the power loss in the EMI filter can be virtually removed. Figure 21. Current Limit Variation During Soft-Start Adjustable Peak Current Limit & H/L Line Compensation for Constant Power Limit To make the limited output power constant, regardless of the line voltage condition, a special current-limit profile with sample and hold is used (as shown in Figure 22). The current-limit level is sampled and held at the falling edge of the gate drive signal, as shown in Figure 23. Then, the sampled current-limit level is used for the next switching cycle. The sample-and-hold function prevents sub-harmonic oscillation in currentmode control. The current-limit level increases as the duty cycle increases, which reduces the current limit as duty cycle decreases. This allows a lower current-limit level for high-line voltage condition where the duty cycle is smaller than that of low line. Therefore, the limited maximum output power can remain constant even for a wide input voltage range. The peak current limit is programmable using a resistor on the IPK pin. The internal 50 µA current source for the IPK pin generates voltage drop across the resistor. The voltage of the IPK pin determines the current-limit level. Since the upper and lower clamping voltages of the IPK pin are 3 V and 1.5 V, respectively; the suggested resistor value is from 30 kΩ to 60 kΩ. Figure 24. Ax-CAP® Circuit Green Mode The FSB127AH modulates the PWM frequency as a function of FB voltage, as shown in Figure 25. Since the output power is proportional to the FB voltage in currentmode control, the switching frequency decreases as load decreases. In heavy-load conditions, the switching frequency is 100 kHz. Once VFB decreases below VFB-N (2.6 V), the PWM frequency linearly decreases from 100 kHz to 23 kHz to reduce switching losses at lightload condition. As VFB decreases to VFB-G (2.4 V), the switching frequency is fixed at 23 kHz. As VFB falls below VFB-ZDC (2.1 V), the FSB127AH enters Burst Mode, where PWM switching is disabled. Then the output voltage starts to drop, causing the feedback voltage to rise. Once VFB rises above VFB-ZDCR, switching resumes. Burst Mode alternately enables and disables switching, thereby reducing switching loss to reduce power consumption, as shown in Figure 26. Figure 22. ILMT vs. PWM Turn-On Time Figure 25. Figure 23. Current Limit Variation with Duty Cycle © 2013 Fairchild Semiconductor Corporation FSB127AH • Rev. 1.0.0 PWM Frequency www.fairchildsemi.com 11 FSB127AH — mWSaver™ Fairchild Power Switch (FPS™) mWSaver™ Technology Over-Temperature Protection (OTP) The SenseFET and the control IC are integrated in one package. This makes it easier for the control IC to detect the abnormal over temperature of the SenseFET. If the temperature exceeds approximately 140°C, the OTP is triggered and the MOSFET remains off. When the junction temperature drops by 25°C from OTP temperature, normal operation resumes. Two-Level UVLO Since all the protections are auto-restart, the power supply repeats shutdown and restart until the fault condition is removed. Two-level UVLO is enabled when protection is triggered to delay the re-startup by slowing down VDD discharge. This effectively reduces the input power of the power supply during the fault condition, minimizing the voltage/current stress of the switching devices. Figure 28 shows the normal UVLO operation and two-step UVLO operation. When VDD drops to 6 V without triggering the protection, the PWM stops switching and VDD is charged by the HV startup circuit. Meanwhile, when the protection is triggered, the FSB127AH has a different VDD discharge profile. Once the protection is triggered, the IC stops switching and VDD drops. When VDD drops to 9 V, the operating current becomes very small and VDD is slowly discharged. When VDD is naturally discharged down to 6 V, the protection is reset and VDD is charged by the HV startup circuit. Once VDD reaches 12 V, the IC resumes switching operation. Figure 26. Burst-Mode Operation Protections Protection functions include Overload / Open-Loop Protection (OLP), Over-Voltage Protection (OVP), and Over-Temperature Protection (OTP). All the protections are implemented as Auto-Restart Mode. Once the fault condition is detected, switching is terminated and the SenseFET remains off. This causes VDD to fall. When VDD falls to 6 V, the protection is reset and HV startup circuit charges VDD up to 12 V voltage, allowing restart. Open-Loop / Overload Protection (OLP) Because of the pulse-by-pulse current-limit capability, the maximum peak current through the SenseFET is limited and maximum input power is limited. If the output consumes more than the limited maximum power, the output voltage (VO) drops below the set voltage. Then the current through the opto-coupler LED and the transistor become virtually zero and FB voltage is pulled HIGH, as shown in Figure 27. If feedback voltage is above 4.6 V for longer than 56 ms, OLP is triggered. This protection is also triggered when the feedback loop is open due to a soldering defect. Figure 27. OLP Operation VDD Over-Voltage Protection (OVP) If the secondary-side feedback circuit malfunctions or a solder defect causes an opening in the feedback path, the current through the opto-coupler transistor becomes virtually zero. Then feedback voltage climbs up in a similar manner to the overload situation, forcing the preset maximum current to be supplied to the SMPS until the overload protection triggers. Because more energy than required is provided to the output, the output voltage may exceed the rated voltage before the overload protection triggers, resulting in the breakdown of the devices in the secondary side. To prevent this situation, an OVP circuit is employed. Since VDD voltage is proportional to the output voltage by the transformer © 2013 Fairchild Semiconductor Corporation FSB127AH • Rev. 1.0.0 Figure 28. Normal and Two-Level UVLO www.fairchildsemi.com 12 FSB127AH — mWSaver™ Fairchild Power Switch (FPS™) coupling, the over voltage of output is indirectly detected using VDD voltage. The OVP is triggered when VDD voltage reaches 28 V. Debounce time (typically 150 µs) is applied to prevent false triggering by switching noise. Application Fairchild Device Input Voltage Range Output Standby Auxiliary Power FSB127AH 85 VAC ~ 265 VAC 5 V / 3.2 A Figure 29. Schematic of Typical Application Circuit Transformer Specification   Core: EI 22 Bobbin: EI 22 EI - 22 1 10 N 5V Np/2 2 Np/2 3 6 Na 4 5 Figure 30. Transformer Specification © 2013 Fairchild Semiconductor Corporation FSB127AH • Rev. 1.0.0 www.fairchildsemi.com 13 FSB127AH — mWSaver™ Fairchild Power Switch (FPS™) Typical Application Circuit Pin (S → F) Wire Turns Winding Method 4→5 0.15φ×1 12 Solenoid Winding 31 Solenoid Winding 5 Solenoid Winding 31 Solenoid Winding Pin Specification Remark Primary-Side Inductance 1－3 900 µH ±10% 100 kHz, 1 V Primary-Side Effective Leakage 1－3 < 30 µH Maximum Short All Other Pins Na Insulation: Polyester Tape t = 0.025 mm, 1-Layer Np/2 3→2 0.27φ×1 Insulation: Polyester Tape t = 0.025 mm, 2-Layer N5V 6 → 10 0.55φ×2 Insulation: Polyester Tape t = 0.025 mm, 2-Layer Np/2 2→1 0.27φ×1 Insulation: Polyester Tape t = 0.025 mm, 2-Layer © 2013 Fairchild Semiconductor Corporation FSB127AH • Rev. 1.0.0 www.fairchildsemi.com 14 FSB127AH — mWSaver™ Fairchild Power Switch (FPS™) Typical Application Circuit (Continued) [ 0.400 10.160 0.355 9.017 8 ] 5 [ 0.280 7.112 0.240 6.096 1 HALF LEAD STYLE 4X 0.031 [0.786] MIN MAX 0.210 [5.334] ] 4 FULL LEAD STYLE 4X 0.010 [0.252] MIN 0.195 4.965 0.115 2.933 [ ] [ 0.325 8.263 0.300 7.628 ] SEATING PLANE [ 0.150 3.811 0.115 2.922 ] C MIN 0.015 [0.381] 0.100 [2.540] (0.031 [0.786]) 4X [ ] 0.10 C 0.022 0.562 0.014 0.358 0.300 [7.618] 0.430 [10.922] MAX [ 0.070 1.778 0.045 1.143 FOR 1/2 LEAD STYLE ] 4X 8X FOR FULL LEAD STYLE NOTES: A) THIS PACKAGE CONFORMS TO JEDEC MS-001 VARIATION BA WHICH DEFINES 2 VERSIONS OF THE PACKAGE TERMINAL STYLE WHICH ARE SHOWN HERE. B) CONTROLING DIMS ARE IN INCHES C) DIMENSION S ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSION S AND TOLERANCES PER ASME Y14.5M-2009 E) DRAWING FILENAME AND REVSION: MKT-N08MREV2. 0.015 [0.389] GAGE PLANE PIN 1 INDICATOR ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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