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FSFA2100 — Fairchild Power Switch (FPS™)
for Half-Bridge PWM Converters
Features
Description
The growing demand for higher power density and low
profile in power converter designs has forced designers
to increase switching frequencies. Operation at higher
frequencies considerably reduces the size of passive
components, such as transformers and filters. However,
switching losses have been an obstacle to highfrequency operation. To reduce switching losses and
allow high-frequency operation, Pulse Width Modulation
(PWM) with soft-switching techniques have been
developed. These techniques allow switching devices to
be softly commutated, which dramatically reduces the
switching losses and noise.
Optimized for Complementary Driven Half-Bridge
Soft-Switching Converters
Can be Applied to Various Topologies: Asymmetric
PWM Half-Bridge Converters, Asymmetric PWM
Flyback Converters, Asymmetric PWM Forward
Converters, Active Clamp Flyback Converters
High Efficiency through Zero-Voltage-Switching (ZVS)
Internal SuperFET™s with Fast-Recovery Type
Body Diode (trr=120 ns)
Fixed Dead Time (200 ns) Optimized for MOSFETs
Up to 300 kHz Operating Frequency
Internal Soft-Start
Pulse-by-Pulse Current Limit
Burst-Mode Operation for Low Standby Power
Consumption
Protection Functions: Over-Voltage Protection
(OVP), Over-Load Protection (OLP), Abnormal OverCurrent Protection (AOCP), Internal Thermal
Shutdown (TSD)
Applications
FSFA2100 is an integrated PWM controller and
SuperFET™ specifically designed for Zero-VoltageSwitching (ZVS) half-bridge converters with minimal
external components. The internal controller includes an
oscillator, under-voltage-lockout, leading-edge blanking
(LEB), optimized high-side and low-side gate driver,
internal soft-start, temperature-compensated precise
current sources for loop compensation and selfprotection circuitry. Compared with discrete MOSFET
and PWM controller solution, FSFA2100 can reduce total
cost; component count, size, and weight; while
simultaneously increasing efficiency, productivity, and
system reliability.
PDP and LCD TVs
Desktop PCs and Servers
Adapters
Telecom Power Supplies
Ordering Information
Part
Number
Operating
Junction
Temperature
RDS(ON_MAX)
Maximum Output
Power without
Heatsink
(VIN=350~400 V)(1,2)
FSFA2100
-40 to +130°C
0.38 Ω
200 W
Maximum Output Power
with Heatsink
Package
(VIN=350~400 V)(1,2)
450 W
9-SIP
Notes:
1. The junction temperature can limit the maximum output power.
2. Maximum practical continuous power in an open-frame design at 50°C ambient.
For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2008 Fairchild Semiconductor Corporation
FSFA2100 • Rev. 1.0.1
www.fairchildsemi.com
FSFA2100 — Fairchild Power Switch (FPS™) for Half-Bridge PWM Converter
February 2013
D1
CB
Llk
LVcc
VCC
HVcc
RT
VFB
CDL
Np
VO
Ns
VDL
Lm
Ns
Control
IC
D2
CF RF
VCTR
VIN
KA431
CS
SG
PG
Rsense
Figure 1. Typical Application Circuit for an Asymmetric PWM Half-Bridge Converter
CB
D1
Llk
VDL
LVcc
VCC
HVcc
RT
CDL
VFB
Np
Lm
VO
Ns
Control
IC
VCTR
VIN
CS
CF RF
SG
PG
KA431
Rsense
Figure 2. Typical Application Circuit for an Asymmetric PWM Flyback Converter
© 2008 Fairchild Semiconductor Corporation
FSFA2100 • Rev. 1.0.1
www.fairchildsemi.com
2
FSFA2100 — Fairchild Power Switch (FPS™) for Half-Bridge PWM Converter
Application Circuit Diagram
FSFA2100 — Fairchild Power Switch (FPS™) for Half-Bridge PWM Converter
Block Diagram
Figure 3. Internal Block Diagram
© 2008 Fairchild Semiconductor Corporation
FSFA2100 • Rev. 1.0.1
www.fairchildsemi.com
3
1
VDL
2
VFB
3 4 5 6 7 8
9
SG LVcc
CS PG
HVcc
RT
10
VCTR
Figure 4. Package Diagram
Pin Definitions
Pin #
Name
Description
1
VDL
This is the drain of the high-side MOSFET, typically connected to the input DC link voltage.
2
VFB
This pin is connected to the inverting input of the PWM comparator internally and to the optocoupler externally. The duty cycle is determined by the voltage on this pin.
3
RT
This pin programs the switching frequency using a resistor.
4
CS
This pin senses the current flowing through the low-side MOSFET. Typically, negative
voltage is applied on this pin.
5
SG
This pin is the control ground.
6
PG
This pin is the power ground. This pin is connected to the source of the low-side MOSFET.
7
LVCC
8
NC
9
HVCC
This is the supply voltage of the high-side gate-drive circuit IC.
10
VCTR
This is the drain of the low-side MOSFET. Typically, a transformer is connected to this pin.
This pin is the supply voltage of the control IC.
No connection.
© 2008 Fairchild Semiconductor Corporation
FSFA2100 • Rev. 1.0.1
www.fairchildsemi.com
4
FSFA2100 — Fairchild Power Switch (FPS™) for Half-Bridge PWM Converter
Pin Configuration
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In
addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. TA=25°C unless otherwise specified.
Symbol
Parameter
Min.
VDS
Maximum Drain-to-Source Voltage (VDL-VCTR and VCTR-PG)
600
LVCC
Low-Side Supply Voltage
-0.3
HVCC to VCTR High-Side VCC Pin to Low-Side Drain Voltage
Max.
Unit
V
25.0
V
-0.3
25.0
V
High-Side Floating Supply Voltage
-0.3
625.0
V
Feedback Pin Input Voltage
-0.3
LVCC
V
VCS
Current Sense (CS) Pin Input Voltage
-5.0
1.0
V
VRT
RT Pin Input Voltage
-0.3
5.0
V
50
V/ns
12.0
W
HVCC
VFB
dVCTR/dt
PD
Allowable Low-Side MOSFET Drain Voltage Slew Rate
(3)
Total Power Dissipation
(4)
TJ
TSTG
Maximum Junction Temperature
+150
Recommended Operating Junction Temperature(4)
-40
+130
Storage Temperature Range
-55
+150
°C
°C
MOSFET Section
VDGR
Drain Gate Voltage (RGS=1MΩ)
VGS
Gate Source (GND) Voltage
600
±30
V
V
IDM
Drain Current Pulsed
33
A
ID
Continuous Drain Current
TC=25°C
11
TC=100°C
7
A
Package Section
Torque
Recommended Screw Torque
5~7
kgf·cm
Notes:
3. Per MOSFET when both MOSFETs are conducting.
4. The maximum value of the recommended operating junction temperature is limited by thermal shutdown.
Thermal Impedance
TA=25°C unless otherwise specified.
Symbol
Parameter
θJC
Junction-to-Case Center Thermal Impedance (Both MOSFETs Conducting)
θJA
Junction-to-Ambient Thermal Impedance
© 2008 Fairchild Semiconductor Corporation
FSFA2100 • Rev. 1.0.1
Value
Unit
10.44
ºC/W
80
ºC/W
www.fairchildsemi.com
5
FSFA2100 — Fairchild Power Switch (FPS™) for Half-Bridge PWM Converter
Absolute Maximum Ratings
TA=25°C and LVCC=17 V unless otherwise specified.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
MOSFET Section
BVDSS
Drain-to-Source Breakdown Voltage
RDS(ON)
trr
ID=200 μA, TA=25°C
600
V
ID=200 μA, TA=125°C
650
On-State Resistance
VGS=10 V, ID=5.5 A
0.32
Body Diode Reverse Recovery Time(5)
VGS=0 V, IDiode=11.0 A,
dIDiode/dt=100 A/μs
120
ns
1148
pF
671
pF
CISS
Input Capacitance(5)
COSS
Output Capacitance(5)
VDS=25 V, VGS=0 V,
f=1.0 MHz
0.38
Ω
Supply Section
ILK
Offset Supply Leakage Current
HVCC=VCTR=600 V
IQHVCC
Quiescent HVCC Supply Current
(HVCCUV+) - 0.1 V
IQLVCC
Quiescent LVCC Supply Current
(LVCCUV+) - 0.1 V
IOHVCC
Operating HVCC Supply Current
(RMS Value)
IOLVCC
Operating LVCC Supply Current
(RMS Value)
50
μA
50
120
μA
100
200
μA
6
9
mA
100
200
μA
fOSC=100 KHz, VFB > 3 V
7
11
mA
No Switching, VFB < 1 V
2
4
mA
fOSC=100 KHz, VFB > 3 V
HVCC=17 V
No switching, VFB < 1V
HVCC=17 V
UVLO Section
LVCCUV+
LVCC Supply Under-Voltage Positive Going Threshold (LVCC Start)
13.0
14.5
16.0
V
LVCCUV-
LVCC Supply Under-Voltage Negative Going Threshold (LVCC Stop)
10.2
11.3
12.4
V
LVCCUVH
LVCC Supply Under-Voltage Hysteresis
HVCCUV+
HVCC Supply Under-Voltage Positive Going Threshold (HVCC Start)
8.2
9.2
10.2
V
HVCCUV-
HVCC Supply Under-Voltage Negative Going Threshold (HVCC Stop)
7.8
8.7
9.6
V
HVCCUVH
HVCC Supply Under-Voltage Hysteresis
3.2
V
0.5
V
Oscillator and Feedback Section
VRT
V-I Converter Threshold Voltage
1.5
2.0
2.5
V
fOSC
Output Oscillation Frequency
RT=27 KΩ
94
100
106
KHz
DMAX
Maximum Duty Cycle
VFB=4 V
45
50
55
%
DMIN
Minimum Duty Cycle
VFB=0 V
0
%
Maximum Feedback Voltage for DMAX
DMAX ≥ 48%
2.7
3.0
3.3
V
IFB
Feedback Source Current
VFB=0 V
370
470
570
μA
VBH
Burst Mode High-Threshold Voltage
1.34
1.50
1.66
V
VBL
Burst Mode Low-Threshold Voltage
1.16
1.30
1.44
V
VBHY
Burst Mode Hysteresis Voltage
0.1
0.2
0.3
V
10
15
20
ms
VFB
MAX
tSS
Internal Soft-Start Time
fOSC=100 kHz
Continued on the following page…
© 2008 Fairchild Semiconductor Corporation
FSFA2100 • Rev. 1.0.1
www.fairchildsemi.com
6
FSFA2100 — Fairchild Power Switch (FPS™) for Half-Bridge PWM Converter
Electrical Characteristics
TA=25°C and LVCC=17 V unless otherwise specified.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Protection Section
IOLP
OLP Delay Current
VFB=5 V
3.8
5.0
6.2
μA
VOLP
OLP Protection Voltage
VFB > 6 V
6.3
7.0
7.7
V
VOVP
LVCC Over-Voltage Protection
LVCC > 21 V
21
23
25
V
VAOCP
AOCP Threshold Voltage
ΔV/Δt=-1 V/µs
-1.0
-0.9
-0.8
V
tBAO
AOCP Blanking Time(5)
VCS < VAOCP;
ΔV/Δt=-1 V/µs
50
tDA
Delay Time (Low-Side) from VAOCP to Switch Off(5)
ΔV/Δt=-1 V/µs
250
400
ns
VLIM
Pulse-by-Pulse Current Limit Threshold Voltage
ΔV/Δt=-0.1 V/µs
-0.58
-0.52
V
tBL
Pulse-by-Pulse Current Limit Blanking Time
VCS < VLIM;
ΔV/Δt=-0.1 V/µs
150
ns
tDL
Delay Time (Low-Side) from VLIM to Switch Off(5)
ΔV/Δt=-0.1 V/µs
450
ns
(5)
TSD
Thermal Shutdown Temperature
ISU
Protection Latch Sustain LVCC Supply Current
VPRSET
-0.64
110
LVCC=7.5 V
Protection Latch Reset LVCC Supply Voltage
ns
130
150
°C
100
150
μA
5
V
Dead-Time Control Section
DT
Dead Time(6)
200
ns
Notes:
5. This parameter, although guaranteed, is not tested in production.
6. These parameters, although guaranteed, are tested only in EDS (wafer test) process.
© 2008 Fairchild Semiconductor Corporation
FSFA2100 • Rev. 1.0.1
www.fairchildsemi.com
7
FSFA2100 — Fairchild Power Switch (FPS™) for Half-Bridge PWM Converter
Electrical Characteristics (Continued)
1.1
1.1
1.05
1.05
Normalized at 25℃
Normalized at 25℃
These characteristic graphs are normalized at TA=25°C.
1
0.95
1
0.95
0.9
0.9
-40
-20
0
25
50
75
-40
100
-20
0
50
75
100
Figure 6. Switching Frequency vs. Temperature
1.1
1.1
1.05
1.05
Normalized at 25℃
Normalized at 25℃
Figure 5. Maximum Duty Cycle vs. Temperature
1
0.95
1
0.95
0.9
0.9
-40
-20
0
25
50
75
-40
100
-20
0
25
50
75
100
Temp (℃)
Temp (℃)
Figure 7. High-Side VCC (HVCC) Start vs. Temperature
Figure 8. High-Side VCC (HVCC) Stop vs. Temperature
1.1
1.1
1.05
1.05
Normalized at 25℃
Normalized at 25℃
25
Temp (℃)
Temp (℃)
1
0.95
1
0.95
0.9
0.9
-40
-20
0
25
50
75
-40
100
Figure 9. Low-Side VCC (LVCC) Start vs. Temperature
© 2008 Fairchild Semiconductor Corporation
FSFA2100 • Rev. 1.0.1
-20
0
25
50
75
100
Temp (℃)
Temp (℃)
Figure 10. Low-Side VCC (LVCC) Stop vs. Temperature
www.fairchildsemi.com
8
FSFA2100 — Fairchild Power Switch (FPS™) for Half-Bridge PWM Converter
Typical Performance Characteristics
1.1
1.1
1.05
1.05
Normalized at 25℃
Normalized at 25℃
These characteristic graphs are normalized at TA=25ºC.
1
0.95
1
0.95
0.9
0.9
-40
-20
0
25
50
75
-40
100
-20
0
50
75
100
Figure 12. OLP Voltage vs. Temperature
1.1
1.1
1.05
1.05
Normalized at 25℃
Normalized at 25℃
Figure 11. OLP Delay Current vs. Temperature
1
0.95
1
0.95
0.9
0.9
-40
-20
0
25
50
75
-40
100
-20
0
25
50
75
100
Temp (℃)
Temp (℃)
Figure 13. LVCC OVP Voltage vs. Temperature
Figure 14. RT Voltage vs. Temperature
1.1
1.1
1.05
1.05
Normalized at 25℃
Normalized at 25℃
25
Temp (℃)
Temp (℃)
1
0.95
1
0.95
0.9
0.9
-40
-20
0
25
50
75
-40
100
Figure 15. VBH Voltage vs. Temperature
© 2008 Fairchild Semiconductor Corporation
FSFA2100 • Rev. 1.0.1
-20
0
25
50
75
100
Temp (℃)
Temp (℃)
Figure 16. VLIM Voltage vs. Temperature
www.fairchildsemi.com
9
FSFA2100 — Fairchild Power Switch (FPS™) for Half-Bridge PWM Converter
Typical Performance Characteristics (Continued)
1. Internal Oscillator: FSFA2100 employs a currentcontrolled oscillator as shown in Figure 17. Internally, the
voltage of the RT pin is regulated at 2 V and the
charging/discharging current for the oscillator capacitor
CT is determined by the current flowing out of the RT pin
(ICTC). When the RT pin is pulled down to the ground with
a resistor RSET, the switching frequency is fixed as:
fS =
27kΩ
× 100(kHz)
RSET
(1)
ICTC
VREF
+
3V
ICTC
2ICTC
+
-
RSET RT
1V
Q
-Q
+
CT
2V
S
R
-
F/F
Figure 19. Internal PWM Block Diagram
-
3
3. Protection Circuits: The FSFA2100 has Overload
Protection (OLP), Abnormal Over-Current Protection
(AOCP), Over-Voltage Protection (OVP), and Thermal
Shutdown (TSD) self-protective functions. The OLP and
OVP are auto-restart mode protections, while the AOCP
and TSD are latch-mode protections, as shown in Figure
20.
Figure 17. Current Controlled Oscillator
2. PWM Control: Figure 18 shows the typical control
circuit configuration. The opto-coupler transistor should
be connected to the VFB pin in parallel with the feedback
capacitor to control the duty cycle.
Auto-restart mode protection: Once the fault condition is
detected, the switching is terminated and the MOSFETs
remain off. When LVCC falls down to LVCC stop voltage of
around 11V, the protection is reset. The FPS resumes
normal operation when LVCC reaches the start voltage of
about 14 V.
Latch-mode protection: Once this protection is triggered,
the switching is terminated and the MOSFETs remain off.
The latch is reset only when LVCC is discharged below
5 V.
LVcc
7
+
11.3 / 14.5V
LVcc good
VREF
Internal Bias
-
Shutdown
Auto-restart
protection
OLP
S
OVP
Figure 18. PWM Control Configuration
LVcc good
VFB
R
Q
-Q
F/F
Latch
protection
Q
S
-Q
R
AOCP
TSD
F/F
LVcc < 5V
Figure 19 shows the internal block diagram for PWM
operation. Duty cycle is controlled by comparing the
feedback voltage to the triangular signal with a range
from 1 V to 3 V.
© 2008 Fairchild Semiconductor Corporation
FSFA2100 • Rev. 1.0.1
Figure 20. Protection blocks
Low-side MOSFET current should be sensed for Pulseby-pulse current limit and AOCP. The FSFA2100 senses
drain current as a negative voltage, as shown in Figure
21 and Figure 22. Half-wave sensing allows low-power
dissipation in the sensing resistor, while full-wave sensing
has less noise in the sensing signal.
www.fairchildsemi.com
10
FSFA2100 — Fairchild Power Switch (FPS™) for Half-Bridge PWM Converter
Functional Description
Figure 21. Half-Wave Sensing
t delay =
(7V - 3V ) × C B
5 μA
(2)
I ds
A 30 ~ 50ms delay time is typical for most applications.
VO
V CS
Overload protection
7V
CB
Control
IC
V CS
Np
CS
PG
SG
Rsense
VFB
Ns
Vc
3V
Ns
Ids
tdelay
Figure 22. Full-Wave Sensing
Ids
3.1 Pulse-by-Pulse Current Limit: In normal operation,
the duty cycle of the low-side MOSFET is determined by
comparing the internal triangular signal with the feedback
voltage. However, the low-side MOSFET is forced to turn
off when the current sense pin voltage reaches -0.58 V.
This operation limits the drain current below a predetermined level to avoid the destruction of the
MOSFETs.
t2
ILIM
t
Figure 23. Overload Protection
3.4 Over-Voltage Protection (OVP): When the LVCC
reaches 23V, OVP is triggered. This protection is enabled
when using an auxiliary winding of the transformer to
supply LVCC to FPS.
3.2 Abnormal Over-Current Protection (AOCP): If one
of the secondary rectifier diodes is short-circuited, large
current with extremely high di/dt can flow through the
MOSFET before OCP or OLP is triggered. AOCP is
triggered with a very short shutdown delay time when the
sensed voltage drops below -0.9 V. This protection is
latch mode and reset only when LVCC is pulled below 5 V.
3.5 Thermal Shutdown (TSD): The MOSFETs and the
control IC are built in one package. This allows the
control IC to detect the abnormal over-temperature of the
MOSFET. If the temperature exceeds approximately
130°C, the thermal shutdown triggers.
4. Soft-Start: At startup, the duty cycle starts increasing
slowly to establish the correct working conditions for
transformers, inductors, and capacitors. The voltage on
the output capacitors is progressively increased to
smoothly establish the required output voltage. Soft-start
time is internally implemented for 15 ms (when the
operating frequency is set to 100 kHz.) In addition, to
help the soft-start operation, a capacitor and a resistor
would be connected on the RT pin externally, as shown in
Figure 24. Before the power supply is powered on, the
3.3 Overload Protection (OLP): Overload is defined as
the load current exceeding its nominal level due to an
unexpected abnormal event. In this situation, a protection
circuit should trigger to protect the power supply.
However, even when the power supply is in the normal
condition, the OLP circuit can be triggered during the
load transition. To avoid this undesired operation, the
OLP circuit is designed to trigger only after a specified
time to determine whether it is a transient situation or a
© 2008 Fairchild Semiconductor Corporation
FSFA2100 • Rev. 1.0.1
t1
www.fairchildsemi.com
11
FSFA2100 — Fairchild Power Switch (FPS™) for Half-Bridge PWM Converter
true overload situation. Because of the pulse-by-pulse
current limit capability, the maximum peak current
through the MOSFET is limited; and, therefore, the
maximum input power is restricted with a given input
voltage. If the output consumes more than this maximum
power, the output voltage (VO) decreases below the
nominal voltage. This reduces the current through the
opto-coupler diode, which also reduces the opto-coupler
transistor current, increasing the feedback voltage (VFB).
If VFB exceeds 3V, D1, which is illustrated in Figure 19, is
blocked and the OLP current source starts to charge CB
slowly, as shown in Figure 23. In this condition, VFB
continues increasing until it reaches 7V, then the
switching operation is terminated, as shown in Figure 23.
The delay time for shutdown is the time required to
charge CB from 3V to 7V with 5µA, as given by:
For the high-side MOSFET, a long duty cycle and high
applied voltage make an excessive primary current.
When the high-side MOSFET turns off, the primary
current flows back to the DC link capacitor through the
body diode of the low-side MOSFET. It keeps the same
status even after turning on and off the low-side
MOSFET. When the high-side MOSFET turns on again,
a huge current can flow from the DC link capacitor
through the channel of the high-side MOSFET and body
diode of the low-side one due to the reverse recovery. It
may induce unexpected noise into CS pin.
During the charging time of CSS, the operating frequency
is higher than during normal operation. In asymmetric
half-bridge converters, a switching period contains
powering and commutation periods. The energy cannot
be transferred to the output side during commutation
period. Since the DC link voltage applied to the VDL pin
and the leakage inductance of the main transformer are
fixed, the powering period over the switching period is
shorter in high switching frequencies. As CSS is charged,
the switching frequency decreases and the powering
period over the switching period increases as well. It is
helpful to start SMPS softly with the internal soft-start
time together.
To avoid this issue, the voltage across the DC blocking
capacitor must be low enough. In general, two resistors
with several MHz can be added on the drain-to-source
terminals of each MOSFET to divide the DC link voltage.
6. Burst Operation: To minimize power dissipation in
standby mode, the FSFA2100 enters burst-mode
operation. As the load decreases, the feedback voltage
decreases. As shown in Figure 25, the device
automatically enters burst mode when the feedback
voltage drops below VBL (1.3 V). At this point, switching
stops and the output voltages start to drop at a rate
dependent on standby current load. This causes the
feedback voltage to rise. Once it passes VBH (1.5 V),
switching resumes. The feedback voltage then falls and
the process repeats. Burst-mode operation alternately
enables and disables switching of the MOSFETs, thereby
reducing switching loss in standby mode.
VO
Voset
VFB
1.5V
1.3V
Ids
Figure 24. External Soft-Start Circuit
5. Startup: Due to the imbalance of the turn-off
resistance between the high- and low-side MOSFETs,
the voltage across the DC blocking capacitor cannot be
predicted at startup. Additionally, the high-side MOSFET
starts with a large duty cycle since the duty cycle of the
low-side MOSFET increases step-by-step during softstart time. Therefore, in the case where high voltage is
already charged in the DC blocking capacitor due to the
higher turn-off resistance of the high-side MOSFET
before startup, a large primary current could flow through
the high-side MOSFET during turn-on time after startup.
© 2008 Fairchild Semiconductor Corporation
FSFA2100 • Rev. 1.0.1
Vds
t
t1
Switching
stop
t2
t3
Switching
stop
t4
Figure 25. Burst-Mode Operation
www.fairchildsemi.com
12
FSFA2100 — Fairchild Power Switch (FPS™) for Half-Bridge PWM Converter
capacitor CSS remains fully discharged. After power-on,
CSS becomes charged progressively by the current
through the RT pin, which determines the operating
frequency. The current through the RT pin is inversely
proportional to the total impedance of the connected
resistors. The total impedance at startup is lower than
that of the normal operation because RSS is added on
RSET in parallel, which means the operating frequency
decreases continuously from higher to nominal.
Eventually CSS is fully charged to the RT pin voltage and
the operating frequency is determined by RSET only.
Application
FPS™ Device
Input Voltage Range
Rated Output Power
Output Voltage
(Rated Current)
LCD TV
FSFA2100
400 V
200 W
25 V-8 A
Features
High Efficiency ( >93% at 400 VIN input)
Reduced EMI Noise through Zero-Voltage-Switching (ZVS)
Enhanced System Reliability with Various Protection Functions
Internal Soft-Start (15 ms)
R211
75
C102
220nF/
270VAC
VCC
JP1
10
R106
27
LVcc
C105
22µF/
50V
VIN=400V
(from PFC
output)
C201
2200µF
35V
Ns
D101
1N4137
D211
FFPF20UP20DN
C202
2200µF
35V
L1
27µF
VO
VDL
HVcc
R107
15k
C107
0.68µF
Np
C211
560pF/1kV
D212
FYP2010DN
RT
R105
27k
C106
100nF
FB
Control
IC
R202
1k
N
s
C204
12nF
R201
10k
R204
62k
R206
2k
VCTR
C101
220µF/
450V
C104
68nF
R212
150
CS
C212
680pF/1kV
C203
27nF
R203
33k
U3
KA431
R102
1k
C102
100pF
SG
PG
R205
7k
R101
0.2
Figure 26. Typical Application Circuit
© 2008 Fairchild Semiconductor Corporation
FSFA2100 • Rev. 1.0.1
www.fairchildsemi.com
13
FSFA2100 — Fairchild Power Switch (FPS™) for Half-Bridge PWM Converter
Typical Application Circuit (Asymmetric PWM Half-Bridge Converter)
Core: EER3542 (Ae=107 mm2)
Bobbin: EER3542 (Horizontal)
EER3542
1
16
Np
Ns1
1
3
1
2
Ns2
8
9
Figure 27. Core and Winding
Pin (S → F)
Wire
Turns
Winding Method
Np
8→1
0.12φ×30 (Litz Wire)
50
Solenoid Winding
Ns1
16 → 13
0.1φ×100 (Litz Wire)
8
Solenoid Winding
Ns2
12 → 9
0.1φ×100 (Litz Wire)
8
Solenoid Winding
Pin
Specification
Remark
Inductance
1－8
630 μH ± 5%
100 kHz, 1 V
Leakage
1－8
45 μH ± 10%
Short One of the Secondary Windings
© 2008 Fairchild Semiconductor Corporation
FSFA2100 • Rev. 1.0.1
www.fairchildsemi.com
14
FSFA2100 — Fairchild Power Switch (FPS™) for Half-Bridge PWM Converter
Typical Application Circuit (Continued)
26.20
25.80
3.40
3.00
23.10
22.90
1.20
R0.50 (4X)
10.70
10.30
5.35
5.15
12.00
14.50
13.50
18.50
17.50
0.70
3.20
R0.55
R0.55
8.00 1.30 MAX
7.00
5.08
0.80 MAX
1
2,4,6,8
9
0.70
0.50
2.54
1.27 (5X)
15.24
0.60
0.40
3.48
2.88
FRONT VIEW
RIGHT SIDE VIEW
3.40
3.00
R0.50
BOTTOM VIEW
NOTES: UNLESS OTHERWISE SPECIFIED
A. THIS PACKAGE DOES NOT COMPLY TO
ANY CURRENT PACKAGING STANDARD.
B. ALL DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH AND TIE BAR PROTRUSIONS.
D. DRAWING FILE NAME: MOD09ACREV3
1,3,5,7,9
1.40
1.00
2.54
3.81
1.50
6.00
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