FSL4110LRN

DATA SHEET www.onsemi.cn 1000VSenseFET集电源 FSL4110LR PDIP−7 (PDIP−8 LESS PIN 6) (7−DIP) CASE 626A 述 FSL4110LR是成式宽制 (PWM)控制器和 1000 V崩 用 SenseFET，用外最少的 电压离线式开关 模式电源 (SMPS)。VCC可无 助 压绕组的成式 压电 源器 电。 成式 PWM控制器包括固定率振器、欠压定 (UVLO)、 前沿消 (LEB)、化的栅极动器、内启动、用环  的温度 精密电流源和各种护电。 分立式 MOSFET和 PWM控制器决方案相比，FSL4110L R可在总成本、数、PCB尺寸及的同时提 效 率、生率和系统可性。器提 基本的平台， 合 性比的反激式 换器。 特 •内!崩用 1000 V SenseFET •精确的固定工率：50 kHz •VCC 可#用 压绕组或$应 ! 电 •%歇模式操可最大程度& 噪& •电磁干扰小的'机率波动 •(冲)流 •各种护功*：+护 (OLP)、压护 (OVP)、异常流 护 (AOCP)、带滞回功*的内热关断 (TSD)。带滞回功*的欠 压定 (UVLO) 和线压护 (LOVP)。 •内!内启动和启动电 •对所有护功*的安$动启模式，固定启时% 1.6 s • These are Pb−Free Devices PDIP7 MINUS PIN 6 GW (7−LSOP) CASE 707AA MARKING DIAGRAM $Y&Z&2&K L4110LR FSL4110LRN $Y &Z &2 &K L4110LR $Y&Z&2&K L4110LR FSL4110LRLX = Logo = Assembly Plant Code = 2−Digit Date Code = 2−Digits Lot Run Traceability Code = Specific Device Code ORDERING INFORMATION See detailed ordering and shipping information on page 13 of this data sheet. 用 •用电*的 SMPS •用 3 相 工系统的 助电源 © Semiconductor Components Industries, LLC, 2014 April, 2022 − Rev. 2 1 Publication Order Number: FSL4110LRCN/D FSL4110LR 用电路 VOUT RSTR ( 1) VSTR R1 FSL4110LR VIN Drain PWM GND R2 FB RDLY ( 2) VCC CFB CVCC : 1. RSTR：  。 2. RDLY：  (OLP)。  1. 用电路 部框 VCC 2 Internal Bias VCC Good − VCC VSTART VREF /V STOP Soft Burst + OSC Random VREF S Q IFB R DLY FB 3R 3 Soft− Start R Line Comp. C FB + VIN 4 + VINH Drain 6, 7 HVREG + − VBURH /VBURL VSTR 5 VOLP − − − + PWM Gate Driver R Q LEB R SENSE 100 ms Delay 1.6 s Auto Restart Timing Control 1 GND + − − VAOCP VCC VOVP + TSD −  2. 部框 www.onsemi.cn 2 FSL4110LR 脚配置 7 Drain VCC 2 FB 3 FSL4110LR GND 1 6 Drain VIN 4 5 VSTR  3. 脚配置 (视) 脚 脚 称 述 1 GND 。 PWM    SenseFET 。 2 VCC  。 !"#，%&'() *+。  ,-.  /!" 5 (VSTR)) (0 2)。12  10 V3，45 。6,789:;!" !" 1 (GND)?@A。BCDEF 3 mm。 3 FB GH。;!"IJ PWMKLGM。;!"+ 100ĂmA。NOP/Q IJ;!"。R,;!" GNDA。R,;!"!" 2 (VCC)TP最大漏电流流动，直到G发+护。由 向 出端提 比所2*更多的*，在G发 +护>前， 出电压可*就=出U定电压，$> 导A次级端器击穿。V止B种情况，#用OVP 电。常，VCC 出电压成正比，并FSL4110LR#用VCC，>)是直接监控 出电压。如果 VCC=24.5V，则G发OVP电，导A开关操终 止。H5在正常工期%I然激活OVP，VCC 应在正常情况 24.5V。内OVP电如 图 24 所示。 t  25. LOVP 波E Rectified Line Input (VDC ) Drain 6, 7 VREF OSC IFB 3R FB 3 D1 D2 R1 PWM R Line Comp. VIN LEB S Q R Q Gate Driver LOVP 4 LOVP R2 CVIN RSENSE 1 GND VINH Drain 6, 7 VREF LOVP Disappear LOVP Occurrence  26. LOVP 电路 OSC IFB 3R FB 3 D1 D2 PWM R Line Comp. LEB S Q R Q 方程式 (4) 算 压电平 RMS %。 Gate Driver R2 + OVP RSENSE VCC 2 R1 V DC * V INH (eq. 4) 可根据2I整分压电4的4%。\+情况 ，: 小的4%(导A相对:大的待机功3。H5B种 情况，推L用几 MW的电4器。持稳定0 1，用4%几 MW的电4器时，应同时在 VIN 引 . 和 GND > % , 接   容 %  几 百 pF  的 电 容 (CVIN)。 OVP 1 GND VOVP V INH  24. OVP 电路 热关断 (TSD) SenseFET 和控制 IC 成在同封W方K检测 SenseFET的温度。当结温= 140°C时，将激活热关 断。当温度在 tRESTART (1.6 s) 内- 60°C 时，将启 FSL4110LR。 F荡,模C 振器率在内!，- FSL4110LR具有'机 率波动功*，如图 27所示。开关率的波动将*分 布在比 EMI测]备测得的带宽更宽的率^围内， 因 > * 够 减 少 EMI 。  率 变 化 ^ 围 在 内  固 定 ； 然>，率^围的_择由外反7电压和内$激振 器共同'机决定。'机_择的开关率将 EMI噪声 有效地分布在开关率`a，并Nb用具有成本效 益的电感器，>)是0流 电源滤波器，来满N 球 EMII求。 线路过压保护 (LOVP) 如果线 电压增加 ， 线 电压在整 系统.生 压应力。护 SMPS)发生B种异 常情况，包括 LOVP功*。包括#用分压电4检测 VIN 电压。当 VIN 电压  2.0 V时，B种情况XY 出现异常Z[，PWM开关关断，直- VIN 电压在 www.onsemi.cn 11 FSL4110LR IDS VO several mseconds t S = 1/f S t tS VFB t Dt f SW 0.5 V MAX f S + 1/2Df S 0.4 V t IDS several miliseconds MAX f S − 1/2Df S no repetition t t  27. 频率波9波E VDS 软89 内启动电启动后，(c慢提 SenseFET电 流。典型启动时% 20 ms，如图 28所示，启动 程Nb SenseFET电流(渐d增。 功率开关器 的宽(渐增加，$>建立合变压器、电感器和 电容器的正确工条。 出电容器.的电压(渐增 加，$>e畅地建立所2的 出电压。启动4有助 V止变压器f和，并次级#极管.的应力。 t Switching disabled Switching disabled  29. 间歇模(!" 线路补G 所有开关器C有其固有的Q播延J。此Q播延J 将导A定2 tCLD的电流)制延J。由电流)制延 J tCLD，因此 电压和 电压>%存在电流 峰%差异。电流峰%差异 电压>%的差异相 关， 电压的%hi宽，电流峰%的差异i大。 )j 电压是多少，持稳定的电流峰 %，291线 。FSL4110LR具有线 ，因 此 电压的真实峰%类C 电压的真实峰 %。tCLD效应可X忽略，如图 30所示。 2.5 ms ILIM Soft start envelope Drain Current t 8−Steps  28. 部软89 间歇模(!" 最大程度地待机模式 的功3，FSL4110LR (9突发模式。'着;+，反7电压4( 。当反7电压- VBURL (400 mV) 时，器 $动9%歇模式，如图 29所示。此时，开关操将 /止， 出电压开始，的g率取决待机电 流;+。B(导A反7电压.升。旦此%= VBURH (500 mV)，开关操将恢复。反7电压'> ，此程复。%歇模式(0替*和禁用 SenseFET的开关操，$>待机模式 的开关损 3。另外，E减少可听噪声%歇。 IDRAIN(460 VAC): 100 mA/div 500 ns/div  30. ILIMIT 波E (85 VAC 0 460 VAC) www.onsemi.cn 12 FSL4110LR 订购HI 输K@率表 ( 12) ,$编 FSL4110LRN FSL4110LRLX J装 !"结温 PDIP−7 (PDIP−8 LESS PIN 6) −40°C~125°C (7−DIP) (Pb−Free) 限流 RDS(ON) () 0.52 A 10 W PDIP7 MINUS PIN 6 GW (7−LSOP) (Pb−Free) 45~460 VAC ( 13) 85~460 VAC ( 13) 4 W ( 14) 9 W ( 14) Shipping† 3000 Units / Tube 1000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 12. ‘’8 €*Í。 13. 50°C µ¶’‚$fâÓã䀁åæ|ŠÍ。 14. m xy3。 www.onsemi.cn 13 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS PDIP−7 (PDIP−8 LESS PIN 6) CASE 626A ISSUE C DATE 22 APR 2015 SCALE 1:1 D A E H 8 5 1 4 E1 NOTE 8 b2 c B END VIEW TOP VIEW WITH LEADS CONSTRAINED NOTE 5 A2 A e/2 NOTE 3 L SEATING PLANE A1 C D1 M e 8X SIDE VIEW b 0.010 eB END VIEW M C A M B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3. 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT TO EXCEED 0.10 INCH. 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C. 6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED. 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE LEADS, WHERE THE LEADS EXIT THE BODY. 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS). DIM A A1 A2 b b2 C D D1 E E1 e eB L M INCHES MIN MAX −−−− 0.210 0.015 −−−− 0.115 0.195 0.014 0.022 0.060 TYP 0.008 0.014 0.355 0.400 0.005 −−−− 0.300 0.325 0.240 0.280 0.100 BSC −−−− 0.430 0.115 0.150 −−−− 10 ° MILLIMETERS MIN MAX −−− 5.33 0.38 −−− 2.92 4.95 0.35 0.56 1.52 TYP 0.20 0.36 9.02 10.16 0.13 −−− 7.62 8.26 6.10 7.11 2.54 BSC −−− 10.92 2.92 3.81 −−− 10 ° NOTE 6 GENERIC MARKING DIAGRAM* XXXXXXXXX AWL YYWWG XXXX A WL YY WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DOCUMENT NUMBER: DESCRIPTION: 98AON11774D Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PDIP−7 (PDIP−8 LESS PIN 6) PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS PDIP7 MINUS PIN 6 GW CASE 707AA ISSUE O DOCUMENT NUMBER: DESCRIPTION: 98AON13755G PDIP7 MINUS PIN 6 GW DATE 31 JAN 2017 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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