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FSSD07
1-Bit / 4-Bit SD/SDIO and MMC Dual-Host Multiplexer
Features
Description
On Resistance: 5Ω Typical, VDDC=2.7V
ftoggle: >75MHz
Low On Capacitance: 6pF Typical
Low Power Consumption: 2µA Maximum
Supports Secure Digital (SD), Secure Digital I/O
The FSSD07 is a 2:1 multiplexer that allows dual Secure
Digital (SD), Secure Digital I/O (SDIO), and Multimedia
Card (MMC) host controllers to share a common
peripheral. The host controllers can be equal to, greater
than, or less than peripheral card supply with minimal
power consumption. This configuration enables dual
host CMD, CLK, and D[3:0] signals to be multiplexed to
a common peripheral.
Supports 1-Bit / 4-Bit Host Controllers (VDDH1/H2=1.65V
The architecture includes the necessary bi-directional
data and command transfer capability for single highvoltage cards or dual-voltage supply cards. The clock
path is a uni-directional buffer.
(SDIO), and Multimedia Card (MMC) Specifications
to 3.6V) Communicating with
High-Voltage (2.7-3.6V) and Dual-Voltage Cards
(1.65-1.95V, 2.7-3.6V)
Typical applications involve switching in portables and
consumer applications: cell phones, digital cameras,
home theater monitors, set-top boxes, and notebooks.
VDDC=1.65 to 3.6V, VDDH1/H2=1.65 to 3.6V
24-Lead MLP and UMLP Packages
Applications
Cell Phone, PDA, Digital Camera, Portable GPS, and
Notebook Computer
LCD Monitor, TV, and Set-Top Box
Related Resources
FSSD07 Evaluation Board
Evaluation Board Users Guide
For samples, questions, or board requests; please
contact analogswitch@fairchildsemi.com
Figure 1. Analog Symbol Diagram
Ordering Information
Part
Number
Top
Mark
Operating
Temperature Range
FSSD07BQX
FSSD07
-40°C to +85°C
24-Lead Molded Leadless Package (MLP), JEDEC
MO-220, 3.5 x 4.5mm
Tape &
Reel
FSSD07UMX
JK
-40°C to +85°C
24-Lead Ultra-thin Molded Leadless Package
(UMLP), 0.4mm pitch
Tape &
Reel
© 2007 Fairchild Semiconductor Corporation
FSSD07 Rev. 1.0.2
Package Description
Packing
Method
www.fairchildsemi.com
FSSD07 — 1-Bit / 4-Bit SD/SDIO and MMC Dual-Host Multiplexer
March 2012
CMD
5
20 1DAT[0]
VDDC
6
19 1DAT[1]
GND
7
18
CLK
8
17 2DAT[3]
2DAT[2]
2CMD
15
VDDH2
Figure 2.
OE
1DAT[2]
1DAT[3]
1CMD
VDDH1
21
20
19
1
18
1CLK
CMD
2
17
1DAT[0]
VDDC
3
16
1DAT[1]
GND
4
15
2DAT[2]
CLK
5
14
2DAT[3]
DAT[0]
6
13
2CMD
2CLK
2DAT[0]
16
10
S
9
DAT[1]
2DAT[1]
DAT[0]
13 14
22
MLP Pin Assignments
7
8
Figure 3.
9
10
11
12
2CLK
21 1CLK
12
23
DAT[3]
VDDH2
4
11
24
VDDH1
2DAT[0]
22
3
S
1DAT[3]
1CMD
23
DAT[2]
OE
1DAT[2]
24
2DAT[1]
DAT[3]
1
DAT[1]
DAT[2]
2
UMLP Pin Assignments
Pin Definitions
Pin# MLP
Pin# UMLP
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
1DAT[2]
OE
DAT[2]
DAT[3]
CMD
VDDC
GND
CLK
DAT[0]
DAT[1]
S
2DAT[1]
2DAT[0]
2CLK
VDDH2
2CMD
2DAT[3]
2DAT[2]
1DAT[1]
1DAT[0]
1CLK
VDDH1
1CMD
1DAT[3]
Description
SDIO Common Port
Output Enable (Active HIGH)
SDIO Common Port
Power Supply (SDIO Peripheral Card Port)
Ground
Clock Path Port
FSSD07 — 1-Bit / 4-Bit SD/SDIO and MMC Dual-Host Multiplexer
Pin Configuration
SDIO Common Port
Select Pin
Host Common Port
Clock Path Port
Power Supply (Host Port)
Host Common Port
Clock Path Port
Power Supply (SDIO Host Port)
Host Common Port
Truth Table
OE
S
Function
HIGH
LOW
1CMD, 1CLK, 1DAT[3:0] connected to CMD, CLK, DAT[3:0]
HIGH
HIGH
2CMD, 2CLK,2DAT[3:0] connected to CMD, CLK, DAT[3:0]
LOW
X
CMD, DAT[3:0] ports high impedance; CLK is function of selected nCLK
© 2007 Fairchild Semiconductor Corporation
FSSD07 Rev. 1.0.2
www.fairchildsemi.com
2
VDDC
1.65V to 3.6V
RCMD , RDAT[3:0]
VDDH1
FSSD07
1.65V to 3.6V
CMD, DAT[3:0]
WiFi,
Bluetooth,
MMC or SD
Peripheral
1CMD, 1DAT[3:0]
5
Processor #1
5
1CLK
CLK
Secure Data/
Multi Media Card
Dual Host Selector
VDDH2
1.65V to 3.6V
SD Card
R1CMD, 2CMD = 10k to 100k ohm
R1DAT[3:0] , 2DAT[3:0] = 10k to 100k ohm
2CMD, 2DAT[3:0]
MMC Card
R1CMD, 2CMD = 4.7k to 100k ohm
R1DAT[3:0], 2DAT[3:0] = 50k to 100k ohm
5
2CLK
OE
S
GND
Figure 4. Typical Application Diagram
© 2007 Fairchild Semiconductor Corporation
FSSD07 Rev. 1.0.2
Processor #2
FSSD07 — 1-Bit / 4-Bit SD/SDIO and MMC Dual-Host Multiplexer
Typical Application
www.fairchildsemi.com
3
The FSSD07 enables the multiplexing of dual ASIC /
baseband processor hosts to a common peripheral card
or module, providing bi-directional support of the dualvoltage SD/SDIO or MMC cards available in the
marketplace. Each host SDIO port has its own supply
rail, such that hosts with different supplies can be
interfaced to a common peripheral module or card. The
peripheral card supply must be equal to or greater than
the host(s) to minimize power consumption. The
independent VDDC, VDDH1, and VDDH2 are defined by the
supplies connected from the application Power
Management ICs (PMICs) to the FSSD07. The clock
path is a uni-directional buffered path rather than a bidirectional switch port. The supplies (VDDC, VDDH1, and
VDDH2) have an internal termination resistor (typically
3M) to ensure the supply rails internally do not float if
the application turns off one or all of these sources.
IDLE State & Power-Up CMD/DAT Bus
“Parking”
The SD and MMC card specifications were written for a
direct point-to-point communication between host
controller and card. The introduction of the FSSD07 in
that path, as an expander, requires that the functional
operation and system latency not be impacted by the
switch characteristics. Since there are various card
formats, protocols, and configurable controllers, an OE
pin is available to facilitate a fast IDLE transition for the
CMD/DAT[3:0] outputs. Some controllers, rather than
placing CMD/DAT into high-impedance mode, pull the
outputs HIGH for a clock cycle prior to going into highimpedance mode (referred to as “parking” the output).
Some legacy controllers pull their outputs HIGH versus
high impedance.
If the OE pin is pulled HIGH and the controller places its
command and data outputs into high-impedance (driving
nCMD/nDAT[3:0]), the FSSD07 CMD/DAT[3:0] output
rise time is a function of the RC time constant through
the switch path. Pulling OE LOW puts the switches into
high impedance, disabling communication from the host
to card, and the CMD/DAT[3:0] outputs are pulled HIGH
by the system pull-up resistors chosen for the
application. This mechanism facilitates power-up
sequencing by holding OE LOW until supplies are stable
and communication between the host(s) and card is
enabled.
CMD, DAT Bus Pull-ups
The CMD and DAT[3:0] ports do not have, internally, the
system pull-up resistors as defined in the MMC or SD
card system bus specifications. The system bus pull-up
must be added external to the FSSD07. The value,
within the specific specification limits, is a function of the
individual application and type of card or peripheral
connected. For SD card applications, the RCMD and RDAT
pull-ups should be between 10kΩ and 100kΩ. For MMC
applications, the RCMD pull-ups should be between
4.7kΩ and 100kΩ, and the RDAT pull-ups between 50kΩ
and 100kΩ. The card-side CMD and DAT[3:0] outputs
have a circuit that facilitates incident wave switching, so
the external pull-up resistors ensure retention of the
output high level.
Power Optimization
FSSD07 — 1-Bit / 4-Bit SD/SDIO and MMC Dual-Host Multiplexer
Functional Description
Since the FSSD07 has multiple supplies (VDDC, VDDH1,
and VDDH2), the control signals have been referenced to
the card peripheral side (VDDC). To minimize power
consumption, current paths between supplies are
isolated when one or more supplies are not present.
This includes the configuration of the removal of VDDC
with host controller supplies remaining present.
The OE pin can be used to place the CMD and DAT[3:0]
into high-impedance mode during power-up sequencing
or when the system enters IDLE state (see IDLE State
CMD/DAT Bus “Parking”).
CLK Bus
The 1CLK and 2CLK inputs are bi-state buffer
architectures, rather than a switch I/O, to ensure 52MHz
incident wave switching. Since most host controllers
also have a clock enable register bit to enable or disable
the system clock when in IDLE mode, the CLK output is
not disabled by the OE pin. Instead, the CLK output is a
function of whichever host controller clock is selected by
the S pin.
Consequently, there is always a clock path connected
between the selected host and the card. The state of the
CLK pin is a function of the selected host controller
nCLK output pin, which facilitates retaining clock duty
cycle in the system or performing read / wait operations.
© 2007 Fairchild Semiconductor Corporation
FSSD07 Rev. 1.0.2
www.fairchildsemi.com
4
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VDDC
Parameter
Conditions
Card Supply Voltage
VDDH1,VDDH2 Host Controller Supply Voltage
VSW
VCNTRL
VCLKI
1DAT[3:0], 2DAT[3:0],
1CMD, 2CMD Pins
Switch I/O Voltage(1)
Control Input Voltage(1)
CLK Input Voltage
(1)
(1)
Min.
Max.
Unit
-0.5
4.6
V
-0.5
4.6
V
-0.5
(2)
VDDx + 0.3V
(4.6V maximum)
V
(2)
VDDx +
DAT[3:0], CMD Pins
-0.5
0.3V
(4.6V maximum)
V
S, OE
-0.5
4.6
V
1CLK, 2CLK
-0.5
4.6
V
-0.5
(2)
VDDx + 0.3V
(4.6V maximum)
V
-50
mA
VCLKO
CLK Output Voltage
IINDC
Input Clamp Diode Current
ISW
Switch I/O Current
SDIO Continuous
50
mA
Peak Switch Current
SDIO Pulsed at 1ms
Duration,
