FT7521L6X

FT7521 Reset Timer with Fixed Delay and Reset Pulse Features Description          The FT7521 is a timer for resetting a mobile device where long reset times are needed. The long delay helps avoid unintended resets caused by accidental key presses. It has a fixed delay of 7.5 ±20% seconds. The DSR pin enables Test Mode operation by immediately forcing /RST1 LOW for factory testing. Fixed Reset Delay: 7.5 Seconds One Input Reset Pin Open-Drain Output Pin with Fixed 400ms Pulse 1.8 V to 5.0 V Operation (TA=-40°C to +85°C) 1.7 V to 5.0 V Operation (TA=-25°C to +85°C) 1.65 V to 5.00 V Operation (TA=0°C to +85°C) 7.5 s) When the /SR0 input goes LOW, the internal timer starts counting. If the /SR0 input stays LOW for at least 7.5 s, the RST output is enabled and pulled LOW. The output RST is held LOW for tREC, 400 ms, as soon as the reset time of 7.5 s is met, regardless of the state of the /SR0 pin. When the /SR0 input has returned HIGH and the tREC has expired, the internal timer resets and awaits the next RESET event. Operation Modes A low input signal on /SR0 starts the oscillator. There are two scenarios for counting: short duration and long duration. In the short-duration scenario, output /RST1 is not affected. In the long-duration scenario, the output Zero-Second Test Mode /RST1 goes LOW immediately after /SR0 goes LOW. N=7.5s Short-Duration, Normal Operation /RST1 never goes LOW because /SR0 LOW duration does not meet requirement: Reset Time N=7.5s /SR0 RST1 Long-Duration, Normal Operation /RST1 goes LOW because /SR0 LOW duration exceeded requirement: Reset Time N=7.5s /SR0 RST1 tREC=400ms /SR0 Zero-Second Factory-Test Mode /RST1 goes LOW immediately after /SR0 goes LOW RST1 tREC=400ms Figure 4. © 2009 Fairchild Semiconductor Corporation FT7521 • Rev. 1.0.8 Reset Timing Waveforms www.fairchildsemi.com 5 FT7521 — Reset Timer with Fixed Delay and Reset Pulse Functional Description FT7521 — Reset Timer with Fixed Delay and Reset Pulse AC Test Circuit and Waveforms Figure 5. © 2009 Fairchild Semiconductor Corporation FT7521 • Rev. 1.0.7 AC Test Circuit and Waveforms for /RST1 Output ST Output www.fairchildsemi.com 6 2X 0.05 C 1.45 B 2X (1) 0.05 C (0.254) (0.49) 5X 1.00 (0.75) PIN 1 IDENTIFIER 5 (0.52) 1X A TOP VIEW 0.55MAX (0.30) 6X PIN 1 0.05 C 0.05 0.00 RECOMMENED LAND PATTERN 0.05 C C 0.25 0.15 6X 1.0 DETAIL A 0.10 0.05 0.45 0.35 0.10 0.00 6X C B A C 0.40 0.30 0.35 5X 0.25 0.40 5X 0.30 0.5 (0.05) 6X 0.075 X 45 CHAMFER DETAIL A PIN 1 TERMINAL (0.13) 4X BOTTOM VIEW Notes: 1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD 2. DIMENSIONS ARE IN MILLIMETERS 3. DRAWING CONFORMS TO ASME Y14.5M-1994 4. FILENAME AND REVISION: MAC06AREV4 5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY OTHER LINE IN THE MARK CODE LAYOUT. Figure 6. 6-Lead, MicroPak™ 1.0 x 1.45 mm, JEDEC MO-252 Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2009 Fairchild Semiconductor Corporation FT7521 • Rev. 1.0.7 www.fairchildsemi.com 7 FT7521 — Reset Timer with Fixed Delay and Reset Pulse Physical Dimensions 0.89 0.35 0.05 C 1.00 2X B A 5X 0.40 PIN 1 MIN 250uM 0.66 1.00 1X 0.45 6X 0.19 0.05 C TOP VIEW RECOMMENDED LAND PATTERN FOR SPACE CONSTRAINED PCB 2X 0.90 0.05 C 0.55MAX C 0.35 5X 0.52 SIDE VIEW 0.73 (0.08) 4X 1 DETAIL A 2 1X 0.57 0.09 0.19 6X 3 0.20 6X ALTERNATIVE LAND PATTERN FOR UNIVERSAL APPLICATION (0.05) 6X 5X 0.35 0.25 6 5 4 0.35 0.60 (0.08) 4X 0.10 .05 C C B A 0.40 0.30 BOTTOM VIEW NOTES: A. COMPLIES TO JEDEC MO-252 STANDARD B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. LANDPATTERN RECOMMENDATION IS BASED ON FSC DESIGN. E. DRAWING FILENAME AND REVISION: MGF06AREV3 Figure 7. 0.075X45° CHAMFER DETAIL A PIN 1 LEAD SCALE: 2X 6-Lead, MicroPak2™ 1.0 x 1.0 mm Body, .35 mm Pitch Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2009 Fairchild Semiconductor Corporation FT7521 • Rev. 1.0.7 www.fairchildsemi.com 8 FT7521 — Reset Timer with Fixed Delay and Reset Pulse Physical Dimensions FT7521 — Reset Timer with Fixed Delay and Reset Pulse © 2009 Fairchild Semiconductor Corporation FT7521 • Rev. 1.0.7 www.fairchildsemi.com 9