FUSB302B01MPX

DATA SHEET www.onsemi.cn 采PD的编程USBType‐C  FUSB302B WLCSP9 CASE 567TN 说 FUSB302B向期望实现DRP/SRC/SNK USB Type-C接器， 少程的 员。 FUSB302B 支 持USB Type-C 检 测 ， 包 括  接 和 方 向 。 FUSB302B 成USB BMC电力协的物理层， 100 W功率和换。BMC的PD模块支持Type-C格的替 接口。  WQFN14 CASE 510BR ORDERING INFORMATION • 动DRP切换的双功 • 基接对可 机或备接的力。 • 可用机、用备或双。 See detailed ordering and shipping information on page 2 of this data sheet. ♦ 用备可在带固定CC或VCONN 的Type-C插座或插 头!。 • 完支持Type-C 1.2。 成CC引"的功 ♦ 机接/分离检测 ♦ 机电流力指示 ♦ 备电流力指示 ♦ #$%器&模式 ♦ '(&模式 ♦ 动电)检测 • 将CCx 成到VCONN开，所有具有USB 3.1功的电源* )提+流,制。 • USB电力(PD) 2.0，支持1.2版本 ♦ 动GoodCRC报文响应 ♦ 未收到GoodCRC时动-发报文 ♦ 时，动--发报文 ♦ 动硬-发命 • 电池.尽支持(无电时支持SNK模式) • 功.!： ICC = 25 mA (典型) • 封0： ♦ 9焊点WLCSP (1.215 mm × 1.260 mm) ♦ 14引"MLP (2.5 mm × 2.5 mm, 0.5 mm12)  • 智手机 • 平板电3 • 4型电3 • 笔5本电3 • 电源%器 • 相机 • 加密狗 © Semiconductor Components Industries, LLC, 2015 August, 2021 − Rev. 5 1 Publication Order Number: FUSB302BCN/D FUSB302B USB Type-C Connector Charger OVP VBUS VCONN FUSB302 CC1 USB Type-C Detection Control PD I2Ct CC2 Processor USB Switch TX1/RX1 USB 3.1 TX2/RX2 5Gbps Figure 1. Block Diagram Table 1. ORDERING INFORMATION Part Number Top Mark FUSB302BUCX H4 FUSB302BMPX UA FUSB302B01MPX UP FUSB302B10MPX US FUSB302B11MPX UT FUSB302BVMPX DA Operating Temperature Range Package Shipping† 9-ball Wafer-level Chip Scale Package (WLCSP), 0.4 mm Pitch −40 to 85°C −40 to 85°C 14-lead MLP 2.5 mm × 2.5 mm, 0.5 mm Pitch 3,000 / Tape and Reel −40 to 105°C †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.cn 2 FUSB302B   BAT CHARGER OVP 3.0V VBUS REG 1.71V to V VCONN VDD FUSB302B TYPE−C I2C/ Registers VBUS GND RX2+ TX2+ RX2− TX2− VBUS SBU1 CC2 D− D+ D+ D− CC1 SBU2 VBUS TX1− RX1− TX1+ RX1+ GND CC 2 Dual−Role Detection Auto Toggle CC 1 Switch Matrix CC Detection / Control Powered Cable Audio Adapter / Debug Acc BMC I/O INT_N I2C_SDA I2C_SCL Logic & Control Processor DAC Comparator GND GND USB_3.1 1 FUSB340 USB 3.1 2:1 Switch USB_3.1 2 Figure 2. Typical Application  VCONN VBUS CC1 FUSB302B Processor (Software) Type−C Connection States − SOURCE − SINK − SINK with Accessory Support − Dual−Role Port − Dual−Role Port with Accessory Support Control Settings : Comp. Status RD CC2 Type−C Switch Settings DAC INT_N SDA 2 SCL PD (Provider/Consumer) Device Policy Manager PD/ VDM I C Reg PD Configuration PD Status RD Code/ Control Logic Protocol FIFO CRC32 Tx FIFO CRC32 Rx FIFO Access 4B5B BMC BMC DRIVER Policy Engine BMC Physical Layer 4B5B Figure 3. Functional Block Diagram www.onsemi.cn 3 BMC CDR FUSB302B 脚 A B C 1 2 3 3 2 1 CC2 VBUS VDD VDD VBUS CC2 VCONN INT_N SCL SCL INT_N VCONN CC1 GND SDA SDA GND CC1 TOP Through View A B C Bottom view Figure 4. FUSB302BUCX Pin Assignment Table 2. PIN MAP Column 1 Column 2 Column 3 Row A CC2 VBUS VDD Row B VCONN INT_N SCL Row C CC1 GND SDA www.onsemi.cn 4 FUSB302B 14 CC2 13 VCONN 12 VCONN 11 CC1 1 CC2 TOP THROUGH VIEW 2 VBUS Connect to GND for Thermal 3 VDD 4 VDD 5 INT_N 6 SCL 11 CC1 10 CC1 10 CC1 9 GND 9 GND 8 GND 8 GND 7 SDA 12 VCONN 13 VCONN 14 CC2 1 CC2 BOTTOM VIEW 2 VBUS Connect to GND for Thermal 7 SDA 6 SCL 5 INT_N 3 VDD 4 VDD Figure 5. FUSB302BMPX Pin Assignment (N/C = No Connect) Table 3. PIN DESCRIPTION Name Type Description USB TYPE-C CONNECTOR INTERFACE CC1/CC2 I/O GND Ground VBUS Input Type-C connector Configuration Channel (CC) pins. Initially used to determine when an attach has occurred and what the orientation of the insertion is. Functionality after attach depends on mode of operation detected. Operating as a host: 1. Sets the allowable charging current for VBUS to be sensed by the attached device 2. Used to communicate with devices using USB BMC Power Delivery 3. Used to detect when a detach has occurred Operating as a device: 1. Indicates what the allowable sink current is from the attached host. Used to communicate with devices using USB BMC Power Delivery Ground VBUS input pin for attach and detach detection when operating as an upstream facing port (Device). Expected to be an OVP protected input. POWER INTERFACE VDD Power VCONN Power Switch Input supply voltage. Regulated input to be switched to correct CC pin as VCONN to power USB3.1 full-featured cables and other accessories. SIGNAL INTERFACE SCL Input I2C serial clock signal to be connected to the phone-based I2C master. SDA Open-Drain I/O I2C serial data signal to be connected to the phone-based I2C master INT_N Open-Drain Output Active LOW open drain interrupt output used to prompt the processor to read the I2C register bits www.onsemi.cn 5 FUSB302B 配置通道 • USB BMC电力物理层 •  (CC)6比7器。 FUSB302B 成实施USB Type-C机、器或 双-端口所的控制和检测功： • 器端口拉(RD) • 机端口拉(IP) • 带OCP功的VCONN电源开，%用功 USB3.1电) 每CC引"包含灵活的开矩8，可9机 控制执的Type-C端口:型。开如Figure 6 所示。 CCX VCONN VCONN_SWITCH VCONN_CCx Reg MEAS_CCx Reg DAC/ Comparator MEAS_CC_SWITCH TXCCx Reg BMC I/O TX_BMC_SWITCH PU_ENx Reg Current Source Pull−ups PWDNx Reg PULLUP_SWITCH PULLDOWN_SWITCH 5.1K Figure 6. Configuration Channel Switch Functionality TYPE-C FUSB302B执多比7器和可程的DAC， 可用确定CC和VBUS引"的状态。此状态息 处理器提确定接、断开接及Type-C端口 接电电流所的;息。 FUSB302B有固定6比7器，用比7< 对Type-C 可 检 测 的  种  电 电 流 电 平 来 匹 USB Type−C  格 。 状 态 变 化 时 ， = 比 7 器  动 ! BC_LVL和COMP发生"断。>固定6比7器外， 机?可!用6#DAC更准确地确定CC*状态。 FUSB302B?有用监控VBUS是否到有效 6  的 固 定 比 7 器 。DAC 可 用  测  最 20 V 的 VBUS，9够确@VBUS*已根据PD或$ 方式发生A期变化，更改电电平。 通过自进行 FUSB302B  够 动 切换DRP 。 在  动切 换 时， FUSB302B 可 在 内 ; 控 制PDWN1 、PDWN2 、 PU_EN1、PU_EN2、MEAS_CC1和MEAS_CC2，并在 SRC模式和SNK模式1切换固定DRP。或B，可% SRC或SNK模式!，并持CDECC1和CC2。 www.onsemi.cn 6 FUSB302B  Table 4. PROCESSOR CONFIGURES THE FUSB302B THROUGH I2C I2C Registers/Bits FUSB302B  够手 动 切换DRP 。 在 手 动切 换 +程 "，可!用处理器+I2C和TOGGLE = 0来 FUSB302B。 Value TOGGLE 1 PWR 配置 07H HOST_CUR0 1 HOST_CUR1 0 MEAS_VBUS 0 VCONN_CC1 0 VCONN_CC2 0 Mask Register 0xFE Maska Register 0xBF Maskb Register (Except I_TOGDONE and I_BC_LVL Interrupt) 0x01 PWR[3:0] 0xBF Type-C器必F监控VBUS确定是否接或断 开接。FUSB302B+VBUSOK"断提此息。 Type-C器确定已接Type-C机后，确定各 CC 引 " G 用 的 端 子 : 型 。   将 确 定 是 否 根 据 BC_LVL和COMP"断和状态#来Ra或Rd端子。 另外，对Rd端子，可+H取BC_LVL状态 #，步确定Type-C机容的电电流。Table 5 "汇总。 能 TOGGLE#(Control2寄存器)后，FUSB302B将 在SRC模式和SNK模式1切换DRP。?可% SRC或%SNK模式，并持CDECC1和CC2。此! 模式可+TOGGLE = 1开启，&处理器应最初 写'HOST_CUR1 = 0、HOST_CUR0 = 1 (对I@电 流) 、VCONN_CC1 = VCONN_CC2 = 0 、Mask Register = 0xFE 、Maska register = 0xBF 、Maskb register = 0x01、PWR = 0x01。处理器?应H取"断寄 存器将清>，然后再TOGGLE#。 1. Once it has been determined what the role is of the FUSB302B, it returns I_TOGDONE and TOGSS1/2. 2. Processor then can perform a final manual check through I2C. Table 5. DEVICE INTERRUPT SUMMARY Interrupt Status Status Type BC_LVL[1:0] COMP COMP Setting VBUSOK Meaning CC Detection 2’b00 NA NA 1 vRA 2’b01 NA NA 1 vRd−Connect and vRd−USB 2’b10 NA NA 1 vRd−Connect and vRd−1.5 2’b11 0 6’b11_0100 (2.05 V) 1 vRd−Connect and vRd−3.0 Attach NA NA NA 1 Host Attached, VBUS Valid Detach NA NA NA 0 Host Detached, VBUS Invalid Type-C器(SNK)的层J流程图如Figure 7 所示。 www.onsemi.cn 7 FUSB302B Disabled: FUSB302B in low power mode looking for an attach FUSB302B I_TOGDONE interrupt alerts host software that something has attached. Unattached.SNK: Host software enables FUSB302B pull−downs and measure block to detect attach FUSB302B I_VBUSOK interrupt alerts host software that an attach has occurred FUSB302B I_VBUSOK interrupt alerts host software that a detach has occurred Attached.SNK Host software uses FUSB302B comparators and DAC to determine attach orientation and port type Host software determines that an accessory has been attached DebugAccessory AudioAccessory FUSB302B I_COMP and I_VBUSOK interrupts alert host software that a accessory detach has occurred Figure 7. SNK Software Flow 配置 ! FUSB302B机+HOST_CUR控制#更 改端子的电电流力。如果在接前更改 HOST_CUR#，接器后，FUSB302B将动指示 所的电流力。如果在接器后更改电流 力，FUSB302B(立即将CC更改所的力。 当FUSB302BType-C机时，可!用比 7器和DAC的状态来确定接或断开接Type-C器 的时1，及各CC引"接的端子:型。 ATTACH CC 0V HOST_CUR[1:0] = DEFAULT HIGH CURRENT SETTING Figure 8. HOST_CUR Changed after Attach www.onsemi.cn 8 MED CURRENT SETTING FUSB302B ATTACH CC 0V HIGH CURRENT SETTING MED CURRENT SETTING DEFAULT CURRENT Figure 9. HOST_CUR Changed prior to Attach Type-C格求。BC_LVL比7器?可用 Ra检测 流程的;分。Table 6"汇总。 Type-C格简K明Type-C机的)同接和断 开接6，= 基L各CC引"的电流。根据 HOST_CUR，将'MDAC比7器6，匹 Table 6. HOST INTERRUPT SUMMARY Interrupt Status Termination HOST_CUR[1:0] BC_LVL[1:0] Ra 2’b01 2’b00 NA NA 2’b10 2’b01 0 6’b00_1010 (0.42 V) 2’b11 2’b10 0 6’b01_0011 (0.8 V) 2’b01, 2’b10 NA 0 6’b10_0110 (1.6 V) Attach NA 1 6’b10_0110 (1.6 V) Detach NA 0 6’b11_1110 (2.6 V) Attach NA 1 6’b11_1110 (2.6 V) Detach Rd 2’b11 COMP COMP Setting Attach/Detach NA Type−C机(SRC)的层J流程图如Figure 10" 所示。 www.onsemi.cn 9 FUSB302B Disabled: FUSB302B in low power mode looking for an attach FUSB302B I_TOGDONE interrupt alerts host software that something has attached. Unattached.SRC: Host software enables FUSB302B pull−ups and measure block to detect attach Host software utilizes I_COMP and I_BC_LVL interrupts to determine an attach and what type of port is attached. FUSB302B I_COMP interrupt alerts host software that a detach has occurred Attached.SRC Host software configures FUSB302B based on insertion orientation and enables VBUS and VCONN AudioAccessory DebugAccessory FUSB302B I_COMP and I_VBUSOK interrupts alert host software that a accessory detach has occurred Figure 10. SRC Software Flow 配置"重角色 FUSB302B可用实现双-端口。Type-C双- 端口在Type-C器和Type-C机模式1切换。 机控制FUSB302B在各状态的切换时1和 ，如Figure 11所示。 Type-C格根据所接的端口:型，将端口    器  或  机 。 此 功  : *  G 用 最 新USB 接器的USB OTG端口，+N称双-端口。 Disabled: FUSB302B in low power mode looking for an attach FUSB302B I_TOGONE interrupt alerts host software that something has attached. Host software enables FUSB302B low power Disabled state Unattached.SNK: Host software enables FUSB302B pull−downs and measure block to detect attach FUSB302B I_VBUSOK interrupt alerts host software that a detach has occurred Host software toggle expires FUSB302B I_VBUSOK interrupt alerts host software that an attach has occurred Unattached.SRC: Host software enables FUSB302B pull−ups and measure block to detect attach Host software utilizes I_COMP and I_BC_LVL interrupts to determine an attach Attached.SRC Host software configures FUSB302B based on insertion orientation and enables VBUS and VCONN Attached.SNK Host software uses FUSB302B comparators and DAC to determine attach orientation and port type Figure 11. DRP Software Flow www.onsemi.cn 10 FUSB302B I_COMP interrupt alerts host software that a detach has occurred FUSB302B BMC#$输送 Type-C接器USB电力(PD)功+,端 口1接的CC引"。方法是-助BMC 电力协，出多种)同的原因，. Type-C接器合!用。简/O可的用 P。 • 协商和控制电功率J • 可Q接口包括MHL、Display Port • 用定制扩展坞或的厂商特定接口 • 双-端口的切换功(在机或器模式1 切换) • .USB3.1功电) FUSB302B机+写'和H取FIFO及控 制FUSB302B物理接口来实现USB BMC PD的所有功 。 FUSB302B!用牌控制BMC PD数据包的1。 可+写'= 牌来1FIFO，并控制数据包在 CC引"的1方式。牌灵活，够支持 USB PD格。FUSB302B?可+牌控制BMC发射 器。+特定牌写'可启用或禁用发射器，+将 1数据包所的;息突发写'FIFO，够更快 地处理数据包。 CC引"收到有效的数据包后，FUSB302B接收器 将2存接收FIFO"收到的数据和CRC。CC引"检 测到活动时，BMC接收器将动启用内;振T器， 并在收到数据包后，加UVFIFO。I_ACTIVITY和 I_CRC_CHK"断将提W机收到有效数据包。 FUSB302B 成BMC PD瘦客户端，包括BMC0物 理层和数据包FIFO (48字M用发，80字M用接 收)，可+RSI2C的机发和接收数据包。 Code/ Control Logic 4B5B CC1 BMC DRIVER FIFO CRC32 Tx BMC CC2 FIFO CRC32 Rx 4B5B BMC CDR Figure 12. USB BMC Power Delivery Blocks PD自-.GoodCRC %级& 电力数据包l另有K明，否则所有典型j在TA = 25°C条测得。 Table 9. BASEBAND PD TA = −40 to +855C TA = −40 to +1055C (Note 11) TJ = −40 to +1255C Min Typ Max Unit 3.03 − 3.70 ms Transmitter Output Impedance 33 − 75 W tEndDriveBMC Time to Cease Driving the Line after the end of the last bit of the Frame − − 23 ms tHoldLowBMC Time to Cease Driving the Line after the final High-to-Low Transition 1 − − ms 1.05 − 1.20 V Symbol UI Parameter Unit Interval TRANSMITTER zDriver VOH Logic High Voltage VOL Logic Low Voltage 0 − 75 mV tStartDrive Time before the start of the first bit of the preamble when the transmitter shall start driving the line −1 − 1 ms tRISE_TX Rise Time 300 − − ns tFALL_TX Fall Time 300 − − ns Receiver Capacitance when Driver isn’t Turned On − 50 − pF zBmcRx Receiver Input Impedance 1 − − MW tRxFilter Rx Bandwidth Limiting Filter (Note 4) 100 − − ns RECEIVER cReceiver 4. Guaranteed by Characterization and/or Design. Not production tested. DRP Switch Vconn Switch Vconn Connector Cable Connector Receiver Receiver cCablePlug cCablePlug Figure 16. Transmitter Test Load www.onsemi.cn 14 DRP FUSB302B Table 10. TYPE-C CC SWITCH TA = −40 to +855C TA = −40 to +1055C (Note 11) TJ = −40 to +1255C Symbol Parameter RSW_CCx RDSON for SW1_CC1 and SW1_CC2, VCONN to CC1 & CC2 ISW_CCX Over-Current Protection (OCP) limit at which VCONN switch shuts off over the entire VCONN voltage range (OCPreg = 0Fh) tSoftStart Time taken for the VCONN switch to turn on during which Over-Current Protection is disabled Min Typ Max Unit − 0.4 1.2 W 600 800 1000 mA − 1.5 − ms I80_CCX SRC 80 mA CC current (Default) HOST_CUR1 = 0, HOST_CUR0 = 1 64 80 96 mA I180_CCX SRC 180 mA CC Current (1.5 A) HOST_CUR1 = 1, HOST_CUR0 = 0 166 180 194 mA I330_CCX SRC 330 mA CC Current (3 A) HOST_CUR1 = 1, HOST_CUR0 = 1 304 330 356 mA VUFPDB SNK Pull-down Voltage in Dead Battery under all Pull-up SRC Loads − − 2.18 V RDEVICE Device Pull-down Resistance (Note 5) 4.6 5.1 5.6 kW zOPEN CC Resistance for Disabled State 126 − − kW WAKElow Wake threshold for CC pin SRC or SNK LOW value. Assumes bandgap and wake circuit turned on ie PWR[0] = 1 − 0.25 − V WAKEhigh Wake threshold for CC pin SRC or SNK HIGH value. Assumes bandgap and wake circuit turned on ie PWR[0] = 1 − 1.45 − V Hysteresis on the Ra and Rd Comparators (Note 7) − 20 − mV 0.15 0.61 1.16 0.20 0.66 1.23 0.25 0.70 1.31 vBC_LVLhys vBC_LVL CC Pin Thresholds, Assumes PWR = 4’h7 BC = 2’b00 BC = 2’b01 BC = 2’b10 V vMDACstepCC Measure block MDAC step size for each code in MDAC[5:0] register − 42 − mV vMDACstepVBUS Measure block MDAC step size for each code in MDAC[5:0] register for VBUS measurement − 420 − mV vVBUSthr VBUS threshold at which I_VBUSOK interrupt is triggered. Assumes measure block on ie PWR[2] = 1 − − 4.0 V tTOG1 When TOGGLE = 1, time at which internal versions of PU_EN1 = PU_EN2 = 0 and PWDN1 = PDWN2 = 1 selected to present externally as a SNK in the DRP toggle 30 45 60 ms tTOG2 When TOGGLE = 1, time at which internal versions of PU_EN1 = 1 or PU_EN2 = 1 and PWDN1 = PDWN2 = 0 selected to present externally as a SRC in the DRP toggle 20 40 ms tDIS Disable time after a full toggle (tTOG1 + tTOG2) cycle so as to save power TOG_SAVE_PWR2:1 = 00 TOG_SAVE_PWR2:1 = 01 TOG_SAVE_PWR2:1 = 10 TOG_SAVE_PWR2:1 = 11 − − − − 0 40 80 160 − − − − Tshut Temp. for Vconn Switch Off − 145 − °C Thys Temp. Hysteresis for Vconn Switch Turn On − 10 − °C 5. RDEVICE minimum and maximum specifications are only guaranteed when power is applied. www.onsemi.cn 15 30 ms FUSB302B Table 11. CURRENT CONSUMPTION TA = −40 to +855C TA = −40 to +1055C (Note 11) TJ = −40 to +1255C Min Typ Max Unit Nothing Attached, No I2C Transactions − 0.37 5.0 mA 3.0 to 5.5 Nothing Attached, No I2C Transactions − 0.37 8.5 mA Unattached (standby) Toggle Current 3.0 to 5.5 Nothing attached, TOGGLE = 1, PWR[3:0] = 1h, WAKE_EN = 0, TOG_SAVE_PWR2:1 = 01 − 25 40 mA BMC PD Standby Current 3.0 to 5.5 Device Attached, BMC PD Active But Not Sending or Receiving Anything, PWR[3:0] = 7h − 40 − mA Symbol Parameter Idisable Disabled Current 3.0 to 5.5 Idisable Disabled Current (Note 11) Itog Ipd_stby_meas VDD (V) Conditions Table 12. USB PD SPECIFIC PARAMETERS TA = −40 to +855C TA = −40 to +1055C (Note 11) TJ = −40 to +1255C Symbol Parameter Min Typ Max Unit tHardReset If a Soft Reset message fails, a Hard Reset is sent after tHardReset of CRCReceiveTimer expiring − − 5 ms tHardReset Complete If the FUSB302B cannot send a Hard Reset within tHardResetComplete time because of a busy line, then a I_HARDFAIL interrupt is triggered − − 5 ms 0.9 − 1.1 ms tReceive This is the value for which the CRCReceiveTimer expires. The CRCReceiveTimer is started upon the last bit of the EOP of the transmitted packet tRetry Once the CRCReceiveTimer expires, a retry packet has to be sent out within tRetry time. This time is hard to separate externally from tReceive since they both happen sequentially with no visible difference in the CC output − − 75 ms tSoftReset If a GoodCRC packet is not received within tReceive for NRETRIES then a Soft Reset packet is sent within tSoftReset time. − − 5 ms tTransmit From receiving a packet, we have to send a GoodCRC in response within tTransmit time. It is measured from the last bit of the EOP of the received packet to the first bit sent of the preamble of the GoodCRC packet − − 195 ms Table 13. IO SPECIFICATIONS TA = −40 to +855C TA = −40 to +1055C (Note 11) TJ = −40 to +1255C Symbol Parameter VDD (V) Conditions Min Typ Max Unit − − 0.4 V 50 − − ms HOST INTERFACE PINS (INT_N) VOLINTN TINT_Mask Output Low Voltage 3.0 to 5.5 Time from global interrupt mask bit cleared to when INT_N goes LOW 3.0 to 5.5 IOL = 4 mA I2C INTERFACE PINS – STANDARD, FAST, OR FAST MODE PLUS SPEED MODE (SDA, SCL) (Note 6) VILI2C Low-Level Input Voltage 3.0 to 5.5 − − 0.51 V VIHI2C High-Level Input Voltage 3.0 to 5.5 1.32 − − V www.onsemi.cn 16 FUSB302B Table 13. IO SPECIFICATIONS TA = −40 to +855C TA = −40 to +1055C (Note 11) TJ = −40 to +1255C Symbol Parameter VDD (V) Conditions Min Typ Max Unit 94 − − mV I2C INTERFACE PINS – STANDARD, FAST, OR FAST MODE PLUS SPEED MODE (SDA, SCL) (Note 6) Hysteresis of Schmitt Trigger Inputs 3.0 to 5.5 Input Current of SDA and SCL Pins 3.0 to 5.5 Input Voltage 0.26 V to 2.0 V −10 − 10 mA ICCTI2C VDD Current when SDA or SCL is HIGH 3.0 to 5.5 Input Voltage 1.8 V −10 − 10 mA VOLSDA Low-Level Output Voltage (Open-Drain) 3.0 to 5.5 IOL = 2 mA 0 − 0.35 V IOLSDA Low-Level Output Current (Open-Drain) 3.0 to 5.5 VOLSDA = 0.4 V 20 − − mA CI Capacitance for Each I/O Pin (Note 7) 3.0 to 5.5 − 5 − pF VHYS II2C 6. I2C pull up voltage is required to be between 1.71 V and VDD. Table 14. I2C SPECIFICATIONS FAST MODE PLUS I2C SPECIFICATIONS Fast Mode Plus Min Max Unit 0 1000 kHz Hold Time (Repeated) START Condition 0.26 − ms tLOW Low Period of I2C_SCL Clock 0.5 − ms tHIGH High Period of I2C_SCL Clock 0.26 − ms Symbol fSCL tHD;STA Parameter I2C_SCL Clock Frequency tSU;STA Set-up Time for Repeated START Condition 0.26 − ms tHD;DAT Data Hold Time 0 − ms tSU;DAT Data Set-up Time 50 − ns tr Rise Time of I2C_SDA and I2C_SCL Signals (Note 7) − 120 ns tf Fall Time of I2C_SDA and I2C_SCL Signals (Note 7) 6 120 ns Set−up Time for STOP Condition 0.26 − ms tBUF Bus-Free Time between STOP and START Conditions (Note 7) 0.5 − ms tSP Pulse Width of Spikes that Must Be Suppressed by the Input Filter 0 50 ns Cb Capacitive Load for each Bus Line (Note 7) − 550 pF tVD−DAT Data Valid Time for Data from SCL LOW to SDA HIGH or LOW Output (Note 7) 0 0.45 ms tVD−ACK Data Valid Time for acknowledge from SCL LOW to SDA HIGH or LOW Output (Note 7) 0 0.45 ms tSU;STO VnL Noise Margin at the LOW Level (Note 7) 0.2 − V VnH Noise Margin at the HIGH Level (Note 7) 0.4 − V 7. Guaranteed by Characterization and/or Design. Not production tested. www.onsemi.cn 17 FUSB302B Figure 17. Definition of Timing for Full-Speed Mode Devices on the I2C Bus Table 15. I2C SLAVE ADDRESS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FUSB302BUCX, FUSB302BMPX, FUSB302BVMPX Name 0 1 0 0 0 1 0 R/W FUSB302B01MPX 0 1 0 0 0 1 1 R/W FUSB302B10MPX 0 1 0 0 1 0 0 R/W FUSB302B11MPX 0 1 0 0 1 0 1 R/W Table 16. REGISTER DEFINITIONS (Notes 8 and 9) Address Register Name Type Reg Value 0x01 Device ID R 9X 0x02 Switches0 R/W 3 PU_EN2 PU_EN1 VCONN_ CC2 VCONN_ CC1 0x03 Switches1 R/W 20 POWER ROLE SPEC REV1 SPEC REV0 DATA ROLE 0x04 Measure R/W 31 MEAS_ VBUS MDAC5 MDAC4 0x05 Slice R/W 60 SDAC_ HYS2 SDAC5 SDAC4 0x06 Control0 R/W/C 24 TX_ FLUSH INT_MASK 0x07 Control1 R/W/C 0 ENSOP 2DB ENSOP 1DB 0x08 Control2 R/W 2 TOG_ SAVE_ PWR1 TOG_RD_ ONLY 0x09 Control3 R/W 6 SEND_ HARD_ BIST_ TMODE Bit 7 Bit 6 Bit 5 Bit 4 Version ID[3:0] SDAC_ HYS1 TOG_ SAVE_ PWR2 RESET www.onsemi.cn 18 Bit 3 Bit 2 Bit 1 Product ID[1:0] MEAS_ CC2 MEAS_ CC1 PDWN2 PDWN1 AUTO_ CRC TXCC2 TXCC1 MDAC3 MDAC2 MDAC1 MDAC0 SDAC3 SDAC2 SDAC1 SDAC0 HOST_ CUR1 HOST_ CUR0 AUTO_ PRE TX_START RX_ FLUSH ENSOP2 ENSOP1 BIST_ MODE2 AUTO_ HARD RESET Bit 0 Revision ID[1:0] WAKE_EN MODE[1:0] TOGGLE AUTO_ N_RETRIES[1:0] AUTO_ RETRY SOFTRES ET FUSB302B Table 16. REGISTER DEFINITIONS (Notes 8 and 9) Address Register Name Type Reg Value 0x0A Mask1 R/W 0 0x0B Power R/W 1 0x0C Reset W/C 0 0x0D OCPreg R/W 0F 0x0E Maska R/W 0 0x0F Maskb R/W 0 M_ GCRCSEN T 0x10 Control4 R/W 0 TOG_ EXIT_AUD 0x3C Status0a R 0 SOFTFAIL RETRY FAIL POWER3 POWER2 SOFTRST HARDRST 0x3D Status1a R 0 TOGSS3 TOGSS2 TOGSS1 RXSOP 2DB RXSOP 1DB RXSOP 0x3E Interrupta R/C 0 I_ SOFTFAIL I_RETRY FAIL I_HARD SENT I_TXSENT I_SOFT RST I_HARD RST 0x3F Interruptb R/C 0 0x40 Status0 R 0 VBUSOK ACTIVITY COMP CRC_CHK ALERT WAKE BC_LVL1 BC_LVL0 0x41 Status1 R 28 RXSOP2 RXSOP1 RX_ EMPTY RX_FULL TX_ EMPTY TX_FULL OVRTEMP OCP 0x42 Interrupt R/C 0 I_VBUSOK I_ ACTIVITY I_COMP_ CHNG I_CRC_ CHK I_ALERT I_WAKE I_ COLLISION I_BC_LVL 0x43 FIFOs R/W (Note 10) 0 Type C Bits USB PD Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 M_ VBUSOK M_ ACTIVITY M_COMP_ CHNG M_CRC_C HK M_ALERT M_WAKE M_ COLLISION M_BC_LVL PWR3 PWR2 PWR1 PWR0 PD_ RESET SW_RES M_OCP_ TEMP I_OCP_ TEMP M_ TOGDONE I_ TOGDONE M_SOFT FAIL M_RETRY FAIL OCP_ RANGE OCP_ CUR2 OCP_ CUR1 OCP_ CUR0 M_HARD SENT M_ TXSENT M_ SOFTRST M_ HARDRST I_GCRCS ENT Write to TX FIFO or read from RX FIFO repeatedly without address auto increment General Bits 8. Do not use registers that are blank. 9. Values read from undefined register bits are not defined and invalid. Do not write to undefined registers. 10. FIFO register is serially read/written without auto address increment. 11. Automotive Part Only; FUSB302BVMPX Table 17. DEVICE ID (Address: 01h; Reset Value: 0x1001_XXXX; Type: Read) Bit # Name R/W/C Size (Bits) 7:4 Version ID R 4 Device version ID by Trim or etc. A_[Revision ID]: 1000 (e.g. A_revA) B_[Revision ID]: 1001 C_[Revision ID]: 1010 etc 3:2 Product ID R 2 “01”, “10” and “11” applies to MLP only: 00: FUSB302BMPX/FUSB302BVMPX(Default) & FUSB302BUCX 01: FUSB302B01MPX 10: FUSB302B10MPX 11: FUSB302B11MPX 1:0 Revision ID R 2 Revision History of each version [Version ID]_revA: 00(e.g. revA) [Version ID]_revB: 01 (e.g. revB) [Version ID]_revC: 10 (e.g. revC) [Version ID]_revC: 11 (e.g. revD) Description www.onsemi.cn 19 FUSB302B Table 18. SWITCHES0 (Address: 02h; Reset Value: 0x0000_0011; Type: Read/Write) Bit # Name R/W/C Size (Bits) Description 7 PU_EN2 R/W 1 1: Apply host pull up current to CC2 pin 6 PU_EN1 R/W 1 1: Apply host pull up current to CC1 pin 5 VCONN_CC2 R/W 1 1: Turn on the VCONN current to CC2 pin 4 VCONN_CC1 R/W 1 1: Turn on the VCONN current to CC1 pin 3 MEAS_CC2 R/W 1 1: Use the measure block to monitor or measure the voltage on CC2 2 MEAS_CC1 R/W 1 1: Use the measure block to monitor or measure the voltage on CC1 1 PDWN2 R/W 1 1: Device pull down on CC2. 0: no pull down 0 PDWN1 R/W 1 1: Device pull down on CC1. 0: no pull down Table 19. SWITCHES1 (Address: 03h; Reset Value: 0x0010_0000; Type: Read/Write) Bit # Name R/W/C Size (Bits) Description 7 POWERROLE R/W 1 Bit used for constructing the GoodCRC acknowledge packet. This bit corresponds to the Port Power Role bit in the message header if an SOP packet is received: 1: Source if SOP 0: Sink if SOP 6:5 SPECREV1: SPECREV0 R/W 2 Bit used for constructing the GoodCRC acknowledge packet. These bits correspond to the Specification Revision bits in the message header: 00: Revision 1.0 01: Revision 2.0 10: Do Not Use 11: Do Not Use 4 DATAROLE R/W 1 Bit used for constructing the GoodCRC acknowledge packet. This bit corresponds to the Port Data Role bit in the message header. For SOP: 1: SRC 0: SNK 3 Reserved N/A 1 Do Not Use 2 AUTO_CRC R/W 1 1: 0: Starts the transmitter automatically when a message with a good CRC is received and automatically sends a GoodCRC acknowledge packet back to the relevant SOP* Feature disabled 1 TXCC2 R/W 1 1: Enable BMC transmit driver on CC2 pin 0 TXCC1 R/W 1 1: Enable BMC transmit driver on CC1 pin www.onsemi.cn 20 FUSB302B Table 20. MEASURE (Address: 04h; ·Reset Value: 0x0011_0001; Type: Read/Write) Bit # Name R/W/C Size (Bits) Description 7 Reserved N/A 1 Do Not Use 6 MEAS_VBUS R/W 1 0: 1: 5:0 MDAC[5:0] R/W 6 MDAC/comparator measurement is controlled by MEAS_CC* bits Measure VBUS with the MDAC/comparator. This requires MEAS_CC* bits to be 0 Measure Block DAC data input. LSB is equivalent to 42 mV of voltage which is compared to the measured CC voltage. The measured CC is selected by MEAS_CC2, or MEAS_CC1 bits. MDAC[5:0] MEAS_VBUS = 0 MEAS_VBUS = 1 Unit 00_0000 0.042 0.420 V 00_0001 0.084 0.840 V 11_0000 2.058 20.58 V 11_0011 2.184 21.84 V 11_1110 2.646 26.46 V 11_1111 > 2.688 26.88 V Table 21. SLICE (Address: 05h; Reset Value: 0x0110_0000; Type: Read/Write) Bit # Name R/W/C Size (Bits) Description 7:6 SDAC_HYS[1:0] R/W 2 Adds hysteresis where there are now two thresholds, the lower threshold which is always the value programmed by SDAC[5:0] and the higher threshold that is: 11: 255 mV hysteresis: higher threshold = (SDAC value + 20hex) 10: 170 mV hysteresis: higher threshold = (SDAC value + Ahex) 01: 85 mV hysteresis: higher threshold = (SDAC value + 5) 00: No hysteresis: higher threshold = SDAC value 5:0 SDAC[5:0] R/W 6 BMC Slicer DAC data input. Allows for a programmable threshold so as to meet the BMC receive mask under all noise conditions. Table 22. CONTROL0 (Address: 06h; Reset Value: 0x0010_0100; Type: (see column below)) Bit # Name R/W/C Size (Bits) 7 Reserved N/A 1 Do Not Use 6 TX_FLUSH W/C 1 1: Self clearing bit to flush the content of the transmit FIFO 5 INT_MASK R/W 1 1: 0: Mask all interrupts Interrupts to host are enabled 4 Reserved N/A 1 Do Not Use 3:2 HOST_CUR[1:0] R/W 2 1: 00: 01: 10: 11: Controls the host pull up current enabled by PU_EN[2:1]: No current 80 mA – Default USB power 180 mA – Medium Current Mode: 1.5 A 330 mA – High Current Mode: 3 A 1 AUTO_PRE R/W 1 1: Starts the transmitter automatically when a message with a good CRC is received. This allows the software to take as much as 300 mS to respond after the I_CRC_CHK interrupt is received. Before starting the transmitter, an internal timer waits for approximately 170 mS before executing the transmit start and preamble Feature disabled Description 0: 0 TX_START W/C 1 1: Start transmitter using the data in the transmit FIFO. Preamble is started first. During the preamble period the transmit data can start to be written to the transmit FIFO. Self clearing. www.onsemi.cn 21 FUSB302B Table 23. CONTROL1 (Address: 07h; Reset Value: 0x0000_0000; Type: (see column below)) Bit # Name R/W/C Size (Bits) Description 7 Reserved N/A 1 Do Not Use 6 ENSOP2DB R/W 1 1: 0: Enable SOP”_DEBUG (SOP double prime debug) packets Ignore SOP”_DEBUG (SOP double prime debug) packets 5 ENSOP1DB R/W 1 1: 0: Enable SOP‘_DEBUG (SOP prime debug) packets Ignore SOP‘_DEBUG (SOP prime debug) packets 4 BIST_MODE2 R/W 1 1: Sent BIST Mode 01s pattern for testing 3 Reserved N/A 1 Do Not Use 2 RX_FLUSH W/C 1 1: Self clearing bit to flush the content of the receive FIFO 1 ENSOP2 R/W 1 1: 0: Enable SOP”(SOP double prime) packets Ignore SOP”(SOP double prime) packets 0 ENSOP1 R/W 1 1: 0: Enable SOP‘(SOP prime) packets Ignore SOP‘(SOP prime) packets Table 24. CONTROL2 (Address: 08h; Reset Value: 0x0000_0010; Type: (see column below)) Bit # Name R/W/C Size (Bits) Description 7:6 TOG_SAVE_PWR2: TOG_SAVE_PWR1 N/A 2 00: 01: 10: 11: Don’t go into the DISABLE state after one cycle of toggle Wait between toggle cycles for tDIS time of 40 ms Wait between toggle cycles for tDIS time of 80 ms Wait between toggle cycles for tDIS time of 160 ms 5 TOG_RD_ONLY R/W 1 1: When TOGGLE=1 only Rd values will cause the TOGGLE state machine to stop toggling and trigger the I_TOGGLE interrupt When TOGGLE=1, Rd and Ra values will cause the TOGGLE state machine to stop toggling 0: 4 Reserved N/A 1 Do Not Use 3 WAKE_EN R/W 1 1: 0: Enable Wake Detection functionality if the power state is correct Disable Wake Detection functionality 2:1 MODE R/W 2 11: 10: 01: 00: Enable SRC polling functionality if TOGGLE=1 Enable SNK polling functionality if TOGGLE=1 Enable DRP polling functionality if TOGGLE=1 Do Not Use 0 TOGGLE R/W 1 1: 0: Enable DRP, SNK or SRC Toggle autonomous functionality Disable DRP, SNK and SRC Toggle functionality www.onsemi.cn 22 FUSB302B Table 25. CONTORL3 (Address: 09h; Reset Value: 0x0000_0110; Type: (see column below)) Bit # Name R/W/C Size (Bits) Description 7 Reserved N/A 1 Do Not Use 6 SEND_HARD_RESET W/C 1 1: 0: Send a hard reset packet (highest priority) Don’t send a soft reset packet 5 BIST_TMODE R/W 1 1: 0: BIST mode. Receive FIFO is cleared immediately after sending GoodCRC response Normal operation, All packets are treated as usual 4 AUTO_HARDRESET R/W 1 1: 0: Enable automatic hard reset packet if soft reset fail Disable automatic hard reset packet if soft reset fail 3 AUTO_SOFTRESET R/W 1 1: 0: Enable automatic soft reset packet if retries fail Disable automatic soft reset packet if retries fail 2:1 N_RETRIES[1:0] R/W 2 11: 10: 01: 00: Three retries of packet (four total packets sent) Two retries of packet (three total packets sent) One retry of packet (two total packets sent) No retries (similar to disabling auto retry) 0 AUTO_RETRY R/W 1 1: 0: Enable automatic packet retries if GoodCRC is not received Disable automatic packet retries if GoodCRC not received Table 26. MASK (Address: 0Ah; Reset Value: 0x0000_0000; Type: Read/Write) Bit # Name R/W/C Size (Bits) Description 7 M_VBUSOK R/W 1 1: 0: Mask I_VBUSOK interrupt bit Do not mask 6 M_ACTIVITY R/W 1 1: 0: Mask interrupt for a transition in CC bus activity Do not mask 5 M_COMP_CHNG R/W 1 1: 0: Mask I_COMP_CHNG interrupt for change is the value of COMP, the measure comparator Do not mask 4 M_CRC_CHK R/W 1 1: 0: Mask interrupt from CRC_CHK bit Do not mask 3 M_ALERT R/W 1 1: 0: Mask the I_ALERT interrupt bit Do not mask 2 M_WAKE R/W 1 1: 0: Mask the I_WAKE interrupt bit Do not mask 1 M_COLLISION R/W 1 1: 0: Mask the I_COLLISION interrupt bit Do not mask 0 M_BC_LVL R/W 1 1: 0: Mask a change in host requested current level Do not mask Table 27. POWER (Address: 0Bh; Reset Value: 0x0000_0001; Type: Read/Write) Bit # Name R/W/C Size (Bits) Description 7:4 Reserved N/A 4 Do Not Use 3:0 PWR[3:0] R/W 4 Power enables: PWR[0]: Bandgap and wake circuit PWR[1]: Receiver powered and current references for Measure block PWR[2]: Measure block powered PWR[3]: Enable internal oscillator www.onsemi.cn 23 FUSB302B Table 28. RESET (Address: 0Ch; Reset Value: 0x0000_0000; Type: Write/Clear) Bit # Name R/W/C Size (Bits) Description 7:2 Reserved N/A 6 Do Not Use 1 PD_RESET W/C 1 1: Reset just the PD logic for both the PD transmitter and receiver 0 SW_RES W/C 1 1: Reset the FUSB302B including the I2C registers to their default values Table 29. OCPREG (Address: 0Dh; Reset Value: 0x0000_1111; Type: Read/Write) Bit # Name R/W/C Size (Bits) 7:4 Reserved N/A 4 Do Not Use 3 OCP_RANGE R/W 1 1: 0: 2:0 OCP_CUR2, OCP_CUR1, OCP_CUR0 R/W 3 111: max_range (see bit definition above for OCP_RANGE) 110: 7 × max_range / 8 101: 6 × max_range / 8 100: 5 × max_range / 8 011: 4 × max_range / 8 010: 3 × max_range / 8 001: 2 × max_range / 8 000: max_range / 8 Description OCP range between 100−800 mA (max_range = 800 mA) OCP range between 10−80 mA (max_range = 80 mA) Table 30. MASKA (Address: 0Eh; Reset Value: 0x0000_0000; Type: Read/Write) Bit # Name R/W/C Size (Bits) Description 7 M_OCP_TEMP R/W 1 1: Mask the I_OCP_TEMP interrupt 6 M_TOGDONE R/W 1 1: Mask the I_TOGDONE interrupt 5 M_SOFTFAIL R/W 1 1: Mask the I_SOFTFAIL interrupt 4 M_RETRYFAIL R/W 1 1: Mask the I_RETRYFAIL interrupt 3 M_HARDSENT R/W 1 1: Mask the I_HARDSENT interrupt 2 M_TXSENT R/W 1 1: Mask the I_TXSENT interrupt 1 M_SOFTRST R/W 1 1: Mask the I_SOFTRST interrupt 0 M_HARDRST R/W 1 1: Mask the I_HARDRST interrupt Table 31. MASKB (Address: 0Fh; Reset Value: 0x0000_0000; Type: Read/Write) Bit # Name R/W/C Size (Bits) Description 7:1 Reserved N/A 6 Do Not Use 0 M_GCRCSENT R/W 1 1: Mask the I_GCRCSENT interrupt Table 32. CONTROL4 (Address: 00h; Reset Value: 0x0000_0000; Type: Read/Write) Bit # Name R/W/C Size (Bits) Description 7:1 Reserved N/A 6 Do Not Use 0 TOG_EXIT_AUD R/W 1 1: In auto Rd only Toggle mode, stop Toggle at Audio accessory (Ra on both CC) www.onsemi.cn 24 FUSB302B Table 33. STATUS0A (Address: 3Ch; Reset Value: 0x0000_0000; Type: Read) Bit # Name R/W/C Size (Bits) Description 7:6 Reserved N/A 2 Do Not Use 5 SOFTFAIL R 1 1: All soft reset packets with retries have failed to get a GoodCRC acknowledge. This status is cleared when a START_TX, TXON or SEND_HARD_RESET is executed 4 RETRYFAIL R 1 1: All packet retries have failed to get a GoodCRC acknowledge. This status is cleared when a START_TX, TXON or SEND_HARD_RESET is executed 3:2 POWER3:POWER2 R 2 Internal power state when logic internals needs to control the power state. POWER3 corresponds to PWR3 bit and POWER2 corresponds to PWR2 bit. The power state is the higher of both PWR[3:0] and {POWER3, POWER2, PWR[1:0]} so that if one is 03 and the other is F then the internal power state is F 1 SOFTRST R 1 1: One of the packets received was a soft reset packet 0 HARDRST R 1 1: Hard Reset PD ordered set has been received Table 34. STATUS1A (Address: 3Dh; Reset Value: 0x0000_0000; Type: Read) Bit # Name R/W/C Size (Bits) Description 7:6 Reserved N/A 2 Do Not Use 5:3 TOGSS3, TOGSS2, TOGSS1 R 3 000: Toggle logic running (processor has previously written TOGGLE=1) 001: Toggle functionality has settled to SRCon CC1 (STOP_SRC1 state) 010: Toggle functionality has settled to SRCon CC2 (STOP_SRC2 state) 101: Toggle functionality has settled to SNKon CC1 (STOP_SNK1 state) 110: Toggle functionality has settled to SNKon CC2 (STOP_SNK2 state) 111: Toggle functionality has detected AudioAccessory with vRa on both CC1 and CC2 (settles to STOP_SRC1 state) Otherwise: Not defined (do not interpret) 2 RXSOP2DB R 1 1: Indicates the last packet placed in the RxFIFO is type SOP”_DEBUG (SOP double prime debug) 1 RXSOP1DB R 1 1: Indicates the last packet placed in the RxFIFO is type SOP’_DEBUG (SOP prime debug) 0 RXSOP R 1 1: Indicates the last packet placed in the RxFIFO is type SOP www.onsemi.cn 25 FUSB302B Table 35. INTERRUPTA (Address: 3Eh; Reset Value: 0x0000_0000; Type: Read/Clear) Bit # Name R/W/C Size (Bits) Description 7 I_OCP_TEMP R/C 1 1: Interrupt from either a OCP event on one of the VCONN switches or an over-temperature event 6 I_TOGDONE R/C 1 1: Interrupt indicating the TOGGLE functionality was terminated because a device was detected 5 I_SOFTFAIL R/C 1 1: Interrupt from automatic soft reset packets with retries have failed 4 I_RETRYFAIL R/C 1 1: Interrupt from automatic packet retries have failed 3 I_HARDSENT R/C 1 1: Interrupt from successfully sending a hard reset ordered set 2 I_TXSENT R/C 1 1: Interrupt to alert that we sent a packet that was acknowledged with a GoodCRC response packet 1 I_SOFTRST R/C 1 1: Received a soft reset packet 0 I_HARDRST R/C 1 1: Received a hard reset ordered set Table 36. INTERRUPTB (Address: 3Fh; Reset Value: 0x0000_0000; Type: Read/Clear) Bit # Name R/W/C Size (Bits) Description 7 Reserved N/A 6 Do Not Use 0 I_GCRCSENT R/C 1 1: Sent a GoodCRC acknowledge packet in response to an incoming packet that has the correct CRC value www.onsemi.cn 26 FUSB302B Table 37. STATUS0 (Address: 40h; Reset Value: 0x0000_0000; Type: Read) Bit # Name R/W/C Size (Bits) Description 7 VBUSOK R 1 1: Interrupt occurs when VBUS transitions through vVBUSthr. This bit typically is used to recognize port partner during startup 6 ACTIVITY R 1 1: Transitions are detected on the active CC* line. This bit goes high after a minimum of 3 CC transitions, and goes low with no Transitions Inactive 5 COMP R 1 0: 1: 0: 4 CRC_CHK R 1 1: 0: Measured CC* input is higher than reference level driven from the MDAC Measured CC* input is lower than reference level driven from the MDAC Indicates the last received packet had the correct CRC. This bit remains set until the SOP of the next packet Packet received for an enabled SOP* and CRC for the enabled packet received was incorrect 3 ALERT R 1 1: Alert software an error condition has occurred. An alert is caused by: TX_FULL: the transmit FIFO is full RX_FULL: the receive FIFO is full See Status1 bits 2 WAKE R 1 1: 0: Voltage on CC indicated a device attempting to attach WAKE either not enabled (WAKE_EN=0) or no device attached 1:0 BC_LVL[1:0] R 2 Current voltage status of the measured CC pin interpreted as host current levels as follows: 00: < 200 mV 01: > 200 mV, < 660 mV 10: > 660 mV, < 1.23 V 11: > 1.23 V Note the software must measure these at an appropriate time, while there is no signaling activity on the selected CC line. BC_LVL is only defined when Measure block is on which is when register bits PWR[2]=1 and either MEAS_CC1=1 or MEAS_CC2=1 Description Table 38. STATUS1 (Address: 41h; Reset Value: 0x0010_1000; Type: Read) Bit # Name R/W/C Size (Bits) 7 RXSOP2 R 1 1: Indicates the last packet placed in the RxFIFO is type SOP” (SOP double prime) 6 RXSOP1 R 1 1: Indicates the last packet placed in the RxFIFO is type SOP’ (SOP prime) 5 RX_EMPTY R 1 1: The receive FIFO is empty 4 RX_FULL R 1 1: The receive FIFO is full 3 TX_EMPTY R 1 1: The transmit FIFO is empty 2 TX_FULL R 1 1: The transmit FIFO is full 1 OVRTEMP R 1 1: Temperature of the device is too high 0 OCP R 1 1: Indicates an over-current or short condition has occurred on the VCONN switch www.onsemi.cn 27 FUSB302B Table 39. INTERRUPT (Address: 42h; Reset Value: 0x0000_0000; Type: Read/Clear) Bit # Name R/W/C Size (Bits) Description 7 I_VBUSOK R/C 1 1: Interrupt occurs when VBUS transitions through 4.5 V. This bit typically is used to recognize port partner during startup 6 I_ACTIVITY R/C 1 1: A change in the value of ACTIVITY of the CC bus has occurred 5 I_COMP_CHNG R/C 1 1: A change in the value of COMP has occurred. Indicates selected CC line has tripped a threshold programmed into the MDAC 4 I_CRC_CHK R/C 1 1: The value of CRC_CHK newly valid. I.e. The validity of the incoming packet has been checked 3 I_ALERT R/C 1 1: Alert software an error condition has occurred. An alert is caused by: TX_FULL: the transmit FIFO is full RX_FULL: the receive FIFO is full See Status1 bits 2 I_WAKE R/C 1 1: Voltage on CC indicated a device attempting to attach. Software must then power up the clock and receiver blocks 1 I_COLLISION R/C 1 1: When a transmit was attempted, activity was detected on the active CC line. Transmit is not done. The packet is received normally 0 I_BC_LVL R/C 1 1: A change in host requested current level has occurred Table 40. FIFOS (Address: 43h; Reset Value: 0x0000_0000; Type: (see column below)) Bit # Name R/W/C Size (Bits) Description 7:0 TX/RX Token Read or Write 8 Writing to this register writes a byte into the transmit FIFO. Reading from this register reads from the receive FIFO. Each byte is a coded token. Or a token followed by a fixed number of packed data byte (see token coding in Table 41) 软9 • • • :输34;< 端口+,种方式.端口q片;： I2C寄存器 发VFIFO寄存器或5FIFO寄存器接收的的8#数 据牌。 写'TxFIFO的所有