FUSB302MPX

FUSB302 Programmable USB Type-C Controller w/PD Features Description  Dual-Role Functionality with Autonomous DRP Toggle  Ability to connect as either a host or a device based on what has been attached.  Software configurable either as a dedicated host, dedicated device, or dual role. - Dedicated devices can operate both on a Type-C receptacle or a Type-C plug with a fixed CC and VCONN channel.  Full Type-C 1.1 Support. Integrates the following functionality of the CC pin - Attach/Detach Detection as Host - Current Capability Indication as Host - Current Capability Detection as Device - Audio Adapter Accessory Mode - Debug Accessory Mode - Active Cable Detection  Integrates CCx to VCONN switch with over-current limiting for powering USB3.1 Full Featured cables.  USB Power Delivery (PD) 2.0, Version 1.1 Support The FUSB302 targets system designers looking to implement a DRP/SRC/SNK USB Type-C connector with low amount of programmability. The FUSB302 enables the USB Type-C detection including attach, and orientation. The FUSB302 integrates the physical layer of the USB BMC power delivery protocol to allow up to 100 W of power and role swap. The BMC PD block enables full support for alternative interfaces of the Type-C specification. Applications        Smartphones Tablets Laptops Notebooks Power Adapters Cameras Dongles - Automatic GoodCRC Packet Response - Automatic retries of sending a packet if a GoodCRC is not received - Automatic soft reset packet sent with retries if needed - Automatic Hard Reset Ordered Set Sent  Dead Battery Support (SNK Mode Support when No Power Applied)   Low Power Operation: ICC = 25 μA (Typical) Packaged in 9-Ball WLCSP (1.215 mm x 1.260 mm) and 14-lead MLP (2.5 mm x 2.5 mm, 0.5 mm Pitch) Figure 1. Block Diagram Ordering Information Part Number FUSB302UCX Operating Temperature Range -40 to 85°C FUSB302MPX © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 Package 9-Ball Wafer-Level Chip Scale Package (WLCSP), 0.4 mm Pitch Packing Method Tape and Reel 14-Lead MLP 2.5 mm x 2.5 mm, 0.5 mm Pitch www.fairchildsemi.com www.onsemi.com FUSB302 — Programmable USB Type-C Controller w/PD July 2017 BATTERY V3P3 PMIC [Charger + VCONN Buck] VBUS V3P3 VBUS VCONN VDD FUSB302 USB PD BMC TYPE-C GND RX2+ TX2+ RX2- TX2VBUS RFU1 CC2 DD+ D+ DCC1 RFU2 VBUS TX1- RX1TX1+ RX1+ GND INT_N SDA SCL I2C/ Registers CC Level Control CC2/VCONN2 CC1/VCONN1 Dual-Role Detection CC and VCONN Switch Block Logic & Control Auto Toggle Switch matrix CC detection/control Powered cable Auto Adapter/Debug Acc DAC comparator Processor GND GND USB_3.11 USB_3.12 Figure 2. USB PHY FUSB340 (USB 3.1 2:1 Switch) Typical Application FUSB302 — Programmable USB Type-C Controller w/PD Typical Application Block Diagram VCONN VBUS CC1 FUSB302 Processor (Software) Type-C Connection States : - SOURCE - SINK - SINK with Accessory Support - Dual-Role Port - Dual-Role Port with Accessory Support Control Settings Comp. Status RD CC2 Type-C Switch Settings DAC INT_N SDA SCL PD (Provider/Consumer) PD/ VDM Device Policy Manager I2C Reg PD Configuration PD Status RD Code/ Control Logic Protocol Figure 3. © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 FIFO CRC32 Tx FIFO CRC32 Rx FIFO Access 4B5B BMC DRIVER Policy Engine BMC BMC Physical Layer 4B5B BMC CDR Functional Block Diagram 2 www.fairchildsemi.com www.onsemi.com FUSB302 — Programmable USB Type-C Controller w/PD Pin Configuration 1 2 3 A B C Figure 4. CC2 VBUS VDD VCONN INT_N SCL CC1 GND SDA FUSB302UCX Pin Assignment (Top Through View) Pin Map Column 1 Column 2 Column 3 Row A CC2 VBUS VDD Row B VCONN INT_N SCL Row C CC1 GND SDA 11 CC1 11 CC1 14 CC2 13 VCONN 12 VCONN 1 CC2 TOP THROUGH VIEW 2 VBUS 3 VDD 10 CC1 10 CC1 9 GND 9 GND 8 GND 8 GND 5 INT_N 6 SCL Figure 5. © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 7 SDA 14 CC2 1 CC2 BOTTOM VIEW 2 VBUS 3 VDD N/C N/C 4 VDD 13 VCONN 12 VCONN 7 SDA 6 SCL 5 INT_N 4 VDD FUSB302MPX Pin Assignment (N/C = No Connect) 3 www.fairchildsemi.com www.onsemi.com Name Type Description USB Type-C Connector Interface CC1/CC2 I/O GND Ground VBUS Input Type-C connector Configuration Channel (CC) pins. Initially used to determine when an attach has occurred and what the orientation of the insertion is. Functionality after attach depends on mode of operation detected. Operating as a host: 1. Sets the allowable charging current for VBUS to be sensed by the attached device 2. Used to communicate with devices using USB BMC Power Delivery 3. Used to detect when a detach has occurred Operating as a device: 1. Indicates what the allowable sink current is from the attached host. -Used to communicate with devices using USB BMC Power Delivery Ground VBUS input pin for attach and detach detection when operating as an upstream facing port (Device). Expected to be an OVP protected input. Power Interface VDD Power VCONN Power Switch Input supply voltage. Regulated input to be switched to correct CC pin as VCONN to power USB3.1 fullfeatured cables and other accessories Signal Interface I2C serial clock signal to be connected to the phone-based I2C master. SCL Input SDA Open-Drain I/O I2C serial data signal to be connected to the phone-based I2C master INT_N Open-Drain Output Active LOW open drain interrupt output used to prompt the processor to read the I2C register bits © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 4 FUSB302 — Programmable USB Type-C Controller w/PD Pin Descriptions www.fairchildsemi.com www.onsemi.com The FUSB302 integrates the control and detection functionality required to implement a USB Type-C host, device or dual-role port including:    VCONN Power Switch with OCP for Full-Featured USB3.1 Cables   USB BMC Power Delivery Physical Layer Configuration Channel (CC) Threshold Comparators. Each CC pin contains a flexible switch matrix that allows the host software to control what type of Type-C port is implemented. The switches are shown in Figure 6. Device Port Pull-Down(RD) Host Port Pull-Up (IP) CCX VCONN VCONN_CCx Reg VCONN_SWITCH MEAS_CCx Reg DAC/ Comparator MEAS_CC_SWITCH TXCCx Reg BMC I/O TX_BMC_SWITCH PU_ENx Reg Current Source Pull-ups PWDNx Reg Figure 6. FUSB302 — Programmable USB Type-C Controller w/PD Configuration Channel Switch PULLUP_SWITCH PULLDOWN_SWITCH 5.1K Configuration Channel Switch Functionality Type-C Detection Detection through Autonomous Device Toggle The FUSB302 implements multiple comparators and a programmable DAC that can be used by software to determine the state of the CC and VBUS pins. This status information provides the processor all of the information required to determine attach, detach and charging current configuration of the Type-C port connection. The FUSB302 has the capability to do autonomous DRP toggle. In autonomous toggle the FUSB302 internally controls the PDWN1, PDWN2, PU_EN1 and PU_EN2, MEAS_CC1 and MEAS_CC2 and implements a fixed DRP toggle between presenting as a SRC and presenting as a SNK. Alternately, it can present as a SRC or SNK only and poll CC1 and CC2 continuously. The FUSB302 has three fixed threshold comparators that match the USB Type-C specification for the three charging current levels that can be detected by a TypeC device. These comparators automatically cause BC_LVL and COMP interrupts to occur when there is a change of state. In addition to the fixed threshold comparators, the host software can use the 6-bit DAC to determine the state of the CC lines more accurately. The FUSB302 also has a fixed comparator that monitors if VBUS has reached a valid threshold or not. The DAC can be used to measure VBUS up to 20 V which allows the software to confirm that changes to the VBUS line have occurred as expected based on PD or other communication methods to change the charging level. © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 5 www.fairchildsemi.com www.onsemi.com I2C Registers / Bits Manual Device Toggle The FUSB302 has the capability to do manual DRP toggle. In manual toggle the FUSB302 is configurable by the processor software by I2C and setting TOGGLE = 0. Value TOGGLE 1 PWR 07H HOST_CUR0 1 HOST_CUR1 0 MEAS_VBUS 0 VCONN_CC1 0 VCONN_CC2 0 Mask Register 0xFE Maska Register 0xBF Maskb Register (Except I_TOGDONE and I_BC_LVL Interrupt) 0x01 PWR[3:0] 0x07 Manual Device Detection and Configuration A Type-C device must monitor VBUS to determine if it is attached or detached. The FUSB302 provides this information through the VBUSOK interrupt. After the Type-C device knows that a Type-C host has been attached, it needs to determine what type of termination is applied to each CC pin. The software determines if an Ra or Rd termination is present based on the BC_LVL and COMP interrupt and status bits. Additionally, for Rd terminations, the software can further determine what charging current is allowed by the Type-C host by reading the BC_LVL status bits. This is summarized in Table 2. Toggle Functionality When TOGGLE bit (Control2 register) is set the FUSB302 implements a fixed DRP toggle between presenting as a SRC and as a SNK. It can also be configured to present as a SRC only or SNK only and poll CC1 and CC2 continuously. This operation is turned on with TOGGLE=1 and the processor should initially write HOST_CUR1=0, HOST_CUR0=1 (for default current), VCONN_CC1=VCONN_CC2=0, Mask Register=0xFE, Maska register=0xBF, and Maskb register=0x01, and PWR=0x01. The processor should also read the interrupt register to clear them prior to setting the TOGGLE bit. Notes: 1. Once it has been determined what the role is of the FUSB302, it returns I_TOGDONE and TOGSS1/2. 2. Processor then can perform a final manual check through I2C. Table 2. FUSB302 — Programmable USB Type-C Controller w/PD Table 1. Processor Configures the FUSB302 through I2C: Device Interrupt Summary Status Type Interrupt Status Meaning BC_LVL[1:0] COMP COMP Setting VBUSOK 2'b00 NA NA 1 vRA 2'b01 NA NA 1 vRd-Connect and vRd-USB 2'b10 NA NA 1 vRd-Connect and vRd-1.5 2'b11 0 6'b11_0100 (2.226 V) 1 vRd-Connect and vRd-3.0 Attach NA NA NA 1 Host Attached, VBUS Valid Detach NA NA NA 0 Host Detached, VBUS Invalid CC Detection © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 6 www.fairchildsemi.com www.onsemi.com The FUSB302 allows the host software to change the charging current capabilities of the port through the HOST_CUR control bits. If the HOST_CUR bits are changed prior to attach, the FUSB302 automatically indicates the programmed current capability when a device is attached. If the current capabilities are changed after a device is attached, the FUSB302 immediately changes the CC line to the programmed capability. Disabled: FUSB302 in low power mode looking for an attach FUSB302 I_TOGDONE interrupt alerts host software that something has attached. ATTACH CC Unattached.SNK: Host software enables FUSB302 pull-downs and measure block to detect attach FUSB302 I_VBUSOK interrupt alerts host software that a detach has occurred 0V HOST_CUR[1:0] = DEFAULT FUSB302 I_VBUSOK interrupt alerts host software that an attach has occurred Figure 8. MED CURRENT SETTING HIGH CURRENT SETTING HOST_CUR Changed After Attach ATTACH Attached.SNK Host software uses FUSB302 comparators and DAC to determine attach orientation and port type CC 0V HIGH CURRENT SETTING Figure 9. Host software determines that an accessory has been attached DebugAccessory DEFAULT CURRENT HOST_CUR Changed Prior To Attach The Type-C specification outlines different attach and detach thresholds for a Type-C host that are based on how much current is supplied to each CC pin. Based on the programmed HOST_CUR setting, the software adjusts the DAC comparator threshold to match the Type-C specification requirements. The BC_LVL comparators can also be used as part of the Ra detection flow. This is summarized in Table 3. AudioAccessory FUSB302 I_COMP and I_VBUSOK interrupts alert host software that a accessory detach has occurred Figure 7. MED CURRENT SETTING SNK Software Flow FUSB302 — Programmable USB Type-C Controller w/PD The high level software flow diagram for a Type-C device (SNK) is shown in Figure 7. Manual Host Detection and Configuration When the FUSB302 is configured as a Type-C host, the software can use the status of the comparators and DAC to determine when a Type-C device has been attached or detached and what termination type has been attached to each CC pin. Table 3. Host Interrupt Summary Termination Ra HOST_CUR[1:0] Interrupt Status COMP 2'b01 2'b00 NA NA 2'b10 2'b01 0 6'b00_1001 (0.42 V) 2'b11 2'b10 0 6'b01_0010 (0.8 V) NA 0 6'b10_0101 (1.6 V) Attach NA 1 6'b10_0101 (1.6 V) Detach NA 0 6'b11_1101 (2.6 V) Attach NA 1 6'b11_1101 (2.6 V) Detach 2'b01, 2'b10 Rd 2'b11 © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 7 COMP Setting Attach/Detach BC_LVL[1:0] NA www.fairchildsemi.com www.onsemi.com Disabled: FUSB302 in low power mode looking for an attach FUSB302 I_TOGDONE interrupt alerts host software that something has attached. Unattached.SRC: Host software enables FUSB302 pull-ups and measure block to detect attach Host software utilizes I_COMP and I_BC_LVL interrupts to determine an attach and what type of port is attached. FUSB302 I_COMP interrupt alerts host software that a detach has occurred Attached.SRC Host software configures FUSB302 based on insertion orientation and enables VBUS and VCONN AudioAccessory DebugAccessory FUSB302 — Programmable USB Type-C Controller w/PD The high level software flow diagram for a Type-C Host (SRC) is shown below in Figure 10. FUSB302 I_COMP and I_VBUSOK interrupts alert host software that a accessory detach has occurred Figure 10. © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 SRC Software Flow 8 www.fairchildsemi.com www.onsemi.com The Type-C specification allows ports to be both a device and a host depending on what type of port has attached. This functionality is similar to USB OTG ports with the current USB connectors and is called a dual- Disabled: FUSB302 in low power mode looking for an attach FUSB302 I_TOGONE interrupt alerts host software that something has attached. Host software enables FUSB302 low power Disabled state Unattached.SNK: Host software enables FUSB302 pull-downs and measure block to detect attach Host software toggle expires FUSB302 I_VBUSOK interrupt alerts host software that an attach has occurred FUSB302 I_VBUSOK interrupt alerts host software that a detach has occurred Host software utilizes I_COMP and I_BC_LVL interrupts to determine an attach DRP Software Flow The FUSB302 uses tokens to control the transmission of BMC PD packets. These tokens are written to the transmit FIFO and control how the packet is transmitted on the CC pin. The tokens are designed to be flexible and support all aspects of the USB PD specification. The FUSB302 additionally enables control of the BMC transmitter through tokens. The transmitter can be enabled or disabled by specific token writes which allow faster packet processing by burst writing the FIFO with all the information required to transmit a packet. BMC Power Delivery The Type-C connector allows USB Power Delivery (PD) to be communicated over the connected CC pin between two ports. The communication method is the BMC Power Delivery protocol and is used for many different reasons with the Type-C connector. Possible uses are outlined below.    Negotiating and controlling charging power levels  Role swap for dual-role ports that want to switch who is the host or device Alternative Interfaces such as MHL, Display Port The FUSB302 receiver stores the received data and the received CRC in the receive FIFO when a valid packet is received on the CC pin. The BMC receiver automatically enables the internal oscillator when activity is sensed on the CC pin and load the FIFO when a packet is received. The I_ACTIVITY and I_CRC_CHK interrupts alert the host software that a valid packet was received. Vendor specific interfaces for use with custom docks or accessories  Communication with USB3.1 full featured cables The FUSB302 integrates a thin BMC PD client which includes the BMC physical layer and packet FIFOs (48 bytes for transmit and 80 bytes for receive) which allows packets to be sent and received by the host software through I2C accesses. The FUSB302 allows host software to implement all features of USB BMC PD through writes and reads of the FIFO and control of the FUSB302 physical interface. © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 FUSB302 I_COMP interrupt alerts host software that a detach has occurred Attached.SRC Host software configures FUSB302 based on insertion orientation and enables VBUS and VCONN Attached.SNK Host software uses FUSB302 comparators and DAC to determine attach orientation and port type Figure 11. Unattached.SRC: Host software enables FUSB302 pull-ups and measure block to detect attach FUSB302 — Programmable USB Type-C Controller w/PD role port. The FUSB302 can be used to implement a dual-role port. A Type-C dual role port toggles between presenting as a Type-C device and a Type-C host. The host software controls the toggle time and configuration of the FUSB302 in each state as shown in Figure 11. Manual Dual-Role Detection and Configuration 9 www.fairchildsemi.com www.onsemi.com CC1 4B5B BMC BMC DRIVER FIFO CRC32 Tx CC2 FIFO CRC32 Rx 4B5B Figure 12. BMC CDR USB BMC Power Delivery Blocks If no power applied to VDD then the SRC can recognize the FUSB302 as a SNK. Power Level Determination The Type-C specification outlines the order of precedence for power level determination which covers power levels from basic USB2.0 levels to the highest levels of USB PD. The host software is expected to follow the USB Type-C specification for charging current priority based on feedback from the FUSB302 detection, external BC1.2 detection and any USB Power Delivery communication. PD Automatic Receive GoodCRC The power delivery packets require a GoodCRC acknowledge packet to be sent for each received packet where the calculated CRC is the correct value. This calculation is done by the FUSB302 and triggers the I_CRC_CHK interrupt if the CRC is good. If the AUTO_CRC (Switches1 register bit) is set and AUTO_PRE=0, then the FUSB302 will automatically send the GoodCRC control packet in response to alleviate the local processor from responding quickly to the received packet. If GoodCRC is required for anything beyond SOP, then enable SOP*. The FUSB302 does not integrate BC1.2 charger detection which is assumed available in the USB transceiver or USB charger in the system. Power Up, Initialization and Reset When power is first applied through VDD, the FUSB302 is reset and registers are initialized to the default values shown in the register map. FUSB302 — Programmable USB Type-C Controller w/PD Code/ Control Logic PD Send The FUSB302 implements part of the PD protocol layer for sending packets in an autonomous fashion. The FUSB302 can be reset through software by programming the SW_RES bit in the RESET register. PD Packet Sent Automatic Sending Retries Soft Reset Hard Reset If not, this Soft Reset packet is retried NRETRIES times (MessageID is always 0 for all retries) if a GoodCRC acknowledge packet is not received with CRCReceiveTimer expiring (tReceive of 1.1 ms max). If all retries fail, then I_SOFTFAIL interrupt is triggered. PD Automatic Sending Retries If GoodCRC packet is not received and AUTO_RETRY is set, then a retry of the same message that was in the TxFIFO written by the processor is executed within tRetry and that is repeated for NRETRY times. PD Send Soft Reset PD Send Hard Reset If the correct GoodCRC packet is still not received for all retries then I_RETRYFAIL interrupt is triggered and if AUTO_SOFT_RESET is set, then a Soft Reset packet is created (MessageID is set to 0 and the processor upon servicing I_RETRYFAIL would set the true MessageIDCounter to 0. If all retries of the soft reset packet fail and if AUTO_HARD_RESET is set, then a hard reset ordered set is sent by loading up the TxFIFO with RESET1, RESET1, RESET1, RESET2 and sending a hard reset. Note only one hard reset is sent since the typical retry mechanism doesn’t apply. The processor’s policy engine firmware is responsible for retrying the hard reset is it doesn’t receive the required response. If this Soft Reset is sent successfully where a GoodCRC control packet is received with a MessageID=0 then I_TXSENT interrupt occurs. © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 10 www.fairchildsemi.com www.onsemi.com The FUSB302 includes a full I2C slave controller. The I2C slave fully complies with the I2C specification version 6 requirements. This block is designed for Fast Mode Plus traffic up to 1 MHz SCL operation. 8bits 8bits The TOGGLE features allow for very low power operation with slow clocking thus may not be fully compliant to the 1 MHz operation. Examples of an I2C write and read sequence are shown in Figure 13 and Figure 14 respectively. 8bits S Slave Address WR A Register Address K A Write Data A Write Data K+1 A Write Data K+2 A Note: A P Single Byte read is initiated by Master with P immediately following first data byte Figure 13. I2C Write Example 8bits 8bits 8bits 8bits S Slave Address WR A Register Address K A S Slave Address RD A Register address to Read specified Note: Write Data K+N-1 Read Data K A Read Data K+1 A Read Data K+N-1 NA P Single or multi byte read executed from current register location (Single Byte read is initiated by Master with NA immediately following first data byte) If Register is not specified Master will begin read from current register. In this case only sequence showing in Red bracket is needed From Master to Slave From Slave to Master S A Start Condition Acknowledge (SDA Low) Figure 14. © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 NA NOT Acknowledge (SDA High) WR Write=0 I2C Read Example 11 RD P Read =1 Stop Condition FUSB302 — Programmable USB Type-C Controller w/PD I2C Interface www.fairchildsemi.com www.onsemi.com Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VvDD VCC_HDDRP VVBUS TSTORAGE Parameter Min. Max. Unit Supply Voltage from VDD -0.5 6.0 V CC pins when configured as Host, Device or Dual Role Port -0.5 6.0 V VBUS Supply Voltage -0.5 28.0 V Storage Temperature Range -65 +150 C TJ Maximum Junction Temperature +150 C TL Lead Temperature (Soldering, 10 Seconds) +260 C IEC 61000-4-2 System ESD ESD Human Body Model, ANSI/ESDA/JEDEC JS-001-2012 Charged Device Model, JEDEC JESD22-C101 Connector Pins (VBUS, CCx) Air Gap 15 Contact 8 kV All Pins 4 kV All Pins 1 kV Recommended Operating Conditions FUSB302 — Programmable USB Type-C Controller w/PD Absolute Maximum Ratings The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance. ON Semiconductor does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VVBUS VVDD Parameter VBUS Supply Voltage VDD Supply Voltage VVCONN VCONN Supply Voltage IVCONN VCONN Supply Current TA Operating Temperature Min. Typ. Max. Unit 4.0 5.0 21.0 V 2.8(3) 3.3 5.5 V 5.5 V 560 mA +85 C 2.7 -40 Note: 3. This is for functional operation only and not the lowest limit for all subsequent electrical specifications below. All electrical parameters have a minimum of 3.0 V operation. © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 12 www.fairchildsemi.com www.onsemi.com All typical values are at TA=25°C unless otherwise specified. Baseband PD Symbol UI TA=-40 to +85°C TJ=-40 to +125°C Parameter Unit Interval Unit Min. Typ. Max. 3.03 3.70 µs 79 Ω 23 µs Transmitter rOutput TX Output Resistance 21 tEndDriveBMC Time to Cease Driving the Line after the end of the last bit of the Frame tHoldLowBMC Time to Cease Driving the Line after the final High-to-Low Transition 50 1 µs VOH Logic High Voltage 1.05 1.20 V VOL Logic Low Voltage 0 75 mV tStartDrive Time before the start of the first bit of the preamble when the transmitter shall start driving the line -1 1 µs tRISE_TX Rise Time 300 ns tFALL_TX Fall Time 300 ns Receiver cReceiver zBmcRx Receiver Capacitance when Driver isn’t Turned On Receiver Input Impedance 50 pF 1 MΩ vSDACstep BMC Receiver SDAC step size for each code in SDAC[5:0] register 17 mV vSDAChys BMC Receiver SDAC hysteresis for each code over the SDAC range (SDAC_HYS=01) 85 mV tRxFilter Rx Bandwidth Limiting Filter(5) nTransitionCount Transitions count in time window of 12 µs Min. and 20 µs Max. (5) tACTIVITY edge(4) Time from the last BMC in the STATUS register(5) to when ACTIVITY bit goes LOW 100 ns 3 edges 5 9 FUSB302 — Programmable USB Type-C Controller w/PD DC and Transient Characteristics µs Notes: 4. The last BMC edge includes edge when BMC bus is not driven and thus voltage is the result of pull ups/pull downs to if/when it trips the SDAC receiver threshold to cause another BMC edge. 5. Guaranteed by characterization. Not production tested Figure 15. © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 Transmitter Test Load 13 www.fairchildsemi.com www.onsemi.com Symbol TA=-40 to +85°C TJ=-40 to +125°C Parameter Min. RSW_CCx RDSON for SW1_CC1 and SW1_CC2 ISW_CCX Over-Current Protection (OCP) limit at which VCONN switch shuts off over the entire VCONN voltage range. OCPreg=0Fh. tSoftStart VCONN to CC1 & CC2 600 Time taken for the VCONN switch to turn on during which OverCurrent Protection is disabled Unit Typ. Max. 0.4 1.2 Ω 800 1000 mA 1.5 ms I80_CCX SRC 80 µA CC current (Default) HOST_CUR1=0, HOST_CUR0=1 64 80 96 µA I180_CCX SRC 180 µA CC Current (1.5 A) HOST_CUR1=1, HOST_CUR0=0 166 180 194 µA I330_CCX SRC 330 µA CC Current (3 A) HOST_CUR1=1, HOST_CUR0=1 304 330 356 µA VUFPDB SNK Pull-down Voltage in Dead Battery under all Pull-up SRC Loads 2.18 V RDEVICE Device Pull-down Resistance(6) 4.6 5.6 kΩ zOPEN CC Resistance for Disabled State 126 5.1 kΩ WAKElow Wake threshold for CC pin SRC or SNK LOW value. Assumes bandgap and wake circuit turned on ie PWR[0]=1 0.25 V WAKEhigh Wake threshold for CC pin SRC or SNK HIGH value. Assumes bandgap and wake circuit turned on ie PWR[0]=1 1.45 V 20 mV vBC_LVLhys vBC_LVL Hysteresis on the Ra and Rd Comparators CC Pin Thresholds, Assumes PWR=4’h7 BC=2’b00 0.15 0.20 0.25 V BC=2’b01 0.61 0.66 0.70 V BC=2’b10 1.16 1.23 1.31 V vMDACstepCC Measure block MDAC step size for each code in MDAC[5:0] register 42 mV vMDACstepVBUS Measure block MDAC step size for each code in MDAC[5:0] register for VBUS measurement 420 mV vVBUSthr VBUS threshold at which I_VBUSOK interrupt is triggered. Assumes measure block on ie PWR[2]=1. tTOG1 When TOGGLE=1, time at which internal versions of PU_EN1=PU_EN2=0 and PWDN1=PDWN2=1 selected to present externally as a SNK in the DRP toggle 30 tTOG2 When TOGGLE=1, time at which internal versions of PU_EN1=1 or PU_EN2=1 and PWDN1=PDWN2=0 selected to present externally as a SRC in the DRP toggle 20 4.0 V 45 60 ms 30 40 ms TOG_SAVE_PWR2:1=00 0 TOG_SAVE_PWR2:1=01 40 TOG_SAVE_PWR2:1=10 80 TOG_SAVE_PWR2:1=11 160 tDIS Disable time after a full toggle (tTOG1+tTOG2) cycle so as to save power Tshut Temp. for Vconn Switch Off 145 °C Thys Temp. Hysteresis for Vconn Switch Turn On 10 °C FUSB302 — Programmable USB Type-C Controller w/PD Type-C CC Switches ms Note: 6. RDEVICE minimum and maximum specifications are only guaranteed when power is applied. © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 14 www.fairchildsemi.com www.onsemi.com Symbol Parameter VDD (V) Conditions TA=-40 to +85°C TJ=-40 to +125°C Min. Idisable Itog Ipd_stby_ meas Nothing Attached, No Transactions I2C Unit Typ. Max. 0.37 5.00 µA 40 µA Disabled Current 3.0 to 5.5 Unattached (standby) toggle current Nothing attached, TOGGLE=1, 3.0 to 5.5 PWR[3:0]=1h, WAKE_EN=0, TOG_SAVE_PWR2:1=01 25 BMC PD Standby Current Device Attached, BMC PD Active But Not Sending or 3.0 to 5.5 Receiving Anything, PWR[3:0]=7h, 40 µA USB PD Specific Parameters Symbol TA = -40 to +85°C TJ=-40 to +125°C Parameter Min. tHardReset If a Soft Reset message fails, a Hard Reset is sent after tHardReset of CRCReceiveTimer expiring Typ. Unit Max. 5 ms 5 ms 1.1 ms Once the CRCReceiveTimer expires, a retry packet has to be sent out within tRetry time. This time is hard to separate externally from tReceive since they both happen sequentially with no visible difference in the CC output 75 µs tSoftReset If a GoodCRC packet is not received within tReceive for NRETRIES then a Soft Reset packet is sent within tSoftReset time. 5 ms tTransmit From receiving a packet, we have to send a GoodCRC in response within tTransmit time. It is measured from the last bit of the EOP of the received packet to the first bit sent of the preamble of the GoodCRC packet 195 µs If the FUSB302 cannot send a Hard Reset within tHardReset tHardResetComplete time because of a busy line, then a Complete I_HARDFAIL interrupt is triggered tReceive tRetry This is the value for which the CRCReceiveTimer expires. The CRCReceiveTimer is started upon the last bit of the EOP of the transmitted packet © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 15 0.9 FUSB302 — Programmable USB Type-C Controller w/PD Current Consumption www.fairchildsemi.com www.onsemi.com Symbol Parameter VDD (V) Conditions TA=-40 to +85°C TJ=-40 to +125°C Min. Typ. Unit Max. Host Interface Pins(INT_N) VOLINTN Output Low Voltage 3.0 to 5.5 IOL=4 mA TINT_Mask Time from global interrupt mask bit cleared to when INT_N goes LOW 3.0 to 5.5 0.4 50 V µs I2C Interface Pins – Standard, Fast, or Fast Mode Plus Speed Mode (SDA, SCL)(7) VILI2C Low-Level Input Voltage 3.0 to 5.5 VIHI2C High-Level Input Voltage 3.0 to 5.5 1.32 V VHYS Hysteresis of Schmitt Trigger Inputs 3.0 to 5.5 94 mV Input Current of SDA and SCL Pins 3.0 to 5.5 ICCTI2C VDD Current when SDA or SCL is HIGH 3.0 to 5.5 Input Voltage 1.8 V VOLSDA Low-Level Output Voltage (Open-Drain) IOLSDA II2C CI 0.51 Input Voltage 0.26 V to 2.0 V V -10 10 µA -10 10 µA 3.0 to 5.5 IOL=2 mA 0 0.35 V Low-Level Output Current (Open-Drain) 3.0 to 5.5 VOLSDA=0.4 V 20 Capacitance for Each I/O Pin 3.0 to 5.5 mA 5 FUSB302 — Programmable USB Type-C Controller w/PD IO Specifications pF Note: 7. I2C pull up voltage is required to be between 1.71 V and VDD. © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 16 www.fairchildsemi.com www.onsemi.com Symbol fSCL tHD;STA Fast Mode Plus Parameter I2C_SCL Clock Frequency Min. Max. Unit 0 1000 kHz Hold Time (Repeated) START Condition 0.26 µs tLOW Low Period of I2C_SCL Clock 0.5 µs tHIGH High Period of I2C_SCL Clock 0.26 µs tSU;STA Set-up Time for Repeated START Condition 0.26 µs tHD;DAT Data Hold Time 0 µs tSU;DAT Data Set-up Time 50 tr tf tSU;STO Rise Time of I2C_SDA and I2C_SCL Signals(8) Fall Time of I2C_SDA and I2C_SCL Signals(8) 6 Set-up Time for STOP Condition ns 120 ns 0.26 Conditions(8) tBUF Bus-Free Time between STOP and START tSP Pulse Width of Spikes that Must Be Suppressed by the Input Filter Cb Line(8) Capacitive Load for each Bus ns 120 µs 0.5 0 µs 50 ns 550 pF tVD-DAT Data Valid Time for Data from SCL LOW to SDA HIGH or LOW Output(8) 0 0.45 µs tVD-ACK Data Valid Time for acknowledge from SCL LOW to SDA HIGH or LOW Output(8) 0 0.45 µs VnL Noise Margin at the LOW Level(8) 0.2 V VnH Level(8) 0.4 V Noise Margin at the HIGH FUSB302 — Programmable USB Type-C Controller w/PD I2C Specifications Fast Mode Plus I2C Specification Note: 8. Guaranteed by characterization. Not production tested. © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 17 www.fairchildsemi.com www.onsemi.com Table 4. FUSB302 — Programmable USB Type-C Controller w/PD Figure 16. Definition of Timing for Full-Speed Mode Devices on the I2C Bus I2CTM Slave Address Name Size (Bits) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Slave Address 8 0 1 0 0 0 1 0 R/W © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 18 www.fairchildsemi.com www.onsemi.com Register Definitions(9)(10) Address Register Name Type Rst Val Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MEAS_CC2 MEAS_CC1 PDWN2 PDWN1 AUTO_CRC TXCC2 TXCC1 MDAC0 0x01 Device ID R 8x 0x02 Switches0 R/W 03 PU_EN2 PU_EN1 VCONN _CC2 VCONN _CC1 0x03 Switches1 R/W 20 POWERROLE SPECREV1 SPECREV0 DATAROLE 0x04 Measure R/W 31 MEAS_VBUS MDAC5 MDAC4 MDAC3 MDAC2 MDAC1 0x05 Slice R/W 60 SDAC_HYS2 SDAC5 SDAC4 SDAC3 SDAC2 SDAC1 SDAC0 0x06 Control0 R/W/C 24 TX_FLUSH INT_MASK HOST_CUR1 HOST_CUR0 AUTO_PRE TX_START 0x07 Control1 R/W/C 00 ENSOP2DB ENSOP1DB RX_FLUSH ENSOP2 ENSOP1 TOG_SAVE_P WR1 TOG_RD_ONLY Version ID[3:0] SDAC_HYS1 TOG_SAVE_PW R2 Revision ID[3:0] BIST_MODE2 0x08 Control2 R/W 02 0x09 Control3 R/W 06 0x0A Mask1 R/W 00 0x0B Power R/W 01 0x0C Reset W/C 00 0x0D OCPreg R/W 0F 0x0E Maska R/W 00 0x0F Maskb R/W 00 M_GCRCSENT 0x10 Undocumented Control4 R/W 00 TOG_USRC_EX IT 0x3C Status0a R 00 SOFTFAIL RETRYFAIL POWER3 POWER2 SOFTRST HARDRST 0x3D Status1a R 00 TOGSS3 TOGSS2 TOGSS1 RXSOP2DB RXSOP1DB RXSOP 0x3E Interrupta R/C 00 I_SOFTFAIL I_RETRYFAIL I_HARDSENT I_TXSENT I_SOFTRST 0x3F Interruptb R/C 00 0x40 Status0 R 00 VBUSOK ACTIVITY COMP CRC_CHK ALERT WAKE BC_LVL1 0x41 Status1 R 28 RXSOP2 RXSOP1 RX_EMPTY RX_FULL TX_EMPTY TX_FULL OVRTEMP OCP 0x42 Interrupt R/C 00 I_VBUSOK I_ACTIVITY I_COMP_CHNG I_CRC_CHK I_ALERT I_WAKE I_COLLISION I_BC_LVL 0x43 FIFOs R/W (11) Type C Bits USB PD Bits SEND_HARD_R ESET M_VBUSOK M_OCP_TEMP I_OCP_TEMP M_ACTIVITY M_TOGDONE I_TOGDONE M_COMP_CHNG M_SOFTFAIL WAKE_EN MODE[1:0] TOGGLE AUTO_HARDR ESET AUTO_SOFTRES ET N_RETRIES[1:0] AUTO_RETRY M_CRC_CHK M_ALERT M_WAKE M_COLLISION PWR3 PWR2 PWR1 PWR0 PD_RESET SW_RES M_RETRYFAIL M_BC_LVL OCP_RANGE OCP_CUR2 OCP_CUR1 OCP_CUR0 M_HARDSENT M_TXSENT M_SOFTRST M_HARDRST I_HARDRST I_GCRCSENT 00 BC_LVL0 Write to TX FIFO or read from RX FIFO repeatedly without address auto increment General Bits Notes: 9. Do not use registers that are blank. 10. Values read from undefined register bits are not defined and invalid. Do not write to undefined registers. 11. FIFO register is serially read/written without auto address increment. © 2015 Semiconductor Components Industries, LLC. - FUSB302 • Rev. 2 19 www.onsemi.com Device ID Address: 01h Reset Value: 0x1000_00XX Type: Read Bit # Name 7:4 R/W/C Version ID 3:0 Description 4 Device version ID by Trim or etc. A_[Revision ID]: 1000 (e.g. A_revA) B_[Revision ID]: 1001 C_[Revision ID]: 1010 etc R 4 Revision History of each version [Version ID]_revA: 0000 (e.g. A_revA) [Version ID]_revB: 0001 [Version ID]_revC: 0010 etc R Revision ID Table 6. Size (Bits) Switches0 Address: 02h Reset Value: 0x0000_0011 Type: Read/Write Bit # Name R/W/C Size (Bits) 7 PU_EN2 R/W 1 1: Apply host pull up current to CC2 pin. 6 PU_EN1 R/W 1 1: Apply host pull up current to CC1 pin. 5 VCONN_CC2 R/W 1 1: Turn on the VCONN current to CC2 pin. 4 VCONN_CC1 R/W 1 1: Turn on the VCONN current to CC1 pin. 3 MEAS_CC2 R/W 1 1: Use the measure block to monitor or measure the voltage on CC2. 2 MEAS_CC1 R/W 1 1: Use the measure block to monitor or measure the voltage on CC1. 1 PDWN2 R/W 1 1: Device pull down on CC2. 0: no pull down. 0 PDWN1 R/W 1 1: Device pull down on CC1. 0: no pull down. Table 7. Description FUSB302 — Programmable USB Type-C Controller w/PD Table 5. Switches1 Address: 03h Reset Value: 0x0010_0000 Type: Read/Write Bit # 7 6:5 Name POWERROLE SPECREV1: SPECREV0 R/W/C Size (Bits) R/W R/W Description 1 Bit used for constructing the GoodCRC acknowledge packet. This bit corresponds to the Port Power Role bit in the message header if an SOP packet is received 1: Source if SOP 0: Sink if SOP 2 Bit used for constructing the GoodCRC acknowledge packet. These bits correspond to the Specification Revision bits in the message header 00: Revision 1.0 01: Revision 2.0 10, 11: Do Not Use 4 DATAROLE R/W 1 Bit used for constructing the GoodCRC acknowledge packet. This bit corresponds to the Port Data Role bit in the message header. For SOP: 1: SRC 0: SNK 3 Reserved N/A 1 Do Not Use 2 AUTO_CRC R/W 1 1: Starts the transmitter automatically when a message with a good CRC is received and automatically sends a GoodCRC acknowledge packet back to the relevant SOP* 0: Feature disabled. 1 TXCC2 R/W 1 1: Enable BMC transmit driver on CC2 pin. 0 TXCC1 R/W 1 1: Enable BMC transmit driver on CC1 pin. © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 20 www.fairchildsemi.com www.onsemi.com Measure Address: 04h Reset Value: 0x0011_0001 Type: Read/Write Bit # Name 7 Reserved 6 R/W/C Size (Bits) MEAS_VBUS N/A R/W Description 1 Do Not Use 1 0: MDAC/comparator measurement is controlled by MEAS_CC* bits. 1: Measure VBUS with the MDAC/comparator. This requires MEAS_CC* bits to be 0. Measure Block DAC data input. LSB is equivalent to 42 mV of voltage which is compared to the measured CC voltage. The measured CC is selected by MEAS_CC2, or MEAS_CC1 bits. 5:0 MDAC[5:0] Table 9. R/W 6 MDAC[5:0] MEAS_VBUS=0 MEAS_VBUS=1 Unit 00_0000 0.042 0.420 V 00_0001 0.084 0.840 V 11_0000 2.058 20.58 V 11_0011 2.184 21.84 V 11_1110 2.646 26.46 V 11_1111 >2.688 26.88 V Slice Address: 05h Reset Value: 0x0110_0000 Type: Read/Write Bit # Name R/W/ C Size (Bits) Description 7:6 SDAC_HYS[1:0] R/W 2 Adds hysteresis where there are now two thresholds, the lower threshold which is always the value programmed by SDAC[5:0] and the higher threshold that is: 11: 255 mV hysteresis: higher threshold = (SDAC value + 20hex) 10 = 170 mV hysteresis: higher threshold = (SDAC value + Ahex) 01 = 85 mV hysteresis: higher threshold = (SDAC value + 5) 00 = No hysteresis: higher threshold = SDAC value 5:0 SDAC[5:0] R/W 6 BMC Slicer DAC data input. Allows for a programmable threshold so as to meet the BMC receive mask under all noise conditions. © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 FUSB302 — Programmable USB Type-C Controller w/PD Table 8. 21 www.fairchildsemi.com www.onsemi.com Address: 06h Reset Value: 0x0010_0100 Type: (see column below) Bit # Name R/W/C Size (Bits) Description 7 Reserved N/A 1 Do Not Use 6 TX_FLUSH W/C 1 1: Self clearing bit to flush the content of the transmit FIFO. 5 INT_MASK R/W 1 1: Mask all interrupts. 0: Interrupts to host are enabled. 4 Reserved N/A 1 Do Not Use 2 1: Controls the host pull up current enabled by PU_EN[2:1]: 00: No current 01: 80 µA – Default USB power. 10: 180 µA – Medium Current Mode: 1.5 A 11: 330 µA – High Current Mode: 3 A 3:2 HOST_CUR[1:0] R/W 1 AUTO_PRE R/W 1 1: Starts the transmitter automatically when a message with a good CRC is received. This allows the software to take as much as 300 µS to respond after the I_CRC_CHK interrupt is received. Before starting the transmitter, an internal timer waits for approximately 170 µS before executing the transmit start and preamble. 0: Feature disabled. 0 TX_START W/C 1 1: Start transmitter using the data in the transmit FIFO. Preamble is started first. During the preamble period the transmit data can start to be written to the transmit FIFO. Self clearing. Table 11. Control1 FUSB302 — Programmable USB Type-C Controller w/PD Table 10. Control0 Address: 07h Reset Value: 0x0000_0000 Type: (see column below) Bit # Name 7 Reserved R/W/C Size (Bits) N/A 1 Do Not Use 6 ENSOP2DB R/W 1 1: Enable SOP”_DEBUG (SOP double prime debug) packets 0: Ignore SOP”_DEBUG (SOP double prime debug) packets 5 ENSOP1DB R/W 1 1: Enable SOP‘_DEBUG (SOP prime debug) packets 0: Ignore SOP‘_DEBUG (SOP prime debug) packets 4 BIST_MODE2 R/W 1 1: Sent BIST Mode 01s pattern for testing 3 Reserved N/A 1 Do Not Use 2 RX_FLUSH W/C 1 1: Self clearing bit to flush the content of the receive FIFO. 1 ENSOP2 R/W 1 1: Enable SOP”(SOP double prime) packets 0: Ignore SOP”(SOP double prime) packets 0 ENSOP1 R/W 1 1: Enable SOP‘(SOP prime) packets 0: Ignore SOP‘(SOP prime) packets © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 Description 22 www.fairchildsemi.com www.onsemi.com Address: 08h Reset Value: 0x0000_0010 Type: (see column below) Bit # 7:6 Name R/W/C Size (Bits) TOG_SAVE_PWR2: TOG_SAVE_PWR1 N/A Description 2 00: Don’t go into the DISABLE state after one cycle of toggle 01: Wait between toggle cycles for tDIS time of 40 ms 10: Wait between toggle cycles for tDIS time of 80 ms 11: Wait between toggle cycles for tDIS time of 160 ms 5 TOG_RD_ONLY R/W 1 1: When TOGGLE=1 only Rd values will cause the TOGGLE state machine to stop toggling and trigger the I_TOGGLE interrupt. 0: When TOGGLE=1, Rd and Ra values will cause the TOGGLE state machine to stop toggling. 4 Reserved N/A 1 Do Not Use 3 WAKE_EN R/W 1 1: Enable Wake Detection functionality if the power state is correct 0: Disable Wake Detection functionality 2:1 MODE R/W 2 11: Enable SRC polling functionality if TOGGLE=1 10: Enable SNK polling functionality if TOGGLE=1 01: Enable DRP polling functionality if TOGGLE=1 00: Do Not Use 0 TOGGLE R/W 1 1: Enable DRP, SNK or SRC Toggle autonomous functionality 0: Disable DRP, SNK and SRC Toggle functionality Table 13. Control3 FUSB302 — Programmable USB Type-C Controller w/PD Table 12. Control2 Address: 09h Reset Value: 0x0000_0110 Type: (see column below) Bit # Name R/W/C Size (Bits) 7 Reserved N/A 1 Do Not Use 6 SEND_HARD_RESET W/C 1 1: Send a hard reset packet (highest priority) 0: Don’t send a soft reset packet 5 Reserved N/A 1 Do Not Use 4 AUTO_HARDRESET R/W 1 1: Enable automatic hard reset packet if soft reset fail 0: Disable automatic hard reset packet if soft reset fail 3 AUTO_SOFTRESET R/W 1 1: Enable automatic soft reset packet if retries fail 0: Disable automatic soft reset packet if retries fail 2 11: Three retries of packet (four total packets sent) 10: Two retries of packet (three total packets sent) 01: One retry of packet (two total packets sent) 00: No retries (similar to disabling auto retry) 1 1: Enable automatic packet retries if GoodCRC is not received 0: Disable automatic packet retries if GoodCRC not received 2:1 0 N_RETRIES[1:0] AUTO_RETRY R/W R/W © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 Description 23 www.fairchildsemi.com www.onsemi.com Address: 0Ah Reset Value: 0x0000_0000 Type: Read/Write Bit # Name R/W/C Size (Bits) Description 7 M_VBUSOK R/W 1 1: Mask I_VBUSOK interrupt bit. 0: Do not mask. 6 M_ACTIVITY R/W 1 1: Mask interrupt for a transition in CC bus activity. 0: Do not mask. 5 M_COMP_CHNG R/W 1 1: Mask I_COMP_CHNG interrupt for change is the value of COMP, the measure comparator. 0: Do not mask. 4 M_CRC_CHK R/W 1 1: Mask interrupt from CRC_CHK bit. 0: Do not mask. 3 M_ALERT R/W 1 1: Mask the I_ALERT interrupt bit. 0: Do not mask. 2 M_WAKE R/W 1 1: Mask the I_WAKE interrupt bit. 0: Do not mask. 1 M_COLLISION R/W 1 1: Mask the I_COLLISION interrupt bit. 0: Do not mask. 0 M_BC_LVL R/W 1 1: Mask a change in host requested current level. 0: Do not mask. Table 15. Power Address: 0Bh Reset Value: 0x0000_0001 Type: Read/Write Bit # Name 7:4 Reserved 3:0 PWR[3:0] R/W/C Size (Bits) N/A R/W FUSB302 — Programmable USB Type-C Controller w/PD Table 14. Mask Description 4 Do Not Use 4 Power enables: PWR[0]: Bandgap and wake circuit. PWR[1]: Receiver powered and current references for Measure block PWR[2]: Measure block powered. PWR[3]: Enable internal oscillator. Table 16. Reset Address: 0Ch Reset Value: 0x0000_0000 Type: Write/Clear Bit # Name R/W/C Size (Bits) 7:2 Reserved N/A 6 Do Not Use 1 PD_RESET W/C 1 1: Reset just the PD logic for both the PD transmitter and receiver. 0 SW_RES W/C 1 1: Reset the FUSB302 including the I2C registers to their default values. © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 Description 24 www.fairchildsemi.com www.onsemi.com Address: 0Dh Reset Value: 0x0000_1111 Type: Read/Write Bit # Name R/W/C Size (Bits) 7:4 Reserved N/A 4 Do Not Use 3 OCP_RANGE R/W 1 1: OCP range between 100 mA-800 mA (max_range=800 mA) 0: OCP range between 10 mA-80 mA (max_range=80 mA) R/W 3 111: max_range (see bit definition above for OCP_RANGE) 110: 7*max_range/8 101: 6*max_range/8 100: 5*max_range/8 011: 4*max_range/8 010: 3*max_range/8 001: 2*max_range/8 000: max_range/8 2:0 OCP_CUR2, OCP_CUR1, OCP_CUR0 Description Table 18. Maska Address: 0Eh Reset Value: 0x0000_0000 Type: Read/Write Bit # Name R/W/ C Size (Bits) 7 M_OCP_TEMP R/W 1 1: Mask the I_OCP_TEMP interrupt 6 M_TOGDONE R/W 1 1: Mask the I_TOGDONE interrupt 5 M_SOFTFAIL R/W 1 1: Mask the I_SOFTFAIL interrupt 4 M_RETRYFAIL R/W 1 1: Mask the I_RETRYFAIL interrupt 3 M_HARDSENT R/W 1 1: Mask the I_HARDSENT interrupt 2 M_TXSENT R/W 1 1: Mask the I_TXSENT interrupt 1 M_SOFTRST R/W 1 1: Mask the I_SOFTRST interrupt 0 M_HARDRST R/W 1 1: Mask the I_HARDRST interrupt R/W/C Size (Bits) Description FUSB302 — Programmable USB Type-C Controller w/PD Table 17. OCPreg Table 19. Maskb Address: 0Fh Reset Value: 0x0000_0000 Type: Read/Write Bit # Name Description 7:1 Reserved N/A 6 Do Not Use 0 M_GCRCSENT R/W 1 1: Mask the I_GCRCSENT interrupt Table 20. Control4 Address: 10h Reset Value: 0x0000_0000 Type: Read/Write Bit # Name R/W/C Size (Bits) 7:1 Reserved N/A 6 Do Not Use 0 TOG_USRC_EXIT R/W 1 1: In TOGGLE mode, stop toggling and exit to STOP_AUD if both CC1 and CC2 are detected in the Ra voltage range when in Unattached.DFP state. © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 Description 25 www.fairchildsemi.com www.onsemi.com Address: 3Ch Reset Value: 0x0000_0000 Type: Read Bit # Name R/W/C Size (Bits) Description 7:6 Reserved N/A 2 Do Not Use 5 SOFTFAIL R 1 1: All soft reset packets with retries have failed to get a GoodCRC acknowledge. This status is cleared when a START_TX, TXON or SEND_HARD_RESET is executed. 4 RETRYFAIL R 1 1: All packet retries have failed to get a GoodCRC acknowledge. This status is cleared when a START_TX, TXON or SEND_HARD_RESET is executed. 3:2 POWER3:POWER2 R 2 Internal power state when logic internals needs to control the power state. POWER3 corresponds to PWR3 bit and POWER2 corresponds to PWR2 bit. The power state is the higher of both PWR[3:0] and {POWER3, POWER2, PWR[1:0]} so that if one is 03 and the other is F then the internal power state is F. 1 SOFTRST R 1 1: One of the packets received was a soft reset packet 0 HARDRST R 1 1: Hard Reset PD ordered set has been received Table 22. Status1a Address: 3Dh Reset Value: 0x0000_0000 Type: Read Bit # Name R/W/C Size (Bits) Description 7:6 Reserved N/A 2 Do Not Use 5:3 TOGSS3: TOGSS2: TOGSS1 R 3 000: Toggle logic running (processor has previously written TOGGLE=1) 001: Toggle functionality has settled to SRCon CC1 (STOP_SRC1 state) 010: Toggle functionality has settled to SRCon CC2 (STOP_SRC2 state) 101: Toggle functionality has settled to SNKon CC1 (STOP_SNK1 state) 110: Toggle functionality has settled to SNKon CC2 (STOP_SNK2 state) 111: Toggle functionality has detected AudioAccessory with vRa on both CC1 and CC2 (settles to STOP_SRC1 state) Otherwise: Not defined (do not interpret) 2 RXSOP2DB R 1 1: Indicates the last packet placed in the RxFIFO is type SOP”_DEBUG (SOP double prime debug). 1 RXSOP1DB R 1 1: Indicates the last packet placed in the RxFIFO is type SOP’_DEBUG (SOP prime debug). 0 RXSOP R 1 1: Indicates the last packet placed in the RxFIFO is type SOP. © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 26 FUSB302 — Programmable USB Type-C Controller w/PD Table 21. Status0a www.fairchildsemi.com www.onsemi.com Address: 3Eh Reset Value: 0x0000_0000 Type: Read/Clear Bit # Name R/W/C Size (Bits) 7 I_OCP_TEMP R/C 1 6 I_TOGDONE R/C 1 5 I_SOFTFAIL R/C 1 4 I_RETRYFAIL R/C 1 3 I_HARDSENT R/C 1 2 I_TXSENT R/C 1 1 0 I_SOFTRST I_HARDRST R/C R/C 1 1 Description 1: Interrupt from either a OCP event on one of the VCONN switches or an over-temperature event 1: Interrupt indicating the TOGGLE functionality was terminated because a device was detected. 1: Interrupt from automatic soft reset packets with retries have failed 1: Interrupt from automatic packet retries have failed 1: Interrupt from successfully sending a hard reset ordered set 1: Interrupt to alert that we sent a packet that was acknowledged with a GoodCRC response packet 1: Received a soft reset packet 1: Received a hard reset ordered set Table 24. Interruptb Address: 3Fh Reset Value: 0x0000_0000 Type: Read/Clear Bit # Name R/W/C Size (Bits) 7 Reserved N/A 6 0 I_GCRCSENT R/C 1 © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 Description Do Not Use 1: Sent a GoodCRC acknowledge packet in response to an incoming packet that has the correct CRC value. 27 FUSB302 — Programmable USB Type-C Controller w/PD Table 23. Interrupta www.fairchildsemi.com www.onsemi.com Address: 40h Reset Value: 0x0000_0000 Type: Read Bit # Name R/W/C Size (Bits) 7 VBUSOK R 1 6 ACTIVITY R 1 5 COMP R 1 4 CRC_CHK R 1 3 ALERT R 1 2 WAKE R 1 1:0 BC_LVL[1:0] R 2 Description 1: Interrupt occurs when VBUS transitions through vVBUSthr. This bit typically is used to recognize port partner during startup. 1: Transitions are detected on the active CC* line. This bit goes high after a minimum of 3 CC transitions, and remains high for tACTIVITY after last transition on CC. 0: inactive. 1: Measured CC* input is higher than reference level driven from the MDAC. 0: Measured CC* input is lower than reference level driven from the MDAC. 1: Indicates the last received packet had the correct CRC. This bit remains set until the SOP of the next packet. 0: Packet received for an enabled SOP* and CRC for the enabled packet received was incorrect 1: Alert software an error condition has occurred. An alert is caused by: TX_FULL: the transmit FIFO is full. RX_FULL: the receive FIFO is full. See Status1 bits 1: Voltage on CC indicated a device attempting to attach. 0: WAKE either not enabled (WAKE_EN=0) or no device attached. Current voltage status of the measured CC pin interpreted as host current levels as follows: 00: < 200 mV 01: >200 mV, 660 mV, 1.23 V Note the software must measure these at an appropriate time, while there is no signaling activity on the selected CC line. BC_LVL is only defined when Measure block is on which is when register bits PWR[2]=1 and either MEAS_CC1=1 or MEAS_CC2=1 FUSB302 — Programmable USB Type-C Controller w/PD Table 25. Status0 Table 26. Status1 Address: 41h Reset Value: 0x0010_1000 Type: Read Bit # Name R/W/C Size (Bits) 7 RXSOP2 R 1 1: Indicates the last packet placed in the RxFIFO is type SOP’’ (SOP double prime). 6 RXSOP1 R 1 1: Indicates the last packet placed in the RxFIFO is type SOP’ (SOP prime). 5 RX_EMPTY R 1 1: The receive FIFO is empty. 4 RX_FULL R 1 1: The receive FIFO is full. 3 TX_EMPTY R 1 1: The transmit FIFO is empty. 2 TX_FULL R 1 1: The transmit FIFO is full. 1 OVRTEMP R 1 1: Temperature of the device is too high. 0 OCP R 1 1: Indicates an over-current or short condition has occurred on the VCONN switch. © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 Description 28 www.fairchildsemi.com www.onsemi.com Address: 42h Reset Value: 0x0000_0000 Type: Read/Clear Bit # Name R/W/C Size (Bits) Description 7 I_VBUSOK R/C 1 1: Interrupt occurs when VBUS transitions through 4.5 V. This bit typically is used to recognize port partner during startup. 6 I_ACTIVITY R/C 1 1: A change in the value of ACTIVITY of the CC bus has occurred. 5 I_COMP_CHNG R/C 1 1: A change in the value of COMP has occurred. Indicates selected CC line has tripped a threshold programmed into the MDAC. 4 I_CRC_CHK R/C 1 1: The value of CRC_CHK newly valid. I.e. The validity of the incoming packet has been checked. 3 I_ALERT R/C 1 1: Alert software an error condition has occurred. An alert is caused by: TX_FULL: the transmit FIFO is full. RX_FULL: the receive FIFO is full. See Status1 bits. 2 I_WAKE R/C 1 1: Voltage on CC indicated a device attempting to attach. Software must then power up the clock and receiver blocks. 1 I_COLLISION R/C 1 1: When a transmit was attempted, activity was detected on the active CC line. Transmit is not done. The packet is received normally. 0 I_BC_LVL R/C 1 1: A change in host requested current level has occurred. Name R/W/C Size (Bits) TX/RX Token Read or Write FUSB302 — Programmable USB Type-C Controller w/PD Table 27. Interrupt Table 28. FIFOs Address: 43h Reset Value: 0x0000_0000 Type: (see column below) Bit # 7:0 © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 8 Description Writing to this register writes a byte into the transmit FIFO. Reading from this register reads from the receive FIFO. Each byte is a coded token. Or a token followed by a fixed number of packed data byte (see token coding in Table 29). 29 www.fairchildsemi.com www.onsemi.com Transmit Data Tokens Port software interacts with the port chip in two primary ways: Transmit data tokens provide in-sequence transmit control and data for the transmit logic. Note that the token codes, and their equivalent USB PD K-Code are not the same. Tokens are read one at a time when they reach the end of the TX FIFO. I.e., the specified token action is performed before the next token is read from the TX FIFO.   I2C Registers  All reserved bits written in the TxFIFO should be 0 and all reserved bit read from the RxFIFO should be ignored. 8 bit data tokens sent to or received from the FIFO register. The tokens are defined as follows: Table 29. Tokens Used in FIFO Code Name Size (Bytes) Description 101x-xxx1 (0xA1) TXON 1 Alternative method for starting the transmitter with the TX-START bit. This is not a token written to the TxFIFO but a command much like TX_START but it is more convenient to write it while writing to the TxFIFO in one contiguous write operation. It is preferred that the TxFIFO is first written with data and then TXON or TX_START is executed. It is expected that A1h will be written for TXON not any other bits where x is non-zero such as B1h, BFh, etc 0x12 SOP1 1 When reaching the end of the FIFO causes a Sync-1 symbol to be transmitted. 0x13 SOP2 1 When reaching the end of the FIFO causes a Sync-2 symbol to be transmitted. 0x1B SOP3 1 When reaching the end of the FIFO causes a Sync-3 symbol to be transmitted. 0x15 RESET1 1 When reaching the end of the FIFO causes a RST-1 symbol to be transmitted. 0x16 RESET2 1 When reaching the end of the FIFO causes a RST-2 symbol to be transmitted. This data token must be immediately followed by a sequence of N packed data bytes. This token is defined by the 3 MSB’s being set to 3’b100. The 5 LSB’s are the number of packed bytes being sent. Note: N cannot be less than 2 since the minimum control packet has a header that is 2 bytes and N cannot be greater than 30 since the maximum data packet has 30 bytes (2 byte header + 7 data objects each having 4 bytes) Packed data bytes have two 4 bit data fields. The 4 LSB’s are sent first, after 4b5b conversion etc in the chip. 0x80 PACKSYM 1+N 0xFF JAM_CRC 1 Causes the CRC, calculated by the hardware, to be inserted into the transmit stream when this token reaches the end of the TX FIFO. 0x14 EOP 1 Causes an EOP symbol to be sent when this token reaches the end of the TX FIFO. 0xFE TXOFF 1 Turn off the transmit driver. Typically the next symbol after EOP. © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 FUSB302 — Programmable USB Type-C Controller w/PD Software Model 30 www.fairchildsemi.com www.onsemi.com Receive data tokens provide in-sequence receive control and data for the receive logic. The RxFIFO can absorb as many packets as the number of bytes in the RxFIFO (80 bytes). The tokens are defined as follows: Table 30. Tokens Used in RxFIFO Code (in binary) Name Size (Bytes) Description 111b_bbbb SOP 1 First byte of a received packet to indicate that the packet is an SOP packet (“b” is undefined and can be any bit) 110b_bbbb SOP1 1 First byte of a received packet to indicate that the packet is an SOP’ packet and occurs only if ENSOP1=1 (“b” is undefined and can be any bit) 101b_bbbb SOP2 1 First byte of a received packet to indicate that the packet is an SOP’’ packet and occurs only if ENSOP2=1 (“b” is undefined and can be any bit) 100b_bbbb SOP1DB 1 First byte of a received packet to indicate that the packet is an SOP’_DEBUG packet and occurs only if ENSOP1DB=1 (“b” is undefined and can be any bit) 011b_bbbb SOP2DB 1 First byte of a received packet to indicate that the packet is an SOP’’_DEBUG packet and occurs only if ENSOP2DB=1 (“b” is undefined and can be any bit) 010b_bbbb / 001b_bbbb / 000b_bbbb Do Not Use 1 These can be used in future versions of this device and should not be relied on to be any special value. (“b” is undefined and can be any bit) © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 31 FUSB302 — Programmable USB Type-C Controller w/PD Receive Data Tokens www.fairchildsemi.com www.onsemi.com Figure 17. FUSB300/302 Reference Schematic Diagram Table 31. Recommended Component Values for Reference Schematic Recommended Value Symbol Parameter Unit Min. Typ. Max. CRECV CCX Receiver Capacitance 200 600 pF CBULK VCONN Source Bulk Capacitance 10 220 µF CVCONN VCONN Decoupling Capacitance 0.1 µF CVDD1 VDD Decoupling Capacitance 0.1 µF CVDD2 VDD Decoupling Capacitance 1.0 µF I2C Pull-up Resistors 4.7 kΩ 4.7 kΩ RPU RPU_INT VPU INT_N Pull-up Resistor 1.0 I2C Pull-up Voltage 1.71 VDD FUSB302 — Programmable USB Type-C Controller w/PD Reference Schematic V The table below is in reference to the WLCSP dimensions on the following page. Product-Specific Dimensions Product D E X Y FUSB302UCX 1.215 mm 1.260 mm 0.230 mm 0.2075 mm © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 32 www.fairchildsemi.com www.onsemi.com 0.03 C E 2X E A B 0.40 A1 BALL A1 INDEX AREA (Ø0.215) Cu Pad (Bottom) 0.40 D 0.03 C (Ø0.315) Solder Mask 2X RECOMMENDED LAND PATTERN (NSMD PAD TYPE) TOP VIEW 0.06 C 0.378±0.018 0.581±0.038 0.05 C 0.203±0.020 C SEATING PLANE D 0.40 0.40 SIDE VIEWS NOTES A. NO JEDEC REGISTRATION APPLIES. B. DIMENSIONS ARE IN MILLIMETERS. 0.005 C A B C. DIMENSIONS AND TOLERANCE PER Ø0.260±0.02 ASME Y14.5M, 2009. 9X D. DATUM C IS DEFINED BY THE C SPHERICAL CROWNS OF THE BALLS. B (Y) ±0.018 E. FOR DIMENSIONS D,E,X, AND Y SEE A PRODUCT DATASHEET. F. DRAWING FILNAME: MKT-UC009Ak rev2 1 2 3 E (X) ±0.018 FUSB302 — Programmable USB Type-C Controller w/PD Physical Dimensions BOTTOM VIEW Figure 18. © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 9-Lead, Wafer-Level Chip-Scale Package (WLCSP) 33 www.fairchildsemi.com www.onsemi.com 0.05 C 2.50 2X A B 2.43 1.45 PIN #1 IDENT 2.50 2.43 1.45 0.05 C TOP VIEW 2X (0.58) 0.75±0.05 0.50 TYP 0.10 C 0.15±0.05 0.08 C 0.30 TYP RECOMMENDED LAND PATTERN C 0.025±0.025 SEATING PLANE FRONT VIEW NOTES: A. NO JEDEC REGISTRATION. 2.50±0.05 1.45±0.05 4 B. DIMENSIONS ARE IN MILLIMETERS. 7 C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 2009. 8 3 D. LAND PATTERN RECOMMENDATION IS EXISTING INDUSTRY LAND PATTERN. 0.50 1.45±0.05 E. DRAWING FILENAME: MKT-MLP14Drev3 10 1 FUSB302 — Programmable USB Type-C Controller w/PD Physical Dimensions 0.30(14X) PIN #1 IDENT 14 11 0.24±0.06(14X) 0.50 BOTTOM VIEW Figure 19. © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 0.10 0.05 C A B C 14-Lead MLP, 2.5 mm x 2.5 mm, 0.5 mm Pin Pitch 34 www.fairchildsemi.com www.onsemi.com FUSB302 — Programmable USB Type-C Controller w/PD ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com © 2015 Semiconductor Components Industries, LLC. FUSB302 • Rev. 2 N. American Technical Support: 800-282-9855 Toll Free USA/Canada. Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5817-1050 35 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative www.fairchildsemi.com www.onsemi.com Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: onsemi: FUSB302UCX FUSB302MPX