DATA SHEET
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Dual Supply, 2-Bit Voltage
Translator / Isolator for I2C
Applications
UQFN8, 1.4x1.2, 0.4P
CASE 523AS
FXMAR2102
UQFN8 1.6X1.6, 0.5P
CASE 523AY
Description
The FXMAR2102 is a high−performance configurable
dual−voltage−supply translator for bi−directional voltage translation
over a wide range of input and output voltages levels. The
FXMAR2102 also works in a push− pull environment.
It is intended for use as a voltage translator between I2C−Bus
compliant masters and slaves. Internal 10 kW pull−up resistors are
provided.
The device is designed so the A port tracks the VCCA level and the B
port tracks the VCCB level. This allows for bi−directional A/B−port
voltage translation between any two levels from 1.65 V to 5.5 V. VCCA
can equal VCCB from 1.65 V to 5.5 V. Either VCC can be powered−up
first. Internal power−down control circuits place the device in 3−state
if either VCC is removed.
The two ports of the device have automatic direction−sense
capability. Either port may sense an input signal and transfer it as an
output signal to the other port.
MARKING DIAGRAM
BU&K
&2&Z
1
BU
&K
&2
&Z
= Device Code
= 2−Digits Lot Run Traceability Code
= 2−Digit Date Code
= Assembly Plant Code
ORDERING INFORMATION
See detailed ordering and shipping information on page 13 of
this data sheet.
Features
•
•
•
•
•
•
•
•
•
•
•
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•
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Bi−Directional Interface between Any Two Levels: 1.65 V to 5.5 V
No Direction Control Needed
Internal 10 kW Pull−Up Resistors
System GPIO Resources Not Required when OE Tied to VCCA
I2C Bus Isolation
A/B Port VOL = 175 mV (Typical), VIL = 150 mV, IOL = 6 mA
Open−Drain Inputs / Outputs
Works in Push Pull Environment
Accommodates Standard−Mode and Fast−Mode I2C−Bus Devices
Supports I2C Clock Stretching & Multi−Master
Fully Configurable: Inputs and Outputs Track VCC
Non−Preferential Power−Up; Either VCC Can Power−Up First
Outputs Switch to 3−State if Either VCC is at GND
Tolerant Output Enable: 5 V
Packaged in 8−Terminal Leadless MicroPakt (1.6 mm x 1.6 mm)
and Ultrathin MLP (1.2 mm x 1.4 mm)
ESD Protection Exceeds:
♦ B Port: 8 kV HBM ESD (vs. GND & vs. VCCB)
♦ All Pins: 4 kV HBM ESD (per JESD22−A114)
♦ 2 kV CDM (per JESD22−C101)
© Semiconductor Components Industries, LLC, 2011
August, 2021 − Rev. 2
1
Publication Order Number:
FXMAR2102/D
FXMAR2102
BLOCK DIAGRAM
OE
VCCB
Dynamic
Driver (with
Time Out)
10 kW
Internal Direction
Generator & Ctrl
V bias A
V bias B
B
A
VCCA
10 kW
Internal Direction
Generator & Ctrl
Dynamic Driver
(With Time Out)
Figure 1. Block Diagram, 1 of 2 Channels
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FXMAR2102
PIN CONFIGURATION
VCCB
B0
B1
OE
7
6
5
8
4
1
2
3
VCCA
A0
A1
VCCA
GND
A0
2
A1
3
GND
4
1
8
VCCB
7
B0
6
B1
5
OE
Figure 2. MicroPak (Top−Through View)
Figure 3. UMLP (Top−Through View)
PIN DEFINITIONS
Pin No.
Name
Description
1
VCCA
A−Side Power Supply
2, 3
A0, A1
A−Side Inputs or 3−State Outputs
4
GND
Ground
5
OE
6, 7
B1, B0
B−Side Inputs or 3−State Outputs
8
VCCB
B−Side Power Supply
Output Enable Input
TRUTH TABLE
Control
OE (Note 1)
Outputs
LOW Logic Level
3−State
HIGH Logic Level
Normal Operation
1. If the OE pin is driven LOW, the FXMAR2102 is disabled and the A0, A1, B0, and B1 pins (including dynamic drivers) are forced into 3−state
and all four 10 kW internal pull−up resisters are decoupled from their respective VCC.
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FXMAR2102
ABSOLUTE MAXIMUM RATINGS
Symbol
VCCA, VCCB
VIN
VO
Parameter
Min
Max
Unit
–0.5
7.0
V
A Port
–0.5
7.0
B Port
–0.5
7.0
Control Input (OE)
–0.5
7.0
An Outputs 3−State
–0.5
7.0
Bn Outputs 3−State
–0.5
7.0
An Outputs Active
–0.5
VCCA + 0.5 V
Bn Outputs Active
–0.5
VCCB + 0.5 V
Supply Voltage
DC Input Voltage
Output Voltage (Note 2)
V
IIK
DC Input Diode Current
At VIN < 0 V
−
–50
mA
IOK
DC Output Diode Current
At VO < 0 V
−
–50
mA
At VO > VCC
−
+50
IOH / IOL
–50
+50
mA
ICC
DC Output Source/Sink Current
DC VCC or Ground Current per Supply Pin
−
±100
mA
PD
Power Dissipation
−
0.129
mW
–65
+150
°C
Human Body Model, B−Port Pins
−
8
kV
Human Body Model, All Pins
(JESD22−A114)
−
4
Charged Device Mode, JESD22−C101
−
2
TSTG
Storage Temperature Range
ESD
Electrostatic Discharge Capability
At 400 KHz
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. IO absolute maximum rating must be observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCCA, VCCB
VIN
ΘJA
TA
Parameter
Min
Max
Unit
1.65
5.50
V
A−Port
0
5.5
V
B−Port
0
5.5
Control Input (OE)
0
VCCA
8−Lead MicroPak
−
279
8−Lead Ultrathin MLP
−
302
–40
+85
Power Supply Operating
Input Voltage (Note 3)
Thermal Resistance
Free Air Operating Temperature
°C/W
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
3. All unused inputs and I/O pins must be held at VCCI or GND. VCCI is the VCC associated with the input side.
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FXMAR2102
FUNCTIONAL DESCRIPTION
Power−Up / Power−Down Sequencing
The recommended power−up sequence is:
1. Apply power to the first VCC.
2. Apply power to the second VCC.
3. Drive the OE input HIGH to enable the device.
The recommended power−down sequence is:
1. Drive OE input LOW to disable the device.
2. Remove power from either VCC.
3. Remove power from the other VCC.
NOTE:
4. Alternatively, the OE pin can be hardwired to VCCA to
save GPIO pins. If OE is hardwired to VCCA, either VCC
can be powered up or down first.
FXM translators offer an advantage in that either VCC
may be powered up first. This benefit derives from the chip
design. When either VCC is at 0 V, outputs are in a
high−impedance state. The control input (OE) is designed to
track the VCCA supply. A pull−down resistor tying OE to
GND should be used to ensure that bus contention, excessive
currents, or oscillations do not occur during
power−up/−down. The size of the pull−down resistor is
based upon the current−sinking capability of the device
driving the OE pin.
APPLICATION CIRCUIT
VCCA
V CCB
0.1 mF
0.1 mF
1
8
V CCA
2
3
5
V CCB
A0
B0
A1
B1
OE
GND
R PD
4
Figure 4. Application Circuit
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7
6
FXMAR2102
APPLICATION NOTES
the Npassgates act as a low−resistive short between both
ports until either of the port’s VCC/2 thresholds are reached.
After the RC time constant has reached the VCC/2 threshold
of either port, the port’s edge detector triggers both dynamic
drivers to drive their respective ports in the LOW−to−HIGH
(LH) direction, accelerating the rising edge. The resulting
rise time resembles the scope shot in Figure 5. Effectively,
two distinct slew rates appear in rise time. The first slew rate
(slower) is the RC time constant of the bus. The second slew
rate (much faster) is the dynamic driver accelerating the
edge.
If both the A and B ports of the translator are HIGH, a
high−impedance path exists between the A and B ports
because both the Npassgates are turned off. If a master or
slave device decides to pull SCL or SDA LOW, that device’s
driver pulls down (Isink) SCL or SDA until the edge reaches
the A or B port VCC/2 threshold. When either the A or B port
threshold is reached, the port’s edge detector triggers both
dynamic drivers to drive their respective ports in the
HIGH−to−LOW (HL) direction, accelerating the falling
edge.
The FXMAR2102 has open−drain I/Os and includes a
total of four 10 kW internal pull−up resistors (RPU) on each
of the four data I/O pins, as shown in Figure 4. If a pair of
data I/O pins (An/Bn) is not used, both pins should
disconnected, eliminating unwanted current flow through
the internal RPUs. External RPUs can be added to the I/Os
to reduce the total RPU value, depending on the total bus
capacitance. The designer is free to lower the total pull−up
resistor value to meet the maximum I2C edge rate per the I2C
specification (UM10204 rev. 03, June 19, 2007). For
example, according to the I2C specification, the maximum
edge rate (30% − 70%) during Fast Mode (400 kbit/s) is
300 ns. If the bus capacitance is approaching the maximum
400 pF, a lower total RPU value helps keep the rise time
below 300 ns (Fast Mode). Likewise, the I2C specification
also specifies a minimum Serial Clock Line High Time of
600 ns during Fast Mode (400 kHz). Lowering the total RPU
also helps increase the SCL High Time. If the bus
capacitance approaches 400 pF, it may make sense to use the
FXMA2102, which does not contain internal RPUs. Then
calculate the ideal external RPU value.
NOTE:
5. Section 7.1 of the I2C specification provides an excellent
guideline for pull−up resistor sizing.
Theory of Operation
The FXMAR2102 is designed for high−performance
level shifting and buffer / repeating in an I2C application.
Figure 1 shows that each bi−directional channel contains
two series−Npassgates and two dynamic drivers. This
hybrid architecture is highly beneficial in an I2C application
where auto−direction is a necessity.
For example, during the following three I2C protocol
events:
• Clock Stretching
• Slave’s ACK Bit (9th bit = 0) following a Master’s Write
Bit (8th bit = 0)
• Clock Synchronization and Multi−Master Arbitration
The bus direction needs to change from master−to−slave
to slave−to−master without the occurrence of an edge. If
there is an I2C translator between the master and slave in
these examples, the I2C translator must change direction
when both A and B ports are LOW. The Npassgates can
accomplish this task very efficiently because, when both A
and B ports are LOW, the Npassgates act as a low−resistive
short between the A and B ports.
Due to I2C’s open−drain topology, I2C masters and slaves
are not push/pull drivers. Logic LOWs are “pulled down”
(Isink), while logic HIGHs are “let go” (3−state). For
example, when the master lets go of SCL (SCL always
comes from the master), the rise time of SCL is largely
determined by the RC time constant, where R = RPU and
C = the bus capacitance. If the FXMAR2102 is attached to
the master [on the A port] and there is a slave on the B port,
Figure 5. Waveform C: 600 pF, Total RPU: 2.2 kW
VOL vs. IOL
The I2C specification mandates a maximum VIL (IOL of
3 mA) of VCC · 0.3 and a maximum VOL of 0.4 V. If there
is a master on the A port of an I2C translator with a VCC of
1.65 V and a slave on the I2C translator B port with a VCC
of 3.3 V, the maximum VIL of the master is (1.65 V x 0.3)
495 mV. The slave could legally transmit a valid logic LOW
of 0.4 V to the master.
If the I2C translator’s channel resistance is too high, the
voltage drop across the translator could present a VIL to the
master greater than 495 mV. To complicate matters, the I2C
specification states that 6 mA of IOL is recommended for bus
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FXMAR2102
capacitances approaching 400 pF. More IOL increases the
voltage drop across the I2C translator. The I2C application
benefits when I2C translators exhibit low VOL performance.
Figure 6 depicts typical FXMAR2102 VOL performance vs.
the competition, given a 0.4 V VIL.
VOL: FXMAR2102 vs. Device B, VIL = 0.4 V
0.65
VOL (V):
0.6
0.55
Device B
VIL = 0.4 V
0.5
FXMAR2102
VIL = 0.4 V
0.45
0.4
0
2
4
6
8
10
IOL (mA):
Figure 6. Device Comparison
I2C−Bus Isolation
slave #2 to slave #1 and as the master. However, if the OE
pin is pulled LOW (disabled), both ports (A and B) are
3−stated. This results in the FXMAR2102 isolating slave #2
from the master and slave #1, allowing full communication
between the master and slave #1.
Bus Clear
Because the I2C specification defines the minimum SCL
frequency of DC, the SCL signal can be held LOW forever;
however, this condition shuts down the I2C bus. The I2C
specification refers to this condition as “Bus Clear”. In
Figure 7; if slave #2 holds down SCL forever, the master and
slave #1 are not able to communicate because the
FXMAR2102 passes the SCL stuck−LOW condition from
VCC to GND
If slave #2 is a camera that is suddenly removed from the
I2C bus, resulting in VCCB transitioning from a valid VCC
(1.65 V – 5.5 V) to 0 V; the FXMAR2102 automatically
forces SCL and SDA on both its A and B ports into 3−state.
Once VCCB has reached 0 V, full I2C communication
between the master and slave #1 remains undisturbed.
The FXMAR2102 supports I2C−Bus isolation for the
following conditions:
• Bus isolation if bus clear
• Bus isolation if either VCC goes to ground
Slave #1
Master
SCL
SCL
SDA
SDA
VCCA
VCCB
FXMAR2102
I2C Buffer
Translator
SCL
SDA
Slave #2
OE
OE: High Enable
Low Disable
VCCA: 1.65 V − 5.5 V VCC
Domain
Figure 7. Bus Isolation
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VCCB: 1.65 V − 5.5 V VCC
Domain
FXMAR2102
DC ELECTRICAL CHARACTERISTICS (TA = −40°C to +85°C)
Symbol
Typ
Max
Unit
High Level Input
Voltage A
Data Inputs An
1.65 – 5.50 1.65 – 5.50 VCCA – 0.4
−
−
V
Control Input OE
1.65 – 5.50 1.65 – 5.50 0.7 x VCCA
−
−
VIHB
High Level Input
Voltage B
Data Inputs Bn
1.65 – 5.50 1.65 – 5.50 VCCB – 0.4
−
−
V
VILA
Low Level Input
Voltage A
Data Inputs An
1.65 – 5.50 1.65 – 5.50
−
−
0.4
V
Control Input OE
1.65 – 5.50 1.65 – 5.50
−
−
0.3 x VCCA
VILB
Low Level Input
Voltage B
Data Inputs Bn
1.65 – 5.50 1.65 – 5.50
−
−
0.4
V
VOL
Low Level Output
Voltage
VIL = 0.15 V
1.65–5.50
−
−
0.4
V
VIHA
IL
IOFF
IOZ
Parameter
Condition
VCCA (V)
1.65–5.50
Min
IOL = 6 mA
−
VIN = VCCA
Input Leakage
Current
Control Input OE,
or GND
Power−Off Leakage
Current
An
VIN or VO = 0 V to
5.5 V
0
Bn
VIN or VO = 0 V to
5.5 V
An, Bn
3−State Output
Leakage
(Note 7)
VCCB (V)
1.65 – 5.50 1.65 – 5.50
−
−
±1.0
mA
5.50
−
−
±2.0
mA
5.50
0
−
−
±2.0
VO = 0 V to 5.5 V,
OE = VIL
5.50
5.50
−
−
±2.0
An
VO = 0 V to 5.5 V,
OE = Don’t Care
5.50
0
−
−
±2.0
Bn
VO = 0 V to 5.5 V,
OE = Don’t Care
0
5.50
−
−
±2.0
mA
ICCA/B
Quiescent Supply
Current (Note 8, 9)
VIN = VCCI or Floating, IO = 0
1.65 – 5.50 1.65 – 5.50
−
−
5.0
mA
ICCZ
Quiescent Supply
Current (Note 8)
VIN = VCCI or GND, IO = 0,
OE = VIL
1.65 – 5.50 1.65 – 5.50
−
−
5.0
mA
ICCA
Quiescent Supply
Current (Note 7)
VIN = 5.5 V or GND, IO = 0,
OE = Don’t Care, Bn to An
–2.0
mA
ICCB
Quiescent Supply
Current (Note 7)
VIN = 5.5 V or GND, IO = 0,
OE = Don’t Care, An to Bn
Resistor Pull−up
Value
VCCA & VCCB Sides
RPU
0
1.65 – 5.50
−
−
1.65 – 5.50
0
−
−
2.0
1.65 – 5.50
0
−
−
–2.0
0
1.65 – 5.50
−
−
2.0
1.65–5.50 1.65 – 5.50
−
10
−
mA
W
6. This table contains the output voltage for static conditions. Dynamic drive specifications are given in Dynamic Output Electrical
Characteristics.
7. “Don’t Care” indicates any valid logic level.
8. VCCI is the VCC associated with the input side.
9. Reflects current per supply, VCCA or VCCB.
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FXMAR2102
DYNAMIC OUTPUT ELECTRICAL CHARACTERISTICS
OUTPUT RISE / FALL TIME (Note 10) (Output load: CL = 50 pF, RPU = NC, push / pull driver, and TA = −40°C to +85°C.)
VCCO (Note 11)
4.5 to 5.5 V
3.0 to 3.6 V
2.3 to 2.7 V
1.65 to 1.95 V
Symbol
Parameter
Typ
Typ
Typ
Typ
Unit
trise
Output Rise Time; A Port, B Port (Note 12)
3
4
5
7
ns
tfall
Output Fall Time; A Port, B Port (Note 13)
1
1
1
1
ns
10. Output rise and fall times guaranteed by design simulation and characterization; not production tested.
11. VCCO is the VCC associated with the output side.
12. See Figure 12.
13. See Figure 13.
DYNAMIC OUTPUT ELECTRICAL CHARACTERISTICS
MAXIMUM DATA RATE (Note 14) (Output load: CL = 50 pF, RPU = NC, push / pull driver, and TA = −40°C to +85°C.)
VCCB
4.5 to 5.5 V
3.0 to 3.6 V
2.3 to 2.7 V
1.65 to 1.95 V
Minimums
VCCA
Direction
4.5 V to 5.5 V
A to B
50
50
40
30
B to A
50
50
40
40
A to B
50
50
40
19
B to A
50
50
40
40
A to B
40
40
30
19
B to A
40
40
30
30
A to B
40
40
30
19
B to A
30
30
19
19
3.0 V to 3.6 V
2.3 V to 2.7 V
1.65 V to 1.95 V
14. F−toggle guaranteed by design simulation; not production tested.
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Unit
MHz
MHz
MHz
MHz
FXMAR2102
AC CHARACTERISTICS (Note 15) (Output load: CL = 50 pF, RPU = NC, push / pull driver, and TA = −40°C to +85°C.)
VCCB
4.5 to 5.5 V
3.0 to 3.6 V
2.3 to 2.7 V
1.65 to 1.95 V
Typ
Max
Typ
Max
Typ
Max
Typ
Max
Unit
A to B
1
3
1
3
1
3
1
3
ns
B to A
1
3
2
4
3
5
4
7
A to B
2
4
3
5
4
6
5
7
B to A
2
4
2
5
2
6
5
7
OE to A
4
5
6
10
5
9
7
15
Symbol
Parameter
VCCA = 4.5 to 5.5 V
tPLH
tPHL
tPZL
tPLZ
OE to B
3
5
4
7
5
8
10
15
OE to A
65
100
65
105
65
105
65
105
OE to B
tskew
ns
ns
ns
5
9
6
10
7
12
9
16
0.50
1.50
0.50
1.00
0.50
1.00
0.50
1.00
ns
A to B
2.0
5.0
1.5
3.0
1.5
3.0
1.5
3.0
ns
B to A
1.5
3.0
1.5
4.0
2.0
6.0
3.0
9.0
A to B
2.0
4.0
2.0
4.0
2.0
5.0
3.0
5.0
B to A
2.0
4.0
2.0
4.0
2.0
5.0
3.0
5.0
OE to A
4.0
8.0
5.0
9.0
6.0
11.0
7.0
15.0
A Port, B Port (Note 16)
VCCA = 3.0 to 3.6 V
tPLH
tPHL
tPZL
tPLZ
OE to B
4.0
8.0
6.0
9.0
8.0
11.0
10.0
14.0
OE to A
100
115
100
115
100
115
100
115
OE to B
tskew
ns
ns
ns
5
10
4
8
5
10
9
15
0.5
1.5
0.5
1.0
0.5
1.0
0.5
1.0
ns
A to B
2.5
5.0
2.5
5.0
2.0
4.0
1.0
3.0
ns
B to A
1.5
3.0
2.0
4.0
3.0
6.0
5.0
10.0
A to B
2.0
5.0
2.0
5.0
2.0
5.0
3.0
6.0
B to A
2.0
5.0
2.0
5.0
2.0
5.0
3.0
6.0
OE to A
5.0
10.0
5.0
10.0
6.0
12.0
9.0
18.0
A Port, B Port (Note 16)
VCCA = 2.3 to 2.7 V
tPLH
tPHL
tPZL
tPLZ
tskew
ns
ns
OE to B
4.0
8.0
4.5
9.0
5.0
10.0
9.0
18.0
OE to A
100
115
100
115
100
115
100
115
OE to B
65
110
65
110
65
115
12
25
A Port, B Port (Note 16)
0.5
1.5
0.5
1.0
0.5
1.0
0.5
1.0
ns
ns
ns
VCCA = 1.65 to 1.95 V
tPLH
tPHL
tPZL
tPLZ
tskew
A to B
4
7
4
7
5
8
5
10
B to A
1.0
2.0
1.0
2.0
1.5
3.0
5.0
10.0
A to B
5
8
3
7
3
7
3
7
B to A
4
8
3
7
3
7
3
7
OE to A
11
15
11
14
14
28
14
23
OE to B
6
14
6
14
6
14
9
16
OE to A
75
115
75
115
75
115
75
115
OE to B
75
115
75
115
75
115
75
115
A Port, B Port (Note 16)
0.5
1.5
0.5
1.0
0.5
1.0
0.5
1.0
ns
ns
ns
ns
15. AC characteristics are guaranteed by design and characterization.
16. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (An or Bn) and switching
with the same polarity (LOW−to−HIGH or HIGH−to−LOW) (see Figure 15). Skew is guaranteed; not production tested.
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10
FXMAR2102
CAPACITANCE (TA = +25°C.)
Parameter
Symbol
Condition
Typ
Unit
CIN
Input Capacitance Control Pin (OE)
VCCA = VCCB = GND
2.2
pF
CI/O
Input/Output Capacitance, An, Bn
VCCA = VCCB = 5.0 V, OE = GND
13
pF
Figure 8. AC Test Circuit
Table 1. PROPAGATION DELAY TABLE (Note 17)
Test
Input Signal
Output Enable Control
tPLH, tPHL
Data Pulses
VCCA
tPZL (OE to An, Bn)
0V
LOW to HIGH Switch
tPLZ (OE to An, Bn)
0V
HIGH to LOW Switch
17. For tPZL and tPLZ testing, an external 2.2 kW pull−up resister to VCCO is required in order to force the I/O pins high while OE is Low because
when OE is low, the internal 10 kW RPUs are decoupled from their respective VCC’s.
Table 2. AC LOAD TABLE
VCCO
CL
RL
1.8 ±0.15 V
50 pF
NC
2.5 ±0.2 V
50 pF
NC
3.3 ±0.3 V
50 pF
NC
5.0 ±0.5 V
50 pF
NC
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11
FXMAR2102
TIMING DIAGRAMS
DATA
IN
VCCI
Vmi
t pxx
GND
OUTPUT
CONTROL
t pxx
Vmo
VCCO
DATA
OUT
Vmi
GND
Symbol
VCC
Vmi (Note 19)
VCCI / 2
Vx
VOL
VOL
(Note 18)
t PLZ
DATA
OUT
VY
Figure 10. 3−STATE Output Low Enable Time
Figure 9. Waveform for Inverting and
Non−Inverting Functions (Note 18)
VCCA
GND
t PZL
DATA
OUT
OUTPUT
CONTROL
VCCA
Vmi
Vmo
VCCO / 2
VX
0.5 x VCCO
VY
0.1 x VCCO
Figure 11. 3−STATE Output High Enable Time
(Note 18)
Figure 12. Active Output Rise Time
Figure 13. Active Output Fall Time
DATA
OUTPUT
tperiod
DATA
IN
VCCI / 2
Vmo
t skew
VCCI / 2
F−toggle rate, f = 1 / tperiod
VCCI
DATA
OUTPUT
GND
VCCO
Vmo
GND
t skew
Vmo
Vmo
tskew = (tpHLmax – tpHLmin) or (tpLHmax – tpLHmin)
Figure 14. F−Toggle Rate
Figure 15. Output Skew Time
NOTES:
18. Input tR = tF = 2.0 ns, 10% to 90% at VIN = 1.65 V to 1.95 V;
Input tR = tF = 2.0 ns, 10% to 90% at VIN = 2.3 V to 2.7 V;
Input tR = tF = 2.5 ns, 10% to 90%, at VIN = 3.0 V to 3.6 V only;
Input tR = tF = 2.5 ns, 10% to 90%, at VIN = 4.5 V to 5.5 V only.
19. VCCI = VCCA for control pin OE or Vmi = (VCCA / 2).
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12
VCCO
GND
FXMAR2102
ORDERING INFORMATION
Part Number
FXMAR2102L8X
Operating Temperature Range
Top Mark
Package
Packing Method†
−40 to +85°C
BU
8−Lead MicroPak, 1.6 mm Wide
(Pb−Free)
5000 / Tape & Reel
FXMAR2102UMX
8−Lead Ultrathin MLP, 1.2 mm x 1.4 mm
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MicroPak is trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
onsemi is licensed by the Philips Corporation to carry the I2C bus protocol.
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13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UQFN8, 1.4x1.2, 0.4P
CASE 523AS
ISSUE B
SCALE 4:1
DATE 19 AUG 2021
GENERIC
MARKING DIAGRAM*
XXM
1
XX = Specific Device Code
M = Date Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON58906E
UQFN8, 1.4X1.2, 0.4P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UQFN8 1.6X1.6, 0.5P
CASE 523AY
ISSUE O
0.05
C
A
1.60
DATE 31 AUG 2016
0.40
(6X)
1.60
B
0.45
(2X)
2X
1.60
TOP VIEW
PIN#1 IDENT
0.05
1.61
C
0.50
RECOMMENDED
LAND PATTERN
0.50±0.05
0.05
C
0.05
C
0.25
(8X)
NOTES:
SEATING
PLANE
0.025±0.025
A. PACKAGE CONFORMS TO JEDEC MO−255
VARIATION UAAD.
C
B. DIMENSIONS ARE IN MILLIMETERS.
SIDE VIEW
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009.
1.60±0.05
(0.10)
D. LAND PATTERN RECOMMENDATION IS
EXISTING INDUSTRY LAND PATTERN.
(0.20)3X
DETAIL A
1
2
3
(0.20)
(0.09)
4
8
1.60±0.05
0.30±0.05
0.30±0.05 (7X)
7
6
5
0.50
1.00±0.05
(0.15)
0.20±0.05 (8X)
BOTTOM VIEW
DOCUMENT NUMBER:
DESCRIPTION:
98AON13591G
UQFN8 1.6X1.6, 0.5P
0.30±0.05
0.10
C
0.05
C
A
B
DETAIL A
SCALE : 2X
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
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vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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