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FXWA9306
Dual Bi-Directional I2C-Bus® and SMBus Voltage-Level
Translator
Features
Description
2-Bit Bi-Directional Translator for SDA and SCL
2
Lines in Mixed-Mode I C-Bus Applications
Standard-Mode, Fast-Mode, and Fast-Mode-Plus
2
I C-Bus and SMBus Compatible
Less than 1.5ns Maximum Propagation Delay
to Accommodate Standard-Mode and Fast-Mode
2
I C-Bus Devices and Multiple Masters
Allows Voltage Level Translation Between:
The FXWA9306 is a dual, bi-directional, I C-bus and
SMBus, voltage-level translator with an enable (OE)
input that is operational from 1.0V to 3.6V (VCCA) and
1.8V to 5.5V (VCCB) without requiring a direction pin.
2
As with standard I C-bus systems, pull-up resistors are
required to provide the logic HIGH levels on the
translator’s bus. The FXWA9306 has a standard open2
drain configuration of the I C-bus. The size of these pullup resistors depends on the system, but each side of
the translator must have a pull-up resistor. The device is
designed to work with Standard-Mode, Fast-Mode, and
2
Fast Mode Plus I C-bus devices in addition to SMBus
devices. The maximum frequency is dependent on the
RC time constant, but generally supports > 2MHz.
2
VCCA = 1.0 to 3.6V and VCCB = 1.8- 5.0V
Supports I C Clock Stretching and Multi-Master
Low 3.5Ω On-State Connection Between Input and
Output Ports; Provides Less Signal Distortion
Open-Drain I C-Bus I/O Ports (A0, A1, B0, and B1)
Lock-Up-Free Operation
2
Provides Bi-directional Voltage Translation without
Direction Pin
2
2
5V-Tolerant I C-Bus I/O Ports to Support MixedMode Signal Operation
All channels have the same electrical characteristics
and there is a minimum deviation from one output to
another in voltage or propagation delay. This is a benefit
over discrete transistor voltage translation solutions,
since the fabrication of the switch is symmetrical. The
translator provides excellent ESD protection to lower
voltage devices and at the same time protects less-ESD
resistant devices.
VCCA
Flow-Through Pinout for Simpler Printed-Circuit
Board Trace Routing
Packaged in 8-Terminal Leadless MicroPak™
(1.6mm x 1.6mm) and MSOP8 (TSSOP8)
VCCB
2
7
FXWA9306
8
A0
A1
3
4
6
SW
OE
B0
5
SW
B1
1
GND
Figure 1.
Block Diagram
Ordering Information
Part Number
Operating
Top Mark
Temperature Range
Package
Packing Method
FXWA9306L8X
-40 to +85°C
LT
8-Lead, MicroPak™, 1.6mm Wide
5000 Units on
Tape and Reel
FXMA9306MUX
-40 to +85°C
9306
8-Lead, MSOP Package, 3mm Wide
4000 Units on
Tape and Reel
© 2015 Fairchild Semiconductor Corporation
FXWA9306 • Rev. 1.6
www.fairchildsemi.com
FXWA9306 — Dual Bi-Directional I2C-Bus® and SMBus Voltage-Level Translator
September 2016
B0
B1
VCCB
6
5
1
2
3
VCCA
A0
4
GND
8
OE
Figure 2.
7
A1
MicroPak™ (Top-Through View)
GND
1
8
OE
VCCA
2
7
VCCB
A0
3
6
B0
A1
4
5
B1
Figure 3. MSOP (Top-Through View)
Pin Definitions
Pin #
Name
Description
1
GND
Ground
2
VCCA
Low Voltage A-Side Power Supply
3
A0
A-Side Input or 3-State Output. Connect to VCCA through a pull-up resistor.
4
A1
A-Side Input or 3-State Output. Connect to VCCA through a pull-up resistor.
5
B1
B-Side Input or 3-State Output. Connect to VCCB through a pull-up resistor.
6
B0
B-Side Input or 3-State Output. Connect to VCCB through a pull-up resistor.
7
VCCB
8
OE
High Voltage B-Side Power Supply
Output Enable Input; connect to VCCB and pull-up through a high resistor.
Truth Table
Control
FXWA9306 — Bi-Directional I2C-Bus® and SMBus Voltage-Level Translator
Pin Configuration
Outputs
OE
LOW Logic Level
3-State
HIGH Logic Level
Normal Operation; A0 = B0, A1 = B1
Note:
1. If the OE pin is driven LOW, the FXWA9306 is disabled and the A0, A1, B0, and B1 pins are forced into 3-state.
2. OE references VCCB and the OE logic levels should be at least 1V higher than VCCA, for best translator operation.
© 2012 Fairchild Semiconductor Corporation
FXWA9306 • Rev. 1.6
www.fairchildsemi.com
2
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
–0.5
7.0
A Port
–0.5
7.0
B Port
–0.5
7.0
Control Input (OE)
–0.5
7.0
An Outputs 3-State
–0.5
7.0
Bn Outputs 3-State
–0.5
7.0
An Outputs Active
–0.5
VCCA + 0.5V
Bn Outputs Active
–0.5
VCCB + 0.5V
VCCA, VCCB Supply Voltage
VIN
VO
DC Input Voltage
Output Voltage
(3)
ICH
DC Channel Current
IIK
DC Input Diode Current
IOK
DC Output Diode Current
IOH / IOL
ICC
TSTG
ILATCHUP
V
90
mA
–50
mA
At VO < 0V
–50
At VO > VCC
+50
–50
DC Output Source/Sink Current
DC VCC or Ground Current per Supply Pin
–65
Storage Temperature Range
Latch-up Performance Above VCC and below GND at 125°C
Electrostatic Discharge
Capability
V
At VIN < 0V
Human Body Model, JESD22-A114-A
ESD
Units
Human Body Model, Pin to Pin, B Port
mA
+50
mA
±100
mA
+150
°C
+100
mA
> 4000
(4)
> 8000
Charged Device Model, JESD22-A115-A
V
> 1000
Notes:
3. IO absolute maximum rating must be observed.
4. Test conditions: B0 and B1 vs. VCCB, B0 and B1 vs. GND, VCCB vs. GND
FXWA9306 — Bi-Directional I2C-Bus® and SMBus Voltage-Level Translator
Absolute Maximum Ratings
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Units
VCCA
Power Supply Operating
1.0
5.5
V
VCCB
Power Supply Operating
1.8
5.5
V
A Port
0
5.5
B Port
0
5.5
Control Input (OE)
0
5.5
VIN
JA
ISW(pass)
TA
Input Voltage
Thermal Resistance, Junction to Ambient
Pass Switch Current
Free Air Operating Temperature
V
470
C°/W
0
64
mA
–40
+85
°C
Notes:
5. All unused inputs and I/O pins must be held at VCCI or GND.
6. VCCA < VCCB -1V for best results in level-shifting applications.
© 2012 Fairchild Semiconductor Corporation
FXWA9306 • Rev. 1.6
www.fairchildsemi.com
3
Unless otherwise noted, values are at TA = –40°C to +85°C; all typical values are at TA = 25°C.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VIK
Input Clamping Voltage
II = -18mA; VI(OE) = 0V
IIH
High-Level Input Current
VI = 5V; VI(OE) = 0V
Ci(OE)
OE Pin Input Capacitance
VI = 3V or 0V
Ci/O(off)
Off-State I/O Pin Capacitance
A0, A1, B0, B1
VO = 3V or 0V; VI(OE) = 0V
4
6
pF
Ci/O(on)
On-State I/O Pin Capacitance
A0, A1, B0, B1
VO = 3V or 0V; VI(OE) = 3V
9.3
12.5
pF
VI(OE) = 4.5V
2.4
5.0
VI(OE) = 3V
3.0
6.0
VI(OE) = 2.3V
3.8
8.0
VI(OE) = 1.5V
9.0
20.0
(7)
RON
VOL
On-State Resistance A0/B0,
A1/B1
Voltage Output Low
-1.2
V
5
µA
7.1
VI = 0V;
IO = 64mA
VCCA = 1V,
VPUD = 5V,
IOL = 3mA
(B->A Dir)
pF
VIN (B0 or B1) = 0.1V
0.15
VIN (B0 or B1) = 0.2V
0.25
VIN (B0 or B1) = 0.3V
0.35
VIN (B0 or B1) = 0.4V
0.45
Ω
V
Notes:
7. Measured by the voltage drop between the A0 and B0 or A1 and B1 terminals at the indicated current through
the switch. On-state resistance is determined by the lowest voltage of the two terminals.
© 2012 Fairchild Semiconductor Corporation
FXWA9306 • Rev. 1.6
FXWA9306 — Bi-Directional I2C-Bus® and SMBus Voltage-Level Translator
DC Electrical Characteristics
www.fairchildsemi.com
4
TA = –40°C to +85°C. Direction is from B port to A port (translating down). Values guaranteed by design.
Symbol
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Parameter
Low-to-High Propagation Delay,
from (Input) B0 or B1 to (Output)
A0 or A1
High-to-Low Propagation Delay,
from (Input) B0 or B1 to (Output)
A0 or A1
Low-to-High Propagation Delay,
from (Input) B0 or B1 to (Output)
A0 or A1
High-to-Low Propagation Delay,
from (Input) B0 or B1 to (Output)
A0 or A1
Low-to-High Propagation Delay,
from (Input) A0 or A1 to (Output)
B0 or B1
High-to-Low Propagation Delay,
from (Input) A0 or A1 to (Output)
B0 or B1
Low-to-High Propagation Delay,
from (Input) A0 or A1 to (Output)
B0 or B1
High-to-Low Propagation Delay,
from (Input) A0 or A1 to (Output)
B0 or B1
© 2012 Fairchild Semiconductor Corporation
FXWA9306 • Rev. 1.6
Conditions
VI(OE) = 3.3V; VIH = 3.3V;
VIL = 0V; VM = 1.15V;
VCCA = 2.3V
VI(OE) = 2.5V; VIH = 2.5V;
VIL = 0V; VM = 0.75V;
VCCA = 1.5V
VI(OE) = 3.3V; VIH = 2.3V;
VIL = 0V; VTT = 3.3V;
VM = 1.15V; VCCA = 2.3V;
RL = 300Ω
VI(OE) = 2.5V; VIH = 1.5V;
VIL = 0V; VTT = 2.5V;
VM = 0.75V; VCCA = 1.5V;
RL = 300Ω
Load
Condition:
Min:
Max.
CL = 15pF
0
0.60
CL = 30pF
0
1.20
CL = 50pF
0
2.00
CL = 15pF
0
0.75
CL = 30pF
0
1.50
CL = 50pF
0
2.00
CL = 15pF
0
0.60
CL = 30pF
0
1.20
CL = 50pF
0
2.00
CL = 15pF
0
0.75
CL = 30pF
0
1.50
CL = 50pF
0
2.00
CL = 15pF
0
0.50
CL = 30pF
0
1.00
CL = 50pF
0
1.75
CL = 15pF
0
0.80
CL = 30pF
0
1.65
CL = 50pF
0
2.75
CL = 15pF
0
0.50
CL = 30pF
0
1.00
CL = 50pF
0
1.75
CL = 15pF
0
1.00
CL = 30pF
0
2.00
CL = 50pF
0
3.30
Units
ns
ns
ns
ns
ns
ns
ns
ns
FXWA9306 — Bi-Directional I2C-Bus® and SMBus Voltage-Level Translator
AC Electrical Characteristics
www.fairchildsemi.com
5
RL
From output under test
S1
S2 (open)
CL
Load Circuit
VIH
Input
VM
VM
VIL
VOH
Output
VM
VM
VOL
Timing Diagram
Figure 4.
Load Circuit
Notes:
8. S1 = translating up (A-to-B direction), S2 = translating down (B-to-A direction).
9. CL includes probe and jig capacitance.
10. All input pulses are supplied by generators having the following characteristics: PRR < 10MHz; ZO = 50Ω;
tr < 2ns; tf < 2ns.
11. The outputs are measured one at a time, with one transmission per measurement.
© 2012 Fairchild Semiconductor Corporation
FXWA9306 • Rev. 1.6
FXWA9306 — Bi-Directional I2C-Bus® and SMBus Voltage-Level Translator
VTT
www.fairchildsemi.com
6
VPU(D) = 3.3V (1)
VPU(D) = 3.3V (2)
3.3V Enable Signal (2)
OFF ON
200KΩ
1.8V
2
RPU
SCL
I2C-Bus
Master
SDA
1.8V
OE 8
VCCA
VCCB
VCC
200KΩ
FXWA9306
(1)
RPU
RPU
2
7
RPU
4 A1
SW
SW
VCC
6
SCL
VCC
B1 5
SDA
I2C-Bus
Device
I2C-Bus
Master
GND
GND
B0
GND
OE 8
VCCA
VCCB
RPU
3 A0
FXWA9306
(2)
SCL
SDA
RPU
RPU
3 A0
SW
4 A1
SW
6
SCL
VCC
B1 5
SDA
I2C-Bus
Device
B0
GND
GND 1
GND 1
Figure 5.
RPU
7
Application (Switch Always Enabled)
Figure 6.
Application (Switch Enable Control)
Note:
12. The applied voltages at VCCA and VPU(D) should be such that VCCB is at least 1V higher than VCCA for best
translator operation.
Bi-directional Translation
For the bi-directional clamping configuration (higher
voltage to lower voltage or lower voltage to higher
voltage), the OE input must be connected to VCCB and
both pins pulled to HIGH side VPU(D) through a pull-up
resistor (typically 200kΩ). This allows VCCB to regulate
the OE input. A filter capacitor on VCCB is recommended.
2
The I C-bus master output can be totem-pole or open2
drain (pull-up resistors may be required) and the I C-bus
device output can be totem-pole or open-drain (pull-up
resistors are required to pull the B0 and B1 outputs to
VPU(D)). However, if either output is totem-pole, data
must be uni-directional or the outputs must be 3-
Table 1.
stateable and be controlled by some direction-controlled
mechanism to prevent HIGH-to-LOW contentions in
either direction. If both outputs are open-drain, no
direction control is needed.
The reference supply voltage (VCCA) is connected to the
processor core power supply voltage. When VCCB is
connected through a 200kΩ resistor to a 3.3V - 5.5V VPU(D)
power supply, and VCCA is set between 1.0V and (VPU(D) –
1V), the output of each A0 and A1 has a maximum output
voltage equal to VCCA and the output of each B0 and B1
has a maximum output voltage equal to VPU(D).
Application Operating Conditions (refer to Figure 6)
All typical values are at TA = 25°C.
Symbol
Min.
Typ.
Max.
Unit
Reference Bias Voltage
VCCA + 0.6
2.1
5.0
V
VI(OE)
OE Pin Input Voltage
VCCA + 0.6
2.1
5.0
V
VCCA
Reference Voltage
0
1.5
4.4
V
VBIAS(VCCB)
ISW(pass)
Parameter
Conditions
Pass Switch Current
IREF
Reference Current
Transistor
TA
Ambient Temperature
Operating in Free Air
-40
14
mA
5
µA
+85
0
FXWA9306 — Bi-Directional I2C-Bus® and SMBus Voltage-Level Translator
Application Information
C
Sizing Pull-Up Resistor
The pull-up resistor value needs to limit the current
through the pass transistor when it is in the on state to
about 15mA. This ensures a pass voltage of 260mV to
350mV. If the current through the pass transistor is
higher than 15mA, the pass voltage is higher in the on
state. To set the current through each pass transistor at
15mA, the pull-up resistor value is calculated as:
RPU
VPU D 0.35V
0.015A
© 2012 Fairchild Semiconductor Corporation
FXWA9306 • Rev. 1.6
Table 2 summarizes the resistor reference voltages and
currents at 15mA, 10mA, and 3mA. The resistor values
shown in the +10% column or a larger value should be
used to ensure that the pass voltage of the transistor
would be 350mV or less. The external driver must be
able to sink the total current from the resistors on both
sides of the of the FXWA9306 device at 0.175V,
although the 15mA only applies to the current flowing
through the FXWA9306 device.
(1)
www.fairchildsemi.com
7
Application Operating Conditions
Calculated for VOL = 0.35V; assumes output driver VOL = 0.175V at stated current.
Pull-Up Resistor Value (Ω)
VPU(D)
15mA
Nominal
10mA
+10%
(13)
Nominal
3mA
+10%
(13)
Nominal
+10%
(13)
5.0V
310
341
465
512
1550
1705
3.3V
197
217
295
325
983
1082
2.5V
143
158
215
237
717
788
1.8V
97
106
145
160
483
532
1.5V
77
85
115
127
383
422
1.2V
57
63
85
94
283
312
Note:
13. +10% to compensate for VCC range and resistor tolerance.
Maximum Frequency Calculation
The maximum frequency is totally dependent upon the
specifics of the application. The FXWA9306 behaves
like a wire with the additional characteristics of transistor
device physics and should be capable of performing at
higher frequencies if used correctly.
line length of concern is on the 1.8V side because it is
driven through the on resistance of the FXWA9306. If
the line length on the 1.8V side is long enough, there
can be a reflection at the chip / terminating end of the
wire when the transition time is shorter than the time of
flight of the wire. This is because the FXWA9306 looks
like a high-impedance path compared to the wire. If the
wire is too long and the lumped capacitance is not
excessive, the signal is only slightly degraded by the
series resistance added by passing through the
FXWA9306. If the lumped capacitance is large, the rise
time deteriorates. The fall time is much less affected
and if the rise time is slowed down too much, the duty
cycle of the clock is degraded and, at some point, the
clock is no longer useful. So, the principle design
consideration is to minimize the wire length and the
capacitance on the 1.8V side for the clock path. A pullup resistor on the 1.8V side can be used to trade a
slower fall time for a faster rise time and can also
reduce overshoot in some cases.
Here are some guidelines to follow that help maximize
the performance of the device:
Keep trace lengths to a minimum by placing the
FXWA9306 close to the processor.
The trace length should be less than half the time of
flight to reduce ringing and reflections.
The faster the edge of the signal, the higher the
chance of ringing.
The greater the drive strength (up to 15mA), the
higher the frequency the device can use.
In a 3.3V to 1.8V direction level shift, if the 3.3V side is
being driven by a totem-pole type driver; no pull-up
resistor is needed on the 3V side. The capacitance and
FXWA9306 — Bi-Directional I2C-Bus® and SMBus Voltage-Level Translator
Table 2.
Additional Note
The FXWA9306 is not a bus buffer that provides both
level translation and physical capacitance isolation to
either side of the bus when both sides are connected.
The FXWA9306 only isolates the sides when the device
is disabled and provides level translation when active.
When the A1 or B1 port is LOW, the clamp is in the ONstate and a low-resistance connection exists between
the A1 and B1 ports. Assuming the higher voltage is on
the B1 port, when the B1 port is HIGH, the voltage on
the A1 port is limited by the voltage set by V CCA. When
the A1 port is HIGH, the B1 port is pulled to the drain
pull-up supply voltage (VPU(D)) by the pull-up resistors.
This functionality allows a seamless translation between
higher and lower voltages selected by the user without
the need for directional control. The A0/B0 channel also
functions as the A1/B1 channel.
The FXWA9306 can be used to run two buses: one at
400kHz operating frequency and the other at 100kHz
operating frequency. If the two buses are operating at
different frequencies, the 100kHz bus must be isolated
when the 400kHz operation of the bus is required. If the
master is running at 400kHz, the maximum system
operating frequency may be less than 400kHz because
of the delays added to the translator.
© 2012 Fairchild Semiconductor Corporation
FXWA9306 • Rev. 1.6
www.fairchildsemi.com
8
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THEREOF SHALL BE MADE OTHER THAN AS A REFERENCE FOR PROPOSALS AS SUBMITTED
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REVISIONS
WITH SUCH PROPOSALS UNLESS THE CONSENT OF SAID FAIRCHILD SEMICONDUCTOR COR-
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COPIED OR DUPLICATED OR ITS CONTENTS DISCLOSED. THE INFORMATION CONTAINED
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DATE
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QUADRANT
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0.65
TOP VIEW
LAND PATTERN RECOMMENDATION
A
1.10 MAX
0.15
0.05
0.65
SIDE VIEW
C
0.38
0.27
0.10 M
0.23
0.13
END VIEW
12°
TOP & BOTTOM
A B C
GAUGE
PLANE
SEATING
PLANE
0°-8
NOTES: UNLESS OTHERWISE SPECIFIED
A. THIS PACKAGE CONFORMS TO JEDEC MO-187.
B. ALL DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH AND TIE BAR EXTRUSIONS.
D. DIMENSIONS AND TOLERANCES AS PER ASME
Y14.5-1994.
E. LAND PATTERN AS PER IPC7351#TSOP65P490X110-8BL
F. FILE NAME: MKT-MUA08AREV4
0.70
0.40
0.25
0.95
DETAIL A
SCALE 20 : 1
APPROVALS
DRAWN:
BOBOY MALDO
CHECKED:
KH LEE
APPROVED:
BY HUANG
DATE
24SEP09
8LD, MSOP, JEDEC
MO-187, 3.0MM WIDE
.
APPROVED:
HOWARD ALLEN
SCALE
PROJECTION
[MM]
INCH
1:1
SIZE
N/A
DRAWING NUMBER
FORMERLY: N/A
REV
MKT-MUA08A
SHEET :
4
1 OF 1
A
1.60±0.10
PIN #1
IDENT
B
1.60±0.10
0.45
(2X)
1.60
0.40 (6X)
TOP VIEW
0.025±0.025
1.61
0.50±0.05
SEATING PLANE
C
0.50
SIDE VIEW
0.25 (8X)
(0.20) 3X
(0.10)
DETAIL A
1
2
3
RECOMMENDED LAND PATTERN
(0.20)
(0.09)
(0.15)
4
8
0.30±0.05
0.30±0.05 (7X)
7
6
5
0.50
1.00±0.05
BOTTOM VIEW
0.20±0.05(8X)
0.10 C A B
0.05 C
NOTES:
A. PACKAGE CONFORMS TO JEDEC MO-255
VARIATION UAAD.
B. DIMENSIONS ARE IN MILLIMETERS.
C. LAND PATTERN RECOMMENDATION IS
EXISTING INDUSTRY LAND PATTERN.
D. DRAWING FILENAME: MKT-MAC08ArevE.
0.30±0.05
DETAIL A
SCALE 2:1
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