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GF001H
Green-Mode Fairchild Power Switch (FPS™)
Description
Features
Advanced Burst Mode Operation at No-Load
Condition
700 V High-Voltage JFET Startup Circuit
Internal Avalanche-Rugged 700 V SenseFET
Built-in 5 ms Soft-Start
Peak-Current-Mode Control
The GF001H is a next-generation, Green-Mode
Fairchild Power Switch (FPS™). It integrates an
advanced current-mode Pulse Width Modulator (PWM)
and an avalanche-rugged 700 V SenseFET in a single
package, allowing auxiliary power designs with higher
standby energy efficiency, reduced size, improved
reliability, and lower system cost than previous
solutions.
A new frequency modulation reduces EMI emission and
built-in synchronized slope compensation allows stable
peak-current-mode control over a wide range of input
voltage.
Cycle-by-Cycle Current Limiting
Leading-Edge Blanking (LEB)
Synchronized Slope Compensation
Frequency Modulation to Attenuating EMI
Internal Overload / Open-Loop Protection (OLP)
VDD Under-Voltage Lockout (UVLO)
Requiring a minimum number of external components,
the GF001H provides a solid platform for cost-effective
flyback converter design with low standby power
consumption.
VDD Over-Voltage Protection (OVP)
Internal Auto-Restart Circuit (OLP, VDD OVP)
Adjustable Peak Current Limit
Ordering Information
Part Number
SenseFET
Operating
Temperature Range
Package
Packing Method
GF001HN
2 A 700 V
-40°C to +105°C
8-Pin, Dual Inline Package (DIP)
Tube
© 2014 Fairchild Semiconductor Corporation
GF001H • Rev. 1.1
www.fairchildsemi.com
GF001H — Green-Mode Fairchild Power Switch (FPS™)
May 2016
N
EMI
Filter
+
+
+
L
HV
IPK
Drain
PWM
VDD
FB
GND
+
Figure 1. Typical Flyback Application
Output Power Table (1)
230 VAC ±15%
Product
Adapter
GF001HN
(3)
(2)
85-265 VAC
Open-Frame
14 W
(4)
Adapter
20 W
(3)
Open-Frame
11 W
(4)
16 W
Notes:
1. The maximum output power can be limited by junction temperature.
2. 230 VAC or 100/115 VAC with voltage doublers.
3. Typical continuous power in a non-ventilated enclosed adapter, with sufficient drain pattern of printed circuit
board (PCB) as a heat sink, at 50°C ambient.
4. Maximum practical continuous power in an open-frame, design with sufficient drain pattern of printed circuit
board (PCB) as a heat sink, at 50°C ambient.
Block Diagram
HV
Drain
5
6,7,8
Line Voltage
Sample Circuit
Re-start
Protection
Brownout Protection
OVP
OLP
OTP
Soft
Driver
VPWM
HV
Start-up
VDD
Internal
BIAS
2
S
Oscillator
with EMI attenuator
Q
R
UVLO
Soft-start
Comparator
12V/6V
Soft-start
Green
Mode
Current Limit
Comparator
VLimit
Debounce
OVP
1
GND
3
FB
PWM
Comparator
VDD-OVP
5.4V
Max.
Duty
Slope
Compensation
VPWM
3R
3.5V
IPK
R
50µA
OLP
IPK
ZFB
4
S/H
VLimit
OLP
Delay
OLP
Comparator
4.6V
Figure 2. Internal Block Diagram
© 2014 Fairchild Semiconductor Corporation
GF001H • Rev. 1.1
www.fairchildsemi.com
2
GF001H — Green-Mode Fairchild Power Switch (FPS™)
Application Diagram
GF001H — Green-Mode Fairchild Power Switch (FPS™)
Marking Information
8
F – Fairchild Logo
Z – Plant Code
X – 1-Digit Year Code
Y – 1-Digit Week Code
TT – 2-Digit Die Run Code
T – Package Type (N: DIP)
M – Manufacture Flow Code
ZXYTT
GF001H
TM
1
Figure 3. Top Mark
Pin Configuration
GND
1
8
Drain
VDD
2
7
Drain
FB
3
6
Drain
IPK
4
5
HV
Figure 4.
Pin Assignment
Pin Definitions
Pin #
Name
Description
1
GND
Ground. This pin internally connects to the SenseFET source and signal ground of the PWM
controller.
2
VDD
Supply Voltage of the IC. Typically the hold-up capacitor connects from this pin to ground. A
rectifier diode in series with the transformer auxiliary winding connects to this pin to supply bias
during normal operation.
3
FB
Feedback. The signal from the external compensation circuit connects to this pin. The PWM duty
cycle is determined by comparing the signal on this pin and the internal current-sense signal.
4
IPK
Adjust Peak Current. Typically a resistor connects from this pin to the GND pin to program the
current-limit level. The internal current source (50 µA) introduces voltage drop across the
resistor, which determines the current-limit level of pulse-by-pulse current limit.
5
HV
Startup. Typically, resistors in serious from DC line connect to this pin to supply internal bias and
to charge the external capacitor connected between the VDD pin and the GND pin during
startup. This pin is also used to sense the line voltage for brownout protection.
6
7
Drain
SenseFET Drain. This pin is designed to directly drive the transformer.
8
© 2014 Fairchild Semiconductor Corporation
GF001H • Rev. 1.1
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VDRAIN
Parameter
Min.
(5,6)
Drain Pin Voltage
(7)
Max.
Unit
700
V
IDM
Drain Current Pulsed
EAS
Single Pulsed Avalanche Energy
VDD
DC Supply Voltage
VFB
FB Pin Input Voltage
-0.3
VIPK
IPK Pin Input Voltage
-0.3
VHV
HV Pin Input Voltage
PD
Power Dissipation (TA＜50°C)
1.5
W
TJ
Operating Junction Temperature
-40
Internally
(9)
Limited
C
Storage Temperature Range
-55
+150
C
+260
C
TSTG
TL
(8)
Lead Soldering Temperature (Wave Soldering or IR, 10 Seconds)
8.0
A
140
mJ
25
V
6.0
V
6.0
V
700
V
Notes:
5. All voltage values, except differential voltages, are given with respect to the network ground terminal.
6. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
7. Non-repetitive rating: pulse width is limited by the maximum junction temperature.
8. L = 51 mH, starting TJ = 25°C.
9. Internally limited by Over-Temperature Protection(OTP). Refer to TOTP.
Thermal Resistance Table
Symbol
θJA
ψJT
Parameter
Junction-to-Air Thermal Resistance
Junction-to-Package Thermal Resistance
(10)
Value
Unit
86
C/W
20
C/W
Value
Unit
Note:
10. Measured on the package top surface.
ESD Capability
Symbol
Parameter
Human Body Model, JESD22-A114
(11)
ESD
(11)
Charged Device Model, JESD22-C101
All pins excluding HV pin
7
All pins including HV pin
3
All pins excluding HV pin
2
All pins including HV pin
2
kV
Note:
11. Meets JEDEC standards JESD 22-A114 and JESD 22-C101.
© 2014 Fairchild Semiconductor Corporation
GF001H • Rev. 1.1
www.fairchildsemi.com
4
GF001H — Green-Mode Fairchild Power Switch (FPS™)
Absolute Maximum Ratings
VDD=15 V, and TA=25°C unless otherwise specified.
Symbol
Parameter
SenseFET Section
BVDSS
IDSS
Condition
Min.
Typ.
Max.
Unit
(12)
Drain-Source Breakdown Voltage
VDS = 700 V, VGS = 0 V
Zero-Gate-Voltage Drain Current
(12)
700
V
VDS = 700 V, VGS = 0 V
50
VDS = 560 V, VGS = 0 V,
TC = 125°C
200
μA
Drain-Source On-State Resistance
VGS = 10 V, ID = 0.5 A
6.0
7.2
Ω
CISS
Input Capacitance
VGS = 0V , VDS = 25 V,
f = 1 MHz
550
715
pF
COSS
Output Capacitance
VGS = 0 V, VDS = 25 V,
f = 1 MHz
38
50
pF
CRSS
Reverse Transfer Capacitance
VGS = 0 V, VDS = 25 V,
f = 1 MHz
17
26
pF
td(on)
Turn-On Delay
VDS = 350 V, ID = 1.0 A
20
50
ns
Rise Time
VDS = 350 V, ID = 1.0 A
15
40
ns
Turn-Off Delay
VDS = 350 V, ID = 1.0 A
55
120
ns
Fall Time
VDS = 350 V, ID = 1.0 A
25
60
ns
RDS(ON)
tr
td(off)
tf
Control Section
VDD Section
VDD-ON
UVLO Start Threshold Voltage
11
12
13
V
VDD-OFF1
UVLO Stop Threshold Voltage
5
6
7
V
VDD-OFF2
IDD-OLP Enable Threshold Voltage
8
9
10
V
VDD-OLP
VDD Voltage Threshold for HV Startup
Turn-On at Protection Mode
5
6
7
V
IDD-ST
Startup Supply Current
VDD-ON – 0.16 V
30
µA
IDD-OP1
Operating Supply Current with Normal
Switching Operation
VDD=15 V, VFB=3 V
3.8
mA
IDD-OP2
Operating Supply Current without
Switching Operation
VDD=15 V, VFB=1 V
1.8
mA
IDD-OLP
Internal Sinking Current
VDD-OLP + 0.1 V
VDD-OVP
tD-VDDOVP
30
60
90
µA
VDD Over-Voltage Protection
23
24
25
V
VDD Over-Voltage Protection
Debounce Time
40
105
170
µs
5.0
mA
HV Section
IHV
Supply Current Drawn from HV Pin
HV=120 VDC,
VDD=0 V with 10 µF
1.5
VHV
Minimum HV Voltage for VDD being
charged to VDD-ON
RHV=0 Ω,
TA=-40 °C to 105 °C
30
IHV-LC
Leakage Current after Startup
HV=700 V,
VDD=VDD-OFF1+1 V
VDC-ON
Brown-in Threshold Level (VDC)
VDC-OFF
Brownout Threshold Level (VDC)
tUVP
DC Voltage Applied to
HV Pin Through 200 kΩ
Resistor
Brownout Protection Time
V
10
µA
104
114
124
V
89
99
109
V
0.8
1.2
1.6
s
Continued on the following page…
© 2014 Fairchild Semiconductor Corporation
GF001H • Rev. 1.1
www.fairchildsemi.com
5
GF001H — Green-Mode Fairchild Power Switch (FPS™)
Electrical Characteristics
VDD=15 V, TA=25°C unless otherwise specified.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
94
100
106
kHz
Oscillator Section
fOSC
fM
fOSC-G
Frequency in Nominal Mode
Center Frequency
Frequency Modulation
±6
Green-Mode Frequency
20
23
kHz
26
kHz
fDV
Frequency Variation vs. VDD Deviation
VDD=11 V to 22 V
5
%
fDT
Frequency Variation vs. Temperature
(12)
Deviation
TA=-40 °C to 105 °C
5
%
Feedback Input Section
AV
Internal Voltage Dividing Factor of FB Pin
ZFB
Pull-Up Impedance of FB Pin
(12)
FB Pin Open
1/4.5
1/4.0
1/3.5
V/V
15
21
27
kΩ
VFB-OPEN
FB Pin Pull-Up Voltage
5.2
5.4
5.6
V
VFB-OLP
FB Voltage Threshold to Trigger Open-Loop
Protection
4.3
4.6
4.9
V
tD-OLP
Delay of FB Pin Open-Loop Protection
46
56
66
ms
VFB-N
FB Voltage Threshold to Exit Green Mode
VFB is Rising
2.4
2.6
2.8
V
VFB-G
FB Voltage Threshold to Enter Green Mode
VFB is Falling
VFB-ZDC
FB Voltage Threshold to Enter Zero-Duty
State
VFB is Falling
VFB-ZDCR
FB Voltage Threshold to Exit Zero-Duty State VFB is Rising
VFB-N
-0.2
1.1
1.2
V
1.3
VFB-ZDC
+0.1
V
V
IPK Pin Section
VIPK-OPEN
IPK Pin Open Voltage
3.0
VIPK-H
Internal Upper Clamping Voltage of IPK
(12)
Pin
VIPK-L
Internal Lower Clamping Voltage of IPK
(12)
Pin
4.0
V
3
V
V
1.5
Internal Current Source of IPK Pin
TA=-40 °C to 105 °C,
VIPK=2.25 V
ILMT-H
Flat Threshold Level of Current Limit for the
Highest IPK Level
ILMT-L
Flat Threshold Level of Current Limit for the
Lowest IPK Level
IPK
3.5
45
50
55
µA
VIPK=3 V
0.90
1.00
1.10
A
VIPK=1.5 V
0.45
0.50
0.55
A
100
200
ns
210
260
ns
(13)
Current-Sense Section
tPD
tLEB
tSS
(14)
Current Limit Turn-Off Delay
Leading-Edge Blanking Time
Soft-Start Time
GATE Section
DCYMAX
(14)
160
(12)
5
ms
(13)
Maximum Duty Cycle
70
%
140
°C
Over Temperature Protection Section (OTP)
TOTP
Junction Temperature to Trigger OTP
(12)
Notes:
12. Guaranteed by design; not 100% tested in production.
13. Pulse test: pulse width ≤ 300 µs, duty ≤ 2%.
14. These parameters, although guaranteed, are tested in wafer-sort process.
© 2014 Fairchild Semiconductor Corporation
GF001H • Rev. 1.1
www.fairchildsemi.com
6
GF001H — Green-Mode Fairchild Power Switch (FPS™)
Electrical Characteristics (Continued)
Figure 5. VDD-ON vs. Temperature
Figure 6. VDD-OFF1 vs. Temperature
Figure 7. VDD-OFF2 vs. Temperature
Figure 8. VDD-OVP vs. Temperature
Figure 9. VDD-OLP vs. Temperature
Figure 10. IDD-OP1 vs. Temperature
Figure 11. VDC-ON vs. Temperature
Figure 12. VDC-OFF vs. Temperature
© 2014 Fairchild Semiconductor Corporation
GF001H • Rev. 1.1
www.fairchildsemi.com
7
GF001H — Green-Mode Fairchild Power Switch (FPS™)
Typical Characteristics
Figure 13. VFB-OPEN vs. Temperature
Figure 15.
ZFB vs. Temperature
Figure 17.
fOSC vs. Temperature
© 2014 Fairchild Semiconductor Corporation
GF001H • Rev. 1.1
Figure 14. VFB-OLP vs. Temperature
Figure 16.
IPK vs. Temperature
Figure 18. fOSC-G vs. Temperature
www.fairchildsemi.com
8
GF001H — Green-Mode Fairchild Power Switch (FPS™)
Typical Characteristics (Continued)
Startup Operation
PWM Control
The HV pin is typically connected to the DC link input
through one resistor (RHV), as shown in Figure 19. When
the DC input voltage is applied, the VDD hold-up
capacitor is charged by the line voltage through the
resistor. After VDD voltage reaches the turn-on threshold
voltage (VDD-ON), the startup circuit charging the VDD
capacitor is switched off and VDD is supplied by the
auxiliary winding of the transformer. Once the GF001H
starts, it continues operation until VDD drops below 6 V
(VDD-OFF1). The IC startup time with a given DC input
voltage is:
The GF001H employs current-mode control, as shown
in Figure 20. An opto-coupler (such as the H11A817A)
and shunt regulator (such as the KA431) are typically
used to implement the feedback network. Comparing
the feedback voltage with the voltage across the Rsense
resistor makes it possible to control the switching duty
cycle. A synchronized positive slope is added to the
SenseFET current information to guarantee stable
current-mode control over a wide range of input voltage.
The built-in slope compensation stabilizes the current
loop and prevents sub-harmonic oscillation.
t
C
ln
C
C-
6
(1)
-
7
8
5.4V
Drain
VO
ZF
3
FB
OSC
5 HV
GF001H
-
VDD
Good
12/6V
EMI
Filter
PWM
3R
Comparator
2
DC
Link
+
RHV
VDD
Gate
Driver
NA
CDD
KA431
R
+
RLS
RSENSE
Line Sensing
Primary-Side
+
SecondarySide
Slope
Compensation
AC Line
Figure 19. Startup Circuit
Figure 20. Current Mode Control
Brown-in/out Function
Soft-Start
The HV pin can detect the DC link voltage using a
switched voltage divider that consists of external resistor
(RHV) and internal resistor (RLS), as shown in Figure 19.
The internal DC input voltage sensing circuit detects the
input voltage using a sampling circuit and peakdetection circuit. Since the voltage divider causes power
consumption when it is switched on, the switching is
driven by a signal with a very narrow pulse width to
minimize power loss. The sampling frequency is
adaptively changed according to the load condition to
minimize power consumption in light-load condition.
The GF001H has an internal soft-start circuit that
progressively increases the pulse-by-pulse current limit
level of MOSFET during startup to establish the correct
working conditions for transformers and capacitors, as
shown in Figure 21. The current limit levels have nine
steps, as shown in Figure 22. This prevents transformer
saturation and reduces stress on the secondary diode
during startup.
6
7
8
Drain
Based on the detected DC input voltage, brown-in and
brownout thresholds are determined. Since the internal
resistor (RLS) of the voltage divider is much smaller than
RHV, the thresholds are given:
OSC
3R
3
SS
Comparator
FB
R
VSS
Gate
Driver
(2)
5.4V
ZF
PWM
Comparator
+
VLMT
(3)
Current Limit
Comparator
+
Slope
Compensation
RSENSE
Figure 21. Soft-Start and Current-Limit Circuit
© 2014 Fairchild Semiconductor Corporation
GF001H • Rev. 1.1
www.fairchildsemi.com
9
GF001H — Green-Mode Fairchild Power Switch (FPS™)
Functional Description
0.86ILMT
0.59ILMT
0.45ILMT
0.66ILMT
0.73ILMT
The GF001H provides protection functions that include
Overload / Open-Loop Protection (OLP) and OverVoltage Protection (OVP). All the protections are
implemented as Auto-Restart Mode. Once the fault
condition is detected, switching is terminated and the
SenseFET remains off, this causes VDD to fall. When
VDD falls to 6 V, the protection is reset and HV startup
circuit charges VDD up to 12 V voltage, allowing restart.
0.80ILMT
0.52ILMT
0.64ms
1.28ms
1.92ms
2.56ms
3.22ms
3.86ms
4.50ms
5.12ms
Open-Loop / Overload Protection (OLP)
Because of the pulse-by-pulse current-limit capability,
the maximum peak current through the SenseFET is
limited and maximum input power is limited. If the output
consumes more than the limited maximum power, the
output voltage (VO) drops below the set voltage. The
current through the opto-coupler LED and the transistor
become virtually zero and FB voltage is pulled HIGH,
shown in Figure 25. If feedback voltage is above 4.6 V
for longer than 56 ms, OLP is triggered. This protection
is also triggered when the feedback loop is open due to
a soldering defect.
Figure 22. Current Limit Variation During Soft-Start
Adjustable Peak Current Limit
The peak current limit is programmable using a resistor
on the IPK pin. The internal current 50 µA source for the
IPK pin generates voltage drop across the resistor. The
voltage of the IPK pin determines the current-limit level.
Since the upper and lower clamping voltage of the IPK
pin are 3 V and 1.5 V, respectively; the suggested
resistor value is from 30 kΩ to 60 kΩ.
Green Mode
As output load condition is reduced, the switching loss
becomes the largest power loss factor. GF001H uses the
FB pin voltage to monitor output load condition. As output
load decreases, VFB decreases and switching frequency
declines, show in Figure 23. Once VFB falls to 2.4 V, the
switching frequency varies between 21.5 kHz and
24.5 kHz before Burst Mode operation. At Burst Mode
operation, random frequency fluctuation still functions.
VFB
5.4V
VFB-OLP (4.6V)
OLP Shutdown Delay
56ms
As VFB falls below VFB-ZDC, the GF001H enters Burst
Mode, where PWM switching is disabled. The output
voltage starts to drop, causing the feedback voltage to
rise. Once VFB rises above VFB-ZDCR, switching resumes.
Burst Mode alternately enables and disables switching,
thereby reducing switching loss to reduce power
consumption, shown in Figure 24.
PWM Frequency
Figure 25. OLP Operation
VDD Over-Voltage Protection (OVP)
If the secondary-side feedback circuit malfunctions or a
solder defect causes an opening in the feedback path,
the current through the opto-coupler transistor becomes
virtually zero. Feedback voltage climbs in a similar
manner to the overload situation, forcing the preset
maximum current to be supplied to the SMPS until the
overload protection triggers. Since more energy than
required is provided to the output, the output voltage
may exceed the rated voltage before the overload
protection triggers, resulting in the breakdown of the
devices in the secondary side. To prevent this situation,
an OVP circuit is employed. Since VDD voltage is
proportional to the output voltage by the transformer
coupling, the over-voltage of output is indirectly detected
using VDD voltage. The OVP is triggered when VDD
voltage reaches 24 V. Debounce time (typically 105 µs) is
applied to prevent false triggering by switching noise.
Random Frequency
Modulation Range
106kHz
94kHz
24.5kHz
21.5kHz
VFB
VFB-ZDC VFB-ZDCR
Figure 23.
VFB-G VFB-N
PWM Frequency
VO
Two-Level UVLO
Since all the protections of the GF001H are auto-restart,
the power supply repeats shutdown and restart until the
fault condition is removed. GF001H has two-level
UVLO, which is enabled when protection is triggered, to
delay the re-startup by slowing down the discharge of
VDD. This effectively reduces the input power of the
power supply during the fault condition, minimizing the
voltage/current stress of the switching devices. Figure
26 shows the normal UVLO operation and two-step
UVLO operation. When VDD drops to 6 V without
triggering the protection, PWM stops switching and VDD
VFB
VFB.ZDCR
VFB.ZDC
IDrain
Switching
Disabled
Switching
Disabled
Figure 24. Burst-Mode Operation
© 2014 Fairchild Semiconductor Corporation
GF001H • Rev. 1.1
OLP Triggered
www.fairchildsemi.com
10
GF001H — Green-Mode Fairchild Power Switch (FPS™)
Protections
ILMT
0.93ILMT
Line is connected
VDD-ON
12V
VDD-OFF2
9V
VDD-OLP
6V
Normal UVLO without
protection (ex. aux winding
Disconnected)
VDS
IDD-OP1
IDD-OLP
IDD-ST
Line is connected
VDD-ON
12V
VDD-OFF2
9V
VDD-OLP
6V
Protection triggers
VDS
IDD-OP1
IDD-OLP
IDD-ST
Figure 26. Two-Level UVLO
© 2014 Fairchild Semiconductor Corporation
GF001H • Rev. 1.1
www.fairchildsemi.com
11
GF001H — Green-Mode Fairchild Power Switch (FPS™)
is charged up by the HV startup circuit. Meanwhile,
when the protection is triggered, GF001H has a different
VDD discharge profile. Once the protection is triggered,
the IC stops switching and VDD drops. When VDD drops
to 9 V, the operating current becomes very small and
VDD is slowly discharged. When VDD is naturally
discharged down to 6 V, the protection is reset and VDD
is charged up by the HV startup circuit. Once V DD
reaches 12 V, the IC resumes switching operation.
[
0.400 10.160
0.355 9.017
8
]
5
[
0.280 7.112
0.240 6.096
1
HALF LEAD STYLE 4X
0.031 [0.786] MIN
MAX 0.210 [5.334]
]
4
FULL LEAD STYLE 4X
0.010 [0.252] MIN
0.195 4.965
0.115 2.933
[
]
[
0.325 8.263
0.300 7.628
]
SEATING PLANE
[
0.150 3.811
0.115 2.922
]
C
MIN 0.015 [0.381]
0.100 [2.540]
(0.031 [0.786]) 4X
[
]
0.10
C
0.022 0.562
0.014 0.358
0.300 [7.618]
0.430 [10.922]
MAX
[
0.070 1.778
0.045 1.143
FOR 1/2 LEAD STYLE
] 4X
8X FOR FULL LEAD STYLE
NOTES:
A) THIS PACKAGE CONFORMS TO JEDEC MS-001 VARIATION BA WHICH DEFINES
2 VERSIONS OF THE PACKAGE TERMINAL STYLE WHICH ARE SHOWN HERE.
B) CONTROLING DIMS ARE IN INCHES
C) DIMENSION S ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSION S AND TOLERANCES PER ASME Y14.5M-2009
E) DRAWING FILENAME AND REVSION: MKT-N08MREV2.
0.015 [0.389] GAGE PLANE
PIN 1 INDICATOR
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