DATA SHEET
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High-Speed 10 MBit/s
Logic Gate Optocouplers
PDIP8 6.6x3.81, 2.54P
CASE 646BW
8
Single-Channel: 6N137,
HCPL2601, HCPL2611
Dual-Channel: HCPL2630,
HCPL2631
1
8
1
Description
The 6N137, HCPL2601, HCPL2611 single−channel and
HCPL2630, HCPL2631 dual−channel optocouplers consist of a
850 nm AlGaAS LED, optically coupled to a very high speed
integrated photo−detector logic gate with a strobable output. This
output features an open collector, thereby permitting wired OR
outputs. The coupled parameters are guaranteed over the temperature
range of −40°C to +85°C. A maximum input signal of 5 mA will
provide a minimum output sink current of 13 mA (fan out of 8).
An internal noise shield provides superior common mode rejection
of typically 10 kV/s. The HCPL2601 and HCPL2631 has a minimum
CMR of 5 kV/s. The HCPL2611 has a minimum CMR of 10 kV/s.
Very High Speed – 10 MBit/s
Superior CMR – 10 kV/s
Double working voltage − 480 V
Fan−out of 8 Over −40°C to +85°C
Logic Gate Output
Strobable Output
Wired OR−open Collector
U.L. Recognized (File # E90700)
PDIP8 GW
CASE 709AC
8
1
MARKING DIAGRAM
ON
2601
VXXYYT1
2601
V
Features
•
•
•
•
•
•
•
•
PDIP8 9.655x6.6, 2.54P
CASE 646CQ
XX
YY
T1
= Device Number
= VDE mark (Note: Only Appears on
Parts Ordered with VDE Option – See
Order Entry Table)
= Two−Digit Year Code, e.g., ‘03’
= Two−Digit Work Week, Ranging from
‘01’ to ‘53’
= Assembly Package Code
ORDERING INFORMATION
See detailed ordering and shipping information on page 10 of
this data sheet.
Applications
•
•
•
•
•
•
•
Ground Loop Elimination
LSTTL to TTL, LSTTL or 5−volt CMOS
Line Receiver, Data Transmission
Data Multiplexing
Switching Power Supplies
Pulse Transformer Replacement
Computer−peripheral Interface
© Semiconductor Components Industries, LLC, 2005
August, 2021 − Rev. 3
1
Publication Order Number:
HCPL2631/D
Single−Channel: 6N137, HCPL2601, HCPL2611 Dual−Channel: HCPL2630, HCPL2631
SCHEMATICS
8 VCC
N/C 1
+ 1
8 VCC
VF1
+ 2
7 VE
_ 2
6 VO
_
7 V01
VF
_
3
3
6 V02
VF2
N/C 4
+ 4
5 GND
6N137, HCPL2601,
HCPL2611
5 GND
HCPL2630,
HCPL2631
A 0.1 F bypass capacitor must be connected between pins 8 and 5 (Note 1).
Figure 1. Schematics
TRUTH TABLE (Positive Logic)
Input
Enable
Output
H
H
L
L
H
H
H
L
H
L
L
H
H
NC
L
L
NC
H
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2
Single−Channel: 6N137, HCPL2601, HCPL2611 Dual−Channel: HCPL2630, HCPL2631
ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Symbol
Value
Unit
TSTG
Storage Temperature
Parameter
−55 to +125
°C
TOPR
Operating Temperature
−40 to +85
°C
TSOL
Lead Solder Temperature (for Wave Soldering Only)*
260 for 10 s
°C
50
mA
EMITTER
IF
DC/Average Forward Input Current
VE
Enable Input Voltage Not to Exceed VCC by More than
500 mV
VR
Reverse Input Voltage
Each Channel
5.0
V
PI
Power Dissipation
Single Channel
100
mW
Dual Channel (Each Channel)
45
Single Channel
Dual Channel (Each Channel)
30
Single Channel
5.5
V
DETECTOR
VCC
(1 Minute Max)
Supply Voltage
IO
Output Current
7.0
V
Single Channel
25
mA
Dual Channel (Each Channel)
50
mA
VO
Output Voltage
Each Channel
7.0
V
PO
Collector Output Power Dissipation
Single Channel
85
mW
Dual Channel (Each Channel)
60
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
*For peak soldering reflow, please refer to the Reflow Profile on page 9.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
250
A
IFL
Input Current, Low Level
0
IFH
Input Current, High Level
*6.3
15
mA
VCC
Supply Voltage, Output
4.5
5.5
V
VEL
Enable Voltage, Low Level
0
0.8
V
VEH
Enable Voltage, High Level
2.0
VCC
V
TA
Low Level Supply Current
−40
+85
°C
N
Fan Out (TTL Load)
−
8
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
*6.3 mA is a guard banded value which allows for at least 20% CTR degradation. Initial input current threshold value is 5.0 mA or less.
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3
Single−Channel: 6N137, HCPL2601, HCPL2611 Dual−Channel: HCPL2630, HCPL2631
ELECTRICAL CHARACTERISTICS (TA = 0°C to 70°C unless otherwise specified)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
−
−
1.8
V
−
1.4
1.75
5.0
−
−
V
INDIVIDUAL COMPONENT CHARACTERISTICS
EMITTER
VF
Input Forward Voltage
IF = 10 mA
TA = 25°C
BVR
Input Reverse Breakdown
Voltage
IR = 10 A
CIN
Input Capacitance
VF = 0, f = 1 MHz
−
60
−
pF
Input Diode Temperature
Coefficient
IF = 10 mA
−
−1.4
−
mV/°C
ICCH
High Level Supply Current
VCC = 5.5 V, IF = 0 mA,
VE = 0.5 V
Single Channel
−
7
10
mA
Dual Channel
−
10
15
ICCL
Low Level Supply Current
Single Channel
VCC = 5.5 V, IF = 10 mA
−
9
13
Dual Channel
VE = 0.5 V
−
14
21
VF / TA
DETECTOR
mA
IEL
Low Level Enable Current
VCC = 5.5 V, VE = 0.5 V
−
−0.8
−1.6
mA
IEH
High Level Enable Current
VCC = 5.5 V, VE = 2.0 V
−
−0.6
−1.6
mA
VEH
High Level Enable Voltage
VCC = 5.5 V, IF = 10 mA
2.0
−
−
V
VEL
Low Level Enable Voltage
VCC = 5.5 V, IF = 10 mA (Note 3)
−
−
0.8
V
20
45
75
ns
−
−
100
SWITCHING CHARACTERISTICS (TA = −40°C to +85°C, VCC = 5 V, IF = 7.5 mA unless otherwise specified)
TPLH
TPHL
Propagation Delay Time to
Output HIGH Level
RL = 350 , CL = 15 pF
(Note 4) (Figure 13)
Propagation Delay Time to
Output LOW Level
TA = 25°C (Note 5)
25
45
75
RL = 350 , CL = 15 pF (Figure 13)
−
−
100
RL = 350 , CL = 15 pF (Figure 13)
−
3
35
ns
|TPHL–TPLH| Pulse Width Distortion
TA = 25°C
ns
tr
Output Rise Time (10–90%)
RL = 350 , CL = 15 pF (Note 6) (Figure 13)
−
50
−
ns
tf
Output Rise Time (90–10%)
RL = 350 , CL = 15 pF (Note 7) (Figure 13)
−
12
−
ns
tELH
Enable Propagation Delay
Time to Output HIGH Level
IF = 7.5 mA, VEH = 3.5 V, RL = 350 , CL = 15 pF
(Note 8) (Figure 14)
−
20
−
ns
tEHL
Enable Propagation Delay
Time to Output LOW Level
IF = 7.5 mA, VEH = 3.5 V, RL = 350 , CL = 15pF
(Note 9) (Figure 14)
−
20
−
ns
|CMH|
Common Mode Transient
Immunity (at Output HIGH
Level)
TA = 25°C, |VCM| = 50 V
(Peak), IF = 0 mA,
VOH (Min.) = 2.0 V,
RL = 350 (Note 10)
(Figure 15)
6N137, HCPL2630
−
10,000
−
V/s
5000
10,000
−
|VCM| = 400 V
HCPL2611
10,000
15,000
−
RL = 350 , IF = 7.5 mA,
VOL (Max.) = 0.8 V,
TA = 25°C (Note 11)
(Figure 15)
6N137, HCPL2630
−
10,000
−
5000
10,000
−
|VCM| = 400 V
HCPL2611
10,000
15,000
−
|CML|
Common Mode Transient
Immunity (at Output LOW
Level)
HCPL2601, HCPL2631
HCPL2601, HCPL2631
V/s
TRANSFER CHARACTERISTICS (TA = −40°C to +85°C unless otherwise specified)
IOH
HIGH Level Output Current
VCC = 5.5 V, VO = 5.5 V, IF = 250 A, VE = 2.0V
(Note 2)
−
−
100
A
VOL
LOW Level Output Current
VCC = 5.5 V, IF = 5 mA, VE = 2.0 V, ICL = 13 mA
(Note 2)
−
.35
0.6
V
IFT
Input Threshold Current
VCC = 5.5 V, VO = 0.6 V, VE = 2.0 V, IOL = 13 mA
−
3
5
mA
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Single−Channel: 6N137, HCPL2601, HCPL2611 Dual−Channel: HCPL2630, HCPL2631
ELECTRICAL CHARACTERISTICS (TA = 0°C to 70°C unless otherwise specified) (continued)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
ISOLATION CHARACTERISTICS (TA = −40°C to +85°C unless otherwise specified)
II−O
Input−Output Insulation
Leakage Current
Relative Humidity = 45%, TA = 25°C, t = 5 s,
VI−O = 3000 VDC (Note 12)
−
−
1.0*
A
VISO
Withstand Insulation Test
Voltage
RH < 50%, TA = 25°C, II−O ≤ 2 A, t = 1 min.
(Note 12)
2500
−
−
VRMS
RI−O
Resistance (Input to Output)
VI−O = 500 V (Note 12)
−
1012
−
CI−O
Capacitance (Input to Output)
f = 1 MHz (Note 12)
−
0.6
−
pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
*All Typicals at VCC = 5 V, TA = 25°C
1. The VCC supply to each optoisolator must be bypassed by a 0.1 F capacitor or larger. This can be either a ceramic or solid tantalum capacitor
with good high frequency characteristic and should be connected as close as possible to the package VCC and GND pins of each device.
2. Each channel.
3. Enable Input – No pull up resistor required as the device has an internal pull up resistor.
4. tPLH – Propagation delay is measured from the 3.75 mA level on the HIGH to LOW transition of the input current pulse to the 1.5 V level on
the LOW to HIGH transition of the output voltage pulse.
5. tPHL – Propagation delay is measured from the 3.75 mA level on the LOW to HIGH transition of the input current pulse to the 1.5 V level on
the HIGH to LOW transition of the output voltage pulse.
6. tr – Rise time is measured from the 10% to the 90% levels on the LOW to HIGH transition of the output pulse.
7. tf – Fall time is measured from the 90% to the 10% levels on the HIGH to LOW transition of the output pulse.
8. tELH – Enable input propagation delay is measured from the 1.5 V level on the HIGH to LOW transition of the input voltage pulse to the 1.5 V
level on the LOW to HIGH transition of the output voltage pulse.
9. tEHL – Enable input propagation delay is measured from the 1.5 V level on the LOW to HIGH transition of the input voltage pulse to the 1.5 V
level on the HIGH to LOW transition of the output voltage pulse.
10. CMH – The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the HIGH state (i.e., VOUT > 2.0 V).
Measured in volts per microsecond (V/s).
11. CML – The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the LOW output state (i.e.,
VOUT < 0.8 V). Measured in volts per microsecond (V/s).
12. Device considered a two−terminal device: Pins 1, 2, 3 and 4 shorted together, and Pins 5, 6, 7 and 8 shorted together.
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Single−Channel: 6N137, HCPL2601, HCPL2611 Dual−Channel: HCPL2630, HCPL2631
0.8
Conditions:
IF = 5 mA
VE = 2 V
VCC = 5.5 V
0.7
0.6
IF, FORWARD CURRENT (mA)
VOL, LOW LEVEL OUTPUT VOLTAGE (V)
TYPICAL PERFORMANCE CURVES
IOL = 12.8 mA
0.5
IOL = 16 mA
0.4
0.3
IOL = 6.4 mA
IOL = 9.6 mA
0.2
0.1
0.0
−40
30
16
10
1
0.1
0.01
0.001
−20
0
20
40
60
80
0.9
1.0
1.1
IOL, LOW LEVEL OUTPUT CURRENT (mA)
TP, PROPAGATION DELAY (ns)
100
RL = 4 k (TPLH)
80
RL = 1 k (TPLH)
40
20
0
RL = 1 k
RL = 4 k (TPHL)
RL = 350 k
RL = 350 (tPLH)
5
7
9
11
13
15
50
45
1.6
IF = 10 mA
40
IF = 5 mA
35
30
Conditions:
VCC = 5 V
VE = 2 V
VOL = 0.6 V
25
20
−40
IF, FORWARD CURRENT (mA)
−20
0
20
40
60
80
TA, AMBIENT TEMPERATURE (°C)
Figure 5. Low Level Output vs.
Ambient Temperature
6
4
Conditions:
VCC = 5.0 V
VOL = 0.6 V
3
VO, OUTPUT VOLTAGE (V)
IFT, INPUT THRESHOLD CURRENT (mA)
1.5
IF = 15 mA
Figure 4. Switching Time vs. Forward Current
RL = 350
RL = 1 k
2
1
1.4
Figure 3. Input Diode Forward Voltage vs.
Forward Current
VCC = 5 V
60
1.3
VF, FORWARD VOLTAGE (V)
TA, AMBIENT TEMPERATURE (°C)
Figure 2. Low Level Output Voltage vs.
Ambient Temperature
120
1.2
RL = 4 k
−40
−20
0
20
40
60
5
4
3
2
RL = 4 k
RL = 350
1
0
80
RL = 1 k
TA, AMBIENT TEMPERATURE (°C)
0
1
2
3
4
5
6
IF, FORWARD CURRENT (mA)
Figure 6. Input Threshold Current vs.
Ambient Temperature
Figure 7. Output Voltage vs. Input Forward Current
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Single−Channel: 6N137, HCPL2601, HCPL2611 Dual−Channel: HCPL2630, HCPL2631
80
60
40
600
RL = 4 k
Conditions:
IF = 7.5 mA
VCC = 5 V
20
RL = 1 k
0
−60
Tr / Tf, RISE AND FALL TIME (ns)
PWD, PULSE WIDTH DISTORTION (ns)
TYPICAL PERFORMANCE CURVES (Continued)
RL = 350
−40
−20
0
20
40
60
80
RL = 4 k (tr)
500
400
300
Conditions:
IF = 7.5 mA
VCC = 5 V
200
0
−60
−40
TP, PROPAGATION DELAY (ns)
TE, ENABLE PROPAGATION DELAY (ns)
20
40
60
80
100
TA, TEMPERATURE (°C)
RL = 4 k (TELH)
80
RL = 350
RL = 1 k
RL = 4 k
]
(TEHL)
RL = 1 k (TELH)
RL = 350 (TELH)
20
−40
−20
0
20
40
60
80
TA, TEMPERATURE (°C)
40
20
40
60
80
RL = 350 TPLH
−40
−20
0
20
40
60
TA, TEMPERATURE (°C)
80
Figure 11. Switching Time vs. Temperature
5
0
TPHL
RL = 1 k TPLH
10
−20
]
60
Conditions:
VCC = 5.5 V
VO = 5.5 V
VE = 2.0 V
IF = 250 A
−40
RL = 1 k
RL = 4 k
RL = 350
80
20
15
RL = 4 k TPLH
100
20
−60
100
Figure 10. Enable Propagation Delay vs. Temperature
IOH, HIGH LEVEL OUTPUT CURRENT (A)
0
120
100
0
−60
−20
Figure 9. Rise and Fall Time vs. Temperature
120
0
−60
(tf)
RL = 350 (tr)
TA, TEMPERATURE (°C)
40
]
RL = 1 k (tr)
100
100
Figure 8. Pulse Width Distortion vs. Temperature
60
RL = 1 k
RL = 4 k
RL = 350
100
TA, TEMPERATURE (°C)
Figure 12. High Level Output Current vs. Temperature
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100
Single−Channel: 6N137, HCPL2601, HCPL2611 Dual−Channel: HCPL2630, HCPL2631
TEST CIRCUITS
Pulse
Generator
tr = 5 ns
ZO = 50
+5 V
IF = 7.5 mA
VCC
1
2
Input
Monitor
(IF )
Input
(IF )
8
.1 F
bypass
7
3
RL
Output
(VO )
6
4
GND
t PHL
t PLH
Output
(VO)
CL
47
IF = 3.75 mA
1.5 V
90%
Output
(VO)
10%
5
tf
tr
Figure 13. Test Circuit and Waveforms for tPLH, tPHL, tr and tf
Pulse
Generator
tr = 5 ns
ZO = 50
Input
Monitor
(VE)
+5 V
1
7.5 mA
VCC
8
7
2
.1 F
bypass
Output
(VO)
RL
CL
4
GND
1.5 V
t EHL
Output
(VO )
6
3
3.0 V
Input
(VE )
5
Figure 14. Test Circuit tEHL and tELH
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8
t ELH
1.5 V
Single−Channel: 6N137, HCPL2601, HCPL2611 Dual−Channel: HCPL2630, HCPL2631
TEST CIRCUITS (Continued)
VCC
1
A
IF
+5 V
8
2
7
3
6
.1 F
bypass
350
B
VFF
4
GND
Output
(VO)
5
VCM
Pulse Gen
Peak
VCM
0V
5V
CMH
Switching Pos. (A), IF = 0
VO
VO (Min)
VO (Max)
Switching Pos. (B), IF = 7.5 mA
VO
0.5 V
CML
Figure 15. Test Circuit Common Mode Transient Immunity
REFLOW PROFILE
Temperature (°C)
300
215C, 10–30 s
250
225C peak
200
150
Time above 183C, 60–150 s
100
50
0
Ramp up = 3C/s
0
0.5
1
1.5
2
2.5
3
Time (Minute)
3.5
4
4.5
• Peak reflow temperature: 225C (package surface temperature)
• Time of temperature higher than 183C for 60–150 seconds
• One time soldering reflow is recommended
Figure 16. Reflow Profile
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Single−Channel: 6N137, HCPL2601, HCPL2611 Dual−Channel: HCPL2630, HCPL2631
ORDERING INFORMATION
Option
Example Part Number
Description†
S
6N137S
PDIP8 GW, CASE 709AC
Surface Mount Lead Bend
SD
6N137SD
PDIP8 GW, CASE 709AC
Surface Mount; Tape and Reel
W
6N137W
PDIP8 6.6x3.81, 2.54P, CASE 646BW
0.4” Lead Spacing
V
6N137V
PDIP8 9.655x6.6, 2.54P, CASE 646CQ
VDE0884
WV
6N137WV
PDIP8 6.6x3.81, 2.54P, CASE 646BW
VDE0884; 0.4” Lead Spacing
SV
6N137SV
PDIP8 GW, CASE 709AC
VDE0884; Surface Mount
SDV
6N137SDV
PDIP8 GW, CASE 709AC
VDE0884; Surface Mount; Tape and Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP8 6.6x3.81, 2.54P
CASE 646BW
ISSUE O
DOCUMENT NUMBER:
DESCRIPTION:
98AON13445G
PDIP8 6.6X3.81, 2.54P
DATE 31 JUL 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP8 9.655x6.6, 2.54P
CASE 646CQ
ISSUE O
DOCUMENT NUMBER:
DESCRIPTION:
98AON13446G
PDIP8 9.655X6.6, 2.54P
DATE 18 SEP 2017
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP8 GW
CASE 709AC
ISSUE O
DOCUMENT NUMBER:
DESCRIPTION:
98AON13447G
PDIP8 GW
DATE 31 JUL 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
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