HUF75229P3
Data Sheet
December 2001
44A, 50V, 0.022 Ohm, N-Channel UltraFET
Power MOSFET
This N-Channel power MOSFET is
manufactured using the innovative
UltraFET® process. This advanced
process technology achieves the
lowest possible on-resistance per silicon area, resulting in
outstanding performance. This device is capable of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, lowvoltage bus switches, and power management in portable
and battery-operated products.
Features
• 44A, 50V
• Low On-Resistance, rDS(ON) = 0.022Ω
• Temperature Compensating PSPICE® Model
• Thermal Impedance SPICE Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
Ordering Information
PART NUMBER
HUF75229P3
PACKAGE
TO-220AB
BRAND
G
75229P
NOTE: When ordering use the entire part number.
S
Packaging
JEDEC TO-220AB
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Automotive HUFA series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUF75229P3 Rev. B
HUF75229P3
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
50
V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
50
V
±20
V
Drain Current
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
44
Figure 5
A
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Figure 6, 14, 15
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
0.6
W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
-55 to 175
oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V (Figure 11)
50
-
-
V
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 10)
2
-
4
V
VDS = 45V, VGS = 0V
-
-
1
µA
VDS = 40V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = ±20V
-
-
±100
nA
0.017
0.020
0.022
Ω
-
-
105
ns
-
12
-
ns
-
58
-
ns
td(OFF)
-
33
-
ns
tf
-
33
-
ns
tOFF
-
-
100
ns
-
60
75
nC
Zero Gate Voltage Drain Current
IDSS
Gate to Source Leakage Current
Drain to Source On Resistance
IGSS
rDS(ON)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
Fall Time
Turn-Off Time
Total Gate Charge
ID = 44A, VGS = 10V (Figure 9)
VDD = 30V, ID ≅ 44A,
RL = 0.68Ω, VGS = 10V,
RGS = 9.1Ω
(Figures 18, 19)
Qg(TOT)
VGS = 0V to 20V
Gate Charge at 10V
Qg(10)
VGS = 0V to 10V
Threshold Gate Charge
Qg(TH)
VGS = 0V to 2V
VDD = 30V,
ID ≅ 44A,
RL = 0.68Ω
Ig(REF) = 1.0mA
-
35
43
nC
-
2.0
2.5
nC
-
1060
-
pF
-
405
-
pF
(Figures 13, 16, 17)
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 12)
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
-
95
-
pF
Thermal Resistance Junction to Case
RθJC
(Figure 3)
-
-
1.66
oC/W
Thermal Resistance Junction to Ambient
RθJA
TO-220
-
-
62
oC/W
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
©2001 Fairchild Semiconductor Corporation
SYMBOL
MIN
TYP
MAX
UNITS
ISD = 44A
-
-
1.25
V
trr
ISD = 44A, dISD/dt = 100A/µs
-
-
72
ns
QRR
ISD = 44A, dISD/dt = 100A/µs
-
-
120
nC
VSD
TEST CONDITIONS
HUF75229P3 Rev. B
HUF75229P3
Typical Performance Curves
POWER DISSIPATION MULTIPLIER
1.2
50
ID, DRAIN CURRENT (A)
1.0
0.8
0.6
0.4
0.2
0
40
30
20
10
0
0
25
50
75
100
150
125
175
25
50
TC , CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
2
THERMAL IMPEDANCE
ZθJC, NORMALIZED
1
75
100
125
TC, CASE TEMPERATURE (oC)
150
175
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (s)
100
101
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
400
200
IDM, PEAK CURRENT (A)
100
ID, DRAIN CURRENT (A)
TC = 25oC FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
TJ = MAX RATED
TC = 25oC
100µs
10
1ms
10ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON) BVDSS MAX = 50V
1
1
10
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
©2001 Fairchild Semiconductor Corporation
200
I
100
= I25
175 - TC
150
VGS = 10V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
40
10-5
10-4
10-3
10-2
10-1
t, PULSE WIDTH (s)
100
101
FIGURE 5. PEAK CURRENT CAPABILITY
HUF75229P3 Rev. B
HUF75229P3
Typical Performance Curves
100
300
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
(Continued)
100
STARTING TJ = 25oC
STARTING TJ = 150oC
10
0.001
0.01
0.1
1
tAV, TIME IN AVALANCHE (ms)
VGS = 20V
VGS = 10V
VGS = 8V
VGS = 7V
80
VGS = 6V
60
40
VGS = 5V
20
0
10
PULSE DURATION = 250µs
TC = 25oC
0
1
2
3
4
VDS, DRAIN TO SOURCE VOLTAGE (V)
5
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
PULSE TEST
PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX
80
-55oC
175oC
60
40
20
25oC
0
0
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
2.5
100
ID, DRAIN CURRENT (A)
FIGURE 7. SATURATION CHARACTERISTICS
VDD = 15V
1.5
3.0
4.5
6.0
VGS, GATE TO SOURCE VOLTAGE (V)
1.5
1.0
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.2
1.2
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
VGS = VDS, ID = 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
2.0
0.5
-80
7.5
FIGURE 8. TRANSFER CHARACTERISTICS
1.0
0.8
0.6
0.4
-80
PULSE DURATION = 250µs, VGS = 10V, ID = 44A
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
ID = 250µA
1.1
1.0
0.9
0.8
-80
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
HUF75229P3 Rev. B
HUF75229P3
Typical Performance Curves
(Continued)
10
1500
VGS , GATE TO SOURCE VOLTAGE (V)
VGS = 0V, f = 1MHz
C, CAPACITANCE (pF)
1200
CISS
900
600
COSS
300
CRSS
8
6
4
0
10
20
30
40
VDS , DRAIN TO SOURCE VOLTAGE (V)
50
WAVEFORMS IN
DESCENDING ORDER:
ID = 44A
ID = 27A
ID = 11A
2
0
0
VDD = 30V
0
5
10
15
20
25
Qg, GATE CHARGE (nC)
30
35
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
©2001 Fairchild Semiconductor Corporation
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
HUF75229P3 Rev. B
HUF75229P3
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 20V
VGS
Qg(10)
+
VDD
VGS = 10V
VGS
DUT
VGS = 2V
IG(REF)
0
Qg(TH)
Ig(REF)
0
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORM
VDS
tON
tOFF
td(ON)
td(OFF)
tr
RL
VDS
tf
90%
90%
+
VGS
-
VDD
10%
0
10%
DUT
90%
RGS
VGS
VGS
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT
©2001 Fairchild Semiconductor Corporation
10%
50%
50%
PULSE WIDTH
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
HUF75229P3 Rev. B
HUF75229P3
PSPICE Electrical Model
SUBCKT HUF75229P3 2 1 3 ;
rev 6/19/97
CA 12 8 1.72e-9
CB 15 14 1.52e-9
CIN 6 8 9.61e-10
LDRAIN
DPLCAP
DRAIN
2
5
10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
11
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
LGATE
GATE
1
EVTEMP
RGATE +
18 22
9
20
21
EBREAK
17
18
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1e-3
RGATE 9 20 1.52
RLDRAIN 2 5 10
RLGATE 1 9 26.9
RLSOURCE 3 7 28.6
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 13.85e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
+
50
-
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
S1A
S1B
S2A
S2B
ESLC
-
EBREAK 11 7 17 18 58.13
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
LDRAIN 2 5 1e-9
LGATE 1 9 2.86e-9
LSOURCE 3 7 2.69e-9
DBREAK
+
RSLC2
5
51
IT 8 17 1
RLDRAIN
RSLC1
51
RLSOURCE
S1A
12
S2A
14
13
13
8
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
VBAT
5
8
EDS
-
-
IT
14
+
+
-
+
8
22
RVTHRES
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*135),3.5))}
.MODEL DBODYMOD D (IS = 7.50e-13 RS = 5.05e-3 TRS1 = 2.21e-3 TRS2 = 1.02e-6 CJO = 1.51e-9 TT = 4.05e-8 M = 0.5)
.MODEL DBREAKMOD D (RS = 2.14e- 1TRS1 = 9.62e- 4TRS2 = 1.23e-6)
.MODEL DPLCAPMOD D (CJO = 13.5e-1 0IS = 1e-3 0N = 10 M = 0.85)
.MODEL MMEDMOD NMOS (VTO = 3.25 KP = 2.50 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.52)
.MODEL MSTROMOD NMOS (VTO = 3.80 KP = 70.0 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.91 KP = 0.06 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 15.2 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.05e- 3TC2 = 1.94e-7)
.MODEL RDRAINMOD RES (TC1 = 8.04e-2 TC2 = 1.37e-4)
.MODEL RSLCMOD RES (TC1 = 4.83e-3 TC2 = 1.16e-6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC = -3.43e-3 TC2 = -1.63e-5)
.MODEL RVTEMPMOD RES (TC1 = -1.35e- 3TC2 = 1.16e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -7.90 VOFF= -4.90)
VON = -4.90 VOFF= -7.90)
VON = -0.50 VOFF= 2.50)
VON = 2.50 VOFF= -0.50)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2001 Fairchild Semiconductor Corporation
HUF75229P3 Rev. B
HUF75229P3
SPICE Thermal Model
7
JUNCTION
REV 16 June 97
HUF75229P3
CTHERM1 7 6 4.90e-7
CTHERM2 6 5 4.90e-4
CTHERM3 5 4 1.96e-3
CTHERM4 4 3 7.90e-3
CTHERM5 3 2 1.85e-1
CTHERM6 2 1 2.70
RTHERM1 7 6 1.10e-2
RTHERM2 6 5 3.30e-2
RTHERM3 5 4 1.64e-1
RTHERM4 4 3 7.90e-1
RTHERM5 3 2 3.60e-1
RTHERM6 2 1 1.60e-1
CTHERM1
RTHERM1
6
CTHERM2
RTHERM2
5
CTHERM3
RTHERM3
4
CTHERM4
RTHERM4
3
CTHERM5
RTHERM5
2
CTHERM6
RTHERM6
1
©2001 Fairchild Semiconductor Corporation
CASE
HUF75229P3 Rev. B
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DenseTrench™
DOME™
EcoSPARK™
E2CMOSTM
EnSignaTM
FACT™
FACT Quiet Series™
FAST
FASTr™
FRFET™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
OPTOLOGIC™
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerTrench
QFET™
QS™
QT Optoelectronics™
Quiet Series™
SILENT SWITCHER
SMART START™
STAR*POWER™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
TruTranslation™
UHC™
UltraFET
VCX™
STAR*POWER is used under license
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
2. A critical component is any component of a life
systems which, (a) are intended for surgical implant into
support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose
be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance
support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4
