HUF75309T3ST
Data Sheet
3A, 55V, 0.070 Ohm, N-Channel UltraFET
Power MOSFET
This N-Channel power MOSFET is
manufactured using the innovative
UltraFET® process. This advanced
process technology achieves the
lowest possible on-resistance per silicon area, resulting in
outstanding performance. This device is capable of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, lowvoltage bus switches, and power management in portable
and battery operated products.
January 2004
Features
• 3A, 55V
• Ultra Low On-Resistance, rDS(ON) = 0.070Ω
• Diode Exhibits Both High Speed and Soft Recovery
• Temperature Compensating PSPICE® Model
• Thermal Impedance SPICE Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Formerly developmental type TA75309.
D
Ordering Information
PART NUMBER
HUF75309T3ST
PACKAGE
SOT-223
G
BRAND
75309
S
NOTE: HUF75309T3ST is available only in tape and reel.
Packaging
SOT-223
DRAIN
(FLANGE)
GATE
DRAIN
SOURCE
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Automotive HUFA series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2004 Fairchild Semiconductor Corporation
HUF75309T3ST Rev. B1
HUF75309T3ST
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (R GS = 20kΩ) (Note 1) . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (Note 2) (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . .TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . Tpkg
HUF75309T3ST
55
55
±20V
UNITS
V
V
V
3
Figure 5
Figures 6, 14, 15
1.1
9.09
-55 to 150
A
W
mW/oC
oC
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 125oC.
Electrical Specifications
TA = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
MAX
UNITS
-
-
V
-
4
V
-
-
1
µA
VDS = 45V, VGS = 0V, TA = 150oC
-
-
250
µA
VGS = ±20V
-
-
100
nA
rDS(ON)
ID = 3A, VGS = 10V (Figure 9)
-
0.057
0.070
Ω
tON
VDD = 30V, ID ≅ 3A, R L = 10Ω,
VGS = 10V, R GS = 28Ω
-
-
45
ns
-
8
-
ns
Drain to Source Breakdown Voltage
Gate to Source Threshold Voltage
BVDSS
VGS(TH)
Zero Gate Voltage Drain Current
IDSS
Gate to Source Leakage Current
Drain to Source On Resistance
IGSS
Turn-On Time
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
TEST CONDITIONS
MIN
TYP
ID = 250µA, VGS = 0V (Figure 11)
55
VGS = VDS, ID = 250µA (Figure 10)
2
VDS = 50V, VGS = 0V
tr
-
20
-
ns
td(OFF)
-
12
-
ns
tf
-
28
-
ns
tOFF
Qg(TOT)
VGS = 0V to 20V
Gate Charge at 10V
Qg(10)
VGS = 0V to 10V
Threshold Gate Charge
Qg(TH)
VGS = 0V to 2V
Total Gate Charge
VDD = 30V, ID ≅ 3A,
RL = 10Ω
Ig(REF) = 1.0mA
(Figure 13)
-
-
65
ns
-
19
23
nC
-
10.7
13
nC
-
0.71
0.85
nC
Gate to Source Gate Charge
Qgs
-
1.40
-
nC
Gate to Drain “Miller” Charge
Qgd
-
4.80
-
nC
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
Thermal Resistance Junction to Ambient
RθJA
VDS = 25V, VGS = 0V, f = 1MHz
(Figure 12)
-
352
-
pF
-
146
-
pF
-
30
-
pF
Pad Area = 0.164 in2 (See note 2)
-
-
110
oC/W
Pad Area = 0.068 in2 (See TB377)
-
-
126
oC/W
Pad Area = 0.026 in2 (See TB377)
-
-
143
oC/W
MIN
TYP
MAX
UNITS
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
SYMBOL
TEST CONDITIONS
ISD = 3A
-
-
1.25
V
trr
ISD = 3A, dISD/dt = 100A/µs
-
-
41
ns
QRR
ISD = 3A, dISD/dt = 100A/µs
-
-
59
nC
VSD
NOTE:
2. 110oC/W measured using FR-4 board with 0.164 in2 footprint for 1000 seconds.
©2004 Fairchild Semiconductor Corporation
HUF75309T3ST Rev. B1
HUF75309T3ST
Typical Performance Curves
4
RθJA = 110oC/W
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
3
2
1
0.2
0
0
0
25
50
75
125
100
150
25
50
TA , AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
THERMAL IMPEDANCE
ZθJA, NORMALIZED
1
0.1
75
100
125
150
TA, AMBIENT TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.01
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
SINGLE PULSE
0.001
10-5
10-4
10-3
10-2
10-1
100
10 1
102
103
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
50
TJ = MAX RATED
TA = 25oC
RθJA = 110 oC/W
10
100µs
1ms
1
10ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
0.1
1
TA = 25 oC
FOR TEMPERATURES
ABOVE 25 oC DERATE PEAK
RθJA = 110oC/W CURRENT AS FOLLOWS:
I = I 25
150 - TA
125
10
VDSS(MAX) = 55V
10
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
©2004 Fairchild Semiconductor Corporation
I DM, PEAK CURRENT (A)
ID, DRAIN CURRENT (A)
100
200
1
10-3
10-2
10 -1
10 0
101
t, PULSE WIDTH (s)
102
103
FIGURE 5. PEAK CURRENT CAPABILITY
HUF75309T3ST Rev. B1
HUF75309T3ST
Typical Performance Curves
25
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
10
VGS = 20V
VGS = 10V
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
20
(Continued)
STARTING TJ = 25oC
STARTING TJ = 150oC
20
VGS = 8V
15
VGS = 7V
VGS = 6V
10
VGS = 5V
5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TA = 25oC
0
1
0.01
0.1
1
10
0
100
1
tAV, TIME IN AVALANCHE (ms)
2
3
4
5
VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
2.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
20
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
I D, DRAIN CURRENT (A)
25
15
10
25 oC
150oC
5
-55oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, I D = 3A
1.5
1.0
0.5
0
0
1.5
3.0
4.5
6.0
VGS, GATE TO SOURCE VOLTAGE (V)
-80
7.5
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.2
1.0
0.8
0.6
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.2
VGS = VDS, I D = 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
-40
ID = 250µA
1.1
1.0
0.9
0.8
0.4
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
©2004 Fairchild Semiconductor Corporation
-80
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
HUF75309T3ST Rev. B1
HUF75309T3ST
Typical Performance Curves
(Continued)
VGS = 0V, f = 1MHz
CISS = CGS + C GD
CRSS = CGD
COSS = C DS + CGD
500
C, CAPACITANCE (pF)
VGS , GATE TO SOURCE VOLTAGE (V)
600
400
CISS
300
200
COSS
100
CRSS
10
WAVEFORMS IN
DESCENDING ORDER:
ID = 3A
ID = 1A
8
VDD = 30V
6
4
2
0
0
0
10
20
30
40
50
VDS , DRAIN TO SOURCE VOLTAGE (V)
0
60
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
2
4
6
8
Qg, GATE CHARGE (nC)
10
12
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
Test Circuits and Waveforms
BVDSS
VDS
tP
L
IAS
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VDS
VDD
+
RG
VDD
-
VGS
DUT
0
tP
0V
IAS
tAV
0.01Ω
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 20V
VGS
Qg(10)
+
-
VDD
DUT
Ig(REF)
VGS = 10V
VGS
VGS = 2V
0
Qg(TH)
Ig(REF)
0
FIGURE 16. GATE CHARGE TEST CIRCUIT
©2004 Fairchild Semiconductor Corporation
FIGURE 17. GATE CHARGE WAVEFORM
HUF75309T3ST Rev. B1
HUF75309T3ST
Test Circuits and Waveforms
(Continued)
VDS
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
VGS
-
VDD
10%
0
10%
DUT
90%
RGS
VGS
VGS
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT
10%
50%
50%
PULSE WIDTH
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
Thermal Resistance vs. Mounting Pad Area
( T J ( MAX ) – T A )
P D ( MAX ) = -------------------------------------------R θJA
(EQ. 1)
In using surface mount devices such as the SOT-223
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of the
PD(MAX) is complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 20
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow.This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse applications
©2004 Fairchild Semiconductor Corporation
can be evaluated using the Fairchildl device Spice thermal
model or manually utilizing the normalized maximum
transient thermal impedance curve.
200
RθJA = 77.6 - 17.9 * ln(AREA)
143 oC/W - 0.026in2
RθJA (oC/W)
The maximum rated junction temperature, TJ(MAX), and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PD(MAX),
in an application. Therefore the application’s ambient
temperature, TA (oC), and thermal impedance RθJA (oC/W)
must be reviewed to ensure that TJ(MAX) is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
150
126oC/W - 0.068in 2
110oC/W - 0.164in2
100
50
0.01
0.1
1.0
AREA, TOP COPPER AREA (in2)
FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD
AREA
Displayed on the curve are the three RθJA values listed in
the Electrical Specifications table. The three points were
chosen to depict the compromise between the copper board
area, the thermal resistance and ultimately the power
dissipation, P D(MAX). Thermal resistances corresponding to
other component side copper areas can be obtained from
Figure 20 or by calculation using Equation 2. The area, in
square inches is the top copper area including the gate and
source pads.
R θJA = 77.6 – 17.9 × ln ( Area )
(EQ. 2)
HUF75309T3ST Rev. B1
HUF75309T3ST
PSPICE Electrical Model
.SUBCKT HUF75309T3ST 2 1 3 ;
REV December 97
CA 12 8 5.0e-10
CB 15 14 5.0e-10
CIN 6 8 3.27e-10
LDRAIN
DPLCAP
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
10
5
51
ESLC
11
-
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
LGATE
GATE
1
+
50
EVTEMP
RGATE +
18 22
9
20
21
EBREAK
17
18
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
8
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 5e-3
RGATE 9 20 2.2
RLDRAIN 2 5 10
RLGATE 1 9 27.1
RLSOURCE 3 7 5.6
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 4.8e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
DBREAK
+
RSLC2
LDRAIN 2 5 1e-9
LGATE 1 9 2.71e-9
LSOURCE 3 7 5.6e-10
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 58.46
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
DRAIN
2
5
12
S2A
13
8
14
13
S1B
17
18
RVTEMP
S2B
13
CA
RBREAK
15
CB
6
8
EGS
19
-
IT
14
+
+
VBAT
5
8
EDS
-
+
8
22
RVTHRES
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*50),3))}
.MODEL DBODYMOD D (IS = 3.4e-13 RS = 2.3e-2 TRS1 = 2.2e-3 TRS2 = 1.03e-6 CJO = 6.55e-10 TT = 3.6e-8 M = 0.57)
.MODEL DBREAKMOD D (RS = 2.8e-1 TRS1 = 1e-4 TRS2 = 2.25e-5)
.MODEL DPLCAPMOD D (CJO = 4e-10 IS = 1e-30 N = 10 M = 0.75)
.MODEL MMEDMOD NMOS (VTO = 3.35 KP = 3 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.2)
.MODEL MSTROMOD NMOS (VTO = 3.65 KP = 16 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.97 KP = 0.125 LAMBDA = 1e-3 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 22 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.07e-3 TC2 = -5.2e-7)
.MODEL RDRAINMOD RES (TC1 = 5.25e-2 TC2 = 1.08e-4)
.MODEL RSLCMOD RES (TC1 = 3.3e-3 TC2 = 1.03e-7)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -3.15e-3 TC2 = -9.41e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.61e-3 TC2 = 1.37e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -7.25 VOFF= -4.25)
VON = -4.25 VOFF= -7.25)
VON = 0 VOFF= 2.5)
VON = 2.5 VOFF= 0)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2004 Fairchild Semiconductor Corporation
HUF75309T3ST Rev. B1
HUF75309T3ST
SPICE Thermal Model
7
JUNCTION
REV December 97
HUF75309T3ST
CTHERM1 7 6 7.5e-5
CTHERM2 6 5 4.0e-4
CTHERM3 5 4 1.7e-3
CTHERM4 4 3 1.5e-2
CTHERM5 3 2 7.1e-2
CTHERM6 2 1 5.9e-1
RTHERM1
RTHERM1 7 6 7.0e-2
RTHERM2 6 5 2.7e-1
RTHERM3 5 4 2.0
RTHERM4 4 3 3.5
RTHERM5 3 2 30
RTHERM6 2 1 80
RTHERM2
CTHERM1
6
CTHERM2
5
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
1
©2004 Fairchild Semiconductor Corporation
CASE
HUF75309T3ST Rev. B1
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I7
