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HUF75333S3

HUF75333S3

  • 厂商:

    ONSEMI(安森美)

  • 封装:

    SOT226

  • 描述:

    MOSFET N-CH 55V 60A TO-262AA

  • 数据手册
  • 价格&库存
HUF75333S3 数据手册
HUF75333G3, HUF75333P3, HUF75333S3S, HUF75333S3 Data Sheet 66A, 55V, 0.016 Ohm. N-Channel UltraFET Power MOSFETs These N-Channel power MOSFETs are manufactured using the innovative UltraFET® process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching convertors, motor drivers, relay drivers, lowvoltage bus switches, and power management in portable and battery-operated products. . Ordering Information PART NUMBER December 2001 Features • 66A, 55V • Simulation Models - Temperature Compensated PSPICE® and SABER™ Models - SPICE and SABER Thermal Impedance Models Available on the WEB at: www.fairchildsemi.com • Peak Current vs Pulse Width Curve • UIS Rating Curve • Related Literature - TB334, “Guidelines for Soldering Surface Mount Components to PC Boards” Formerly developmental type TA75333 Symbol PACKAGE BRAND HUF75333G3 TO-247 75333G HUF75333P3 TO-220AB 75333P HUF75333S3S TO-263AB 75333S HUF75333S3 TO-262AA 75333S D G S NOTE: When ordering, use the entire part number. Add the suffix T to obtain the TO-263AB variant in tape and reel, e.g., HUF75333S3ST. Packaging JEDEC STYLE TO-247 SOURCE DRAIN GATE JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) DRAIN (TAB) JEDEC TO-263AB GATE SOURCE DRAIN (FLANGE) JEDEC TO-262ABA DRAIN (FLANGE) SOURCE DRAIN GATE Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html For severe environments, see our Automotive HUFA series. All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification. ©2003 Fairchild Semiconductor Corporation HUF75333G3, HUF75333P3, HUF75333S3S, HUF75333S3 Rev. B1 HUF75333G3, HUF75333P3, HUF75333S3S, HUF75333S3 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified UNITS V V V 55 55 ±20 Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . .TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . Tpkg 66 Figure 4 Figures 6, 14, 15 150 1 -55 to 175 A W W/oC oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 55 - - V OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current BVDSS IDSS IGSS ID = 250µA, VGS = 0V (Figure 11) VDS = 50V, VGS = 0V - - 1 µA VDS = 45V, VGS = 0V, TC = 150oC - - 250 µA VGS = ±20V - - ±100 nA ON STATE SPECIFICATIONS Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 10) 2 - 4 V Drain to Source On Resistance rDS(ON) ID = 66A, VGS = 10V (Figure 9) - 0.013 0.016 Ω THERMAL SPECIFICATIONS Thermal Resistance Junction to Case RθJC (Figure 3) - - 1 oC/W Thermal Resistance Junction to Ambient RθJA TO-247 - - 30 oC/W TO-220, TO-263 - - 62 oC/W VDD = 30V, ID ≅ 66A, RL = 0.455Ω, VGS = 10V, RGS = 6.8Ω - - 100 ns - 12 - ns tr - 55 - ns td(OFF) - 11 - ns tf - 25 - ns tOFF - - 55 ns - 70 85 nC - 40 50 nC - 2.5 3.0 nC - 6.2 - nC - 16 - nC SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time tON td(ON) GATE CHARGE SPECIFICATIONS Total Gate Charge Qg(TOT) VGS = 0V to 20V Gate Charge at 10V Qg(10) VGS = 0V to 10V Threshold Gate Charge Qg(TH) VGS = 0V to 2V Gate to Source Gate Charge Qgs Gate to Drain “Miller” Charge Qgd ©2003 Fairchild Semiconductor Corporation VDD = 30V, ID ≅ 66A, RL = 0.455Ω Ig(REF) = 1.0mA (Figure 13) HUF75333G3, HUF75333P3, HUF75333S3S, HUF75333S3 Rev. B1 HUF75333G3, HUF75333P3, HUF75333S3S, HUF75333S3 TC = 25oC, Unless Otherwise Specified Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS - 1300 - pF - 480 - pF - 115 - pF CAPACITANCE SPECIFICATIONS Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Diode Voltage MIN TYP MAX UNITS ISD = 66A - - 1.25 V trr ISD = 66A, dISD/dt = 100A/µs - - 75 ns QRR ISD = 66A, dISD/dt = 100A/µs - - 140 nC VSD Reverse Recovery Time Reverse Recovered Charge TEST CONDITIONS 1.2 70 1.0 60 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER Typical Performance Curves 0.8 0.6 0.4 0.2 50 40 30 20 10 0 0 0 25 50 75 100 125 150 25 175 50 TC , CASE TEMPERATURE (oC) 75 100 125 150 175 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 2 ZθJC, NORMALIZED THERMAL IMPEDANCE 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE ©2003 Fairchild Semiconductor Corporation HUF75333G3, HUF75333P3, HUF75333S3S, HUF75333S3 Rev. B1 HUF75333G3, HUF75333P3, HUF75333S3S, HUF75333S3 Typical Performance Curves (Continued) IDM, PEAK CURRENT (A) 1000 TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 175 - TC I = I25 150 VGS = 10V 100 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 50 10-5 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) FIGURE 4. PEAK CURRENT CAPABILITY 500 500 IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) TJ = MAX RATED TC = 25oC 100 100µs 10 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10ms VDSS(MAX) = 55V If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 100 STARTING TJ = 25oC STARTING TJ = 150oC 10 1 10 1 100 200 0.001 VDS, DRAIN TO SOURCE VOLTAGE (V) 0.01 0.1 1 10 tAV, TIME IN AVALANCHE (ms) NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 5. FORWARD BIAS SAFE OPERATING AREA FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 150 150 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 15V 120 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) VGS = 20V VGS = 10V VGS = 7V VGS = 6V 90 60 VGS = 5V 30 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TC = 25oC 0 0 1.5 3.0 4.5 6.0 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 7. SATURATION CHARACTERISTICS ©2003 Fairchild Semiconductor Corporation 120 -55oC 25oC 90 175oC 60 30 0 7.5 0 1.5 3.0 4.5 6.0 7.5 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 8. TRANSFER CHARACTERISTICS HUF75333G3, HUF75333P3, HUF75333S3S, HUF75333S3 Rev. B1 HUF75333G3, HUF75333P3, HUF75333S3S, HUF75333S3 Typical Performance Curves (Continued) 1.2 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 66A VGS = VDS, ID = 250µA 2.0 NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED DRAIN TO SOURCE ON RESISTANCE 2.5 1.5 1.0 0.5 -80 -40 0 40 80 120 160 1.0 0.8 0.6 0.4 -80 200 -40 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 200 FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 1.2 2000 ID = 250µA C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 1.1 1.0 0.9 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 1500 CISS 1000 COSS 500 CRSS 0.8 0 -80 -40 0 40 80 120 160 200 0 10 TJ , JUNCTION TEMPERATURE (oC) FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE VGS , GATE TO SOURCE VOLTAGE (V) 20 30 40 50 60 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 10 VDD = 30V 8 6 WAVEFORMS IN DESCENDING ORDER: ID = 66A ID = 50A ID = 33A ID = 16A 4 2 0 0 10 20 30 40 Qg, GATE CHARGE (nC) NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT ©2003 Fairchild Semiconductor Corporation HUF75333G3, HUF75333P3, HUF75333S3S, HUF75333S3 Rev. B1 HUF75333G3, HUF75333P3, HUF75333S3S, HUF75333S3 Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN REQUIRED PEAK IAS + RG VDS IAS VDD VDD - VGS DUT tP 0V IAS 0 0.01Ω tAV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS VDS VDD RL Qg(TOT) VDS VGS = 20V VGS Qg(10) + VDD VGS = 10V VGS DUT VGS = 2V IG(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORM VDS tON tOFF td(ON) td(OFF) tr RL VDS tf 90% 90% + VGS - VDD 10% 0 10% DUT 90% RGS VGS VGS 0 FIGURE 18. SWITCHING TIME TEST CIRCUIT ©2003 Fairchild Semiconductor Corporation 10% 50% 50% PULSE WIDTH FIGURE 19. RESISTIVE SWITCHING WAVEFORMS HUF75333G3, HUF75333P3, HUF75333S3S, HUF75333S3 Rev. B1 HUF75333G3, HUF75333P3, HUF75333S3S, HUF75333S3 PSPICE Electrical Model .SUBCKT HUF75333 2 1 3 ; rev 02/24/99 CA 12 8 1.8e-9 CB 15 14 1.73e-9 CIN 6 8 1.19e-9 LDRAIN DPLCAP DRAIN 2 5 10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD DBREAK + RSLC2 5 51 ESLC 11 - EBREAK 11 7 17 18 58.85 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 RLDRAIN RSLC1 51 RDRAIN 6 8 ESG EVTHRES + 19 8 + LGATE GATE 1 LDRAIN 2 5 1e-9 LGATE 1 9 1e-9 LSOURCE 3 7 1e-9 K1 LSOURCE LGATE 0.0085 + 50 - EVTEMP RGATE + 18 22 9 20 21 EBREAK 17 18 DBODY - 16 MWEAK 6 MMED MSTRO RLGATE LSOURCE CIN 8 SOURCE 3 7 RSOURCE RLSOURCE MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD S1A 12 RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 4.50e-3 RGATE 9 20 1 RLDRAIN 2 5 10 RLGATE 3 7 10 RLSOURCE 3 7 11 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 5.95e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B S2A 14 13 13 8 S1B 17 18 RVTEMP S2B 13 CA RBREAK 15 CB 6 8 - - IT 14 + + EGS 19 VBAT 5 8 EDS - + 8 22 RVTHRES 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*180),4))} .MODEL DBODYMOD D (IS = 1.3e-12 RS =0.003 TRS1 = 2.7e-3 TRS2 = 7e-7 CJO = 1.7e-9 TT = 40e-8 M = 0.45 IKF= 20 XTI= 6) .MODEL DBREAKMOD D (RS = 0.1e-1 TRS1 = -4e-4 TRS2 = 1.55e-5 IKF= 1e-5) .MODEL DPLCAPMOD D (CJO = 1.8e-9 IS = 1e-30 N = 1 M = 0.9 vj= 1.45) .MODEL MMEDMOD NMOS (VTO = 3.183 KP = 2 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1) .MODEL MSTROMOD NMOS (VTO = 3.66 KP = 51.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.703 KP = 0.008 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 10 ) .MODEL RBREAKMOD RES (TC1 = 1.05e-3 TC2 = 4.5e-7) .MODEL RDRAINMOD RES (TC1 = 1.16e-2 TC2 = 1.7e-5) .MODEL RSLCMOD RES (TC1 = 3.96e-3 TC2 = 2.7e-6) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-5) .MODEL RVTHRESMOD RES (TC = -2.8e-3 TC2 = -1.0e-6) .MODEL RVTEMPMOD RES (TC1 = -2.75e-3 TC2 = 0.5e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -8 VOFF= -3) VON = -3 VOFF= -8) VON = 0 VOFF= 0.5) VON = 0.5 VOFF= 0) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. ©2003 Fairchild Semiconductor Corporation HUF75333G3, HUF75333P3, HUF75333S3S, HUF75333S3 Rev. B1 HUF75333G3, HUF75333P3, HUF75333S3S, HUF75333S3 SABER Electrical Model REV August 1997 template huf75333 n2, n1, n3 electrical n2, n1, n3 { var i iscl d..model dbodymod = (is = 1.3e-12, xti = 6, cjo = 1.7e-9, tt = 40e-8, n = 1, m = 0.45, vj=0.75) d..model dbreakmod = () d..model dplcapmod = (cjo = 1.8e-9, is = 1e-30, n = 1, m = 0.9, vj = 1.45, fc=0.5) m..model mmedmod = (type=_n, vto = 3.183, kp = 2, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.66, kp = 51.5, is = 1e-30, tox = 1) DPLCAP m..model mweakmod = (type=_n, vto = 2.703, kp = 8e-3, is = 1e-30, tox = 1) 10 sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -8, voff = -3) sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -3, voff = -8) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0, voff = .5) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = .5, voff = 0) RSLC2 DRAIN 2 RSLC1 51 RLDRAIN RDBREAK 72 ISCL c.ca n12 n8 = 1.8e-9 c.cb n15 n14 = 1.73e-9 c.cin n6 n8 = 1.19e-9 RDRAIN 6 8 ESG EVTHRES + 19 8 + LGATE GATE 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 1e-9 l.lsource n3 n7 = 1e-9 EVTEMP RGATE + 18 22 9 20 MWEAK DBODY EBREAK + 17 18 MMED MSTRO CIN 71 11 16 6 RLGATE - 8 LSOURCE 7 SOURCE 3 RSOURCE m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u res.rbreak n17 n18 = 1, tc1 = 1.07e-3, tc2 = 4.5e-7 res.rdbody n71 n5 = 3e-3, tc1 = 2.7e-3, tc2 = 7e-7 res.rdbreak n72 n5 = 1.1e-1, tc1 = -4e-4, tc2 = -1.55e-5 res.rdrain n50 n16 = 4.5e-3, tc1 = 1.16e-2, tc2 = 1.7e-5 res.rgate n9 n20 = 1 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 10 res.rlsource n3 n7 = 10 res.rslc1 n5 n51 = 1e-6, tc1 = 3.96e-3, tc2 = 2.7e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 5.95e-3, tc1 = 1e-3, tc2 = 1e-5 res.rvtemp n18 n19 = 1, tc1 = -2.75e-3, tc2 = 0.5e-6 res.rvthres n22 n8 = 1, tc1 = -2.8e-3, tc2 = -1e-6 21 RDBODY DBREAK 50 - d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 LDRAIN 5 RLSOURCE S1A 12 13 8 S2A 14 13 S1B CA RBREAK 15 17 18 RVTEMP S2B 13 CB 6 8 EGS 19 - - IT 14 + + VBAT 5 8 EDS - + 8 22 RVTHRES spe.ebreak n11 n7 n17 n18 = 58.85 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc = 1 equations { i (n51->n50) + = iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/180))** 4)) } } ©2003 Fairchild Semiconductor Corporation HUF75333G3, HUF75333P3, HUF75333S3S, HUF75333S3 Rev. B1 HUF75333G3, HUF75333P3, HUF75333S3S, HUF75333S3 SPICE Thermal Model th REV January 1999 JUNCTION HUF75333 CTHERM1 th 6 4.9e-4 CTHERM2 6 5 4.5e-3 CTHERM3 5 4 6.0e-3 CTHERM4 4 3 8.5e-3 CTHERM5 3 2 1.0e-2 CTHERM6 2 tl 5.0e-2 RTHERM1 th 6 6.0e-4 RTHERM2 6 5 6.8e-3 RTHERM3 5 4 3.3e-2 RTHERM4 4 3 9.7e-2 RTHERM5 3 2 3.3e-1 RTHERM6 2 tl 3.6e-1 SABER Thermal Model CTHERM1 RTHERM1 6 CTHERM2 RTHERM2 5 CTHERM3 RTHERM3 SABER thermal model HUF75333 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 4.9e-4 ctherm.ctherm2 6 5 = 4.5e-3 ctherm.ctherm3 5 4 = 6.0e-3 ctherm.ctherm4 4 3 = 8.5e-3 ctherm.ctherm5 3 2 = 1.0e-2 ctherm.ctherm6 2 tl = 5.0e-2 rtherm.rtherm1 th 6 = 6.0e-4 rtherm.rtherm2 6 5 = 6.8e-3 rtherm.rtherm3 5 4 = 3.3e-2 rtherm.rtherm4 4 3 = 9.7e-2 rtherm.rtherm5 3 2 = 3.3e-1 rtherm.rtherm6 2 tl = 3.6e-1 } 4 CTHERM4 RTHERM4 3 CTHERM5 RTHERM5 2 CTHERM6 RTHERM6 tl ©2003 Fairchild Semiconductor Corporation CASE HUF75333G3, HUF75333P3, HUF75333S3S, HUF75333S3 Rev. B1 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FACT™ ActiveArray™ FACT Quiet Series™ Bottomless™ FASTâ CoolFET™ FASTr™ CROSSVOLT™ FRFET™ DOME™ GlobalOptoisolator™ EcoSPARK™ GTO™ E2CMOSTM HiSeC™ EnSignaTM I2C™ Across the board. Around the world.™ The Power Franchise™ Programmable Active Droop™ ImpliedDisconnect™ PACMAN™ POP™ ISOPLANAR™ Power247™ LittleFET™ PowerTrenchâ MicroFET™ QFET™ MicroPak™ QS™ MICROWIRE™ QT Optoelectronics™ MSX™ Quiet Series™ MSXPro™ RapidConfigure™ OCX™ RapidConnect™ OCXPro™ SILENT SWITCHERâ OPTOLOGICâ SMART START™ OPTOPLANAR™ SPM™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogicâ TruTranslation™ UHC™ UltraFETâ VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I2 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: onsemi: HUF75333P3 SI9410DY HUF75333S3 HUF75333S3ST HUFA76619D3ST
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