HUF75545S3ST

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Other names and brands may be claimed as the property of others. HUF75545P3, HUF75545S3S October 2013 Data Sheet N-Channel UltraFET Power MOSFET 80 V, 75 A, 10 mΩ Packaging JEDEC TO-220AB JEDEC TO-263AB DRAIN (FLANGE) SOURCE DRAIN GATE GATE SOURCE Features • Ultra Low On-Resistance - rDS(ON) = 0.010Ω,VGS = 10V • Simulation Models - Temperature Compensated PSPICE® and SABER™ Electrical Models - Spice and SABER Thermal Impedance Models - www.onsemi.com • Peak Current vs Pulse Width Curve DRAIN (FLANGE) HUF75545S3ST HUF75545P3 • UIS Rating Curve Ordering Information Symbol PART NUMBER D PACKAGE BRAND HUF75545P3 TO-220AB 75545P HUF75545S3ST TO-263AB 75545S G S Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (TC= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC= 100oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg NOTES: HUF75545P3, HUF75545S3ST 80 80 ±20 UNITS V V V 75 73 Figure 4 Figure 6 270 1.8 -55 to 175 W W/oC oC 300 260 oC oC A A 1. TJ = 25oC to 150oC. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. ©2002 Semiconductor Components Industries, LLC. October-2017, Rev. 3 Publication Order Number: HUF75545S3S/D HUF75545P3, HUF75545S3S Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 80 - - V VDS = 75V, VGS = 0V - - 1 µA VDS = 70V, VGS = 0V, TC = 150oC - - 250 µA VGS = ±20V - - ±100 nA OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current BVDSS IDSS IGSS ID = 250µA, VGS = 0V (Figure 11) ON STATE SPECIFICATIONS Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 10) 2 - 4 V Drain to Source On Resistance rDS(ON) ID = 75A, VGS = 10V (Figure 9) - 0.0082 0.010 Ω TO-220 and TO-263 - - 0.55 oC/W - - 62 oC/W - - 210 ns - 14 - ns tr - 125 - ns td(OFF) - 40 - ns tf - 90 - ns tOFF - - 195 ns - 195 235 nC - 105 125 nC - 6.8 8.2 nC THERMAL SPECIFICATIONS Thermal Resistance Junction to Case RθJC Thermal Resistance Junction to Ambient RθJA SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time tON td(ON) VDD = 40V, ID = 75A VGS = 10V, RGS = 2.5Ω GATE CHARGE SPECIFICATIONS Qg(TOT) VGS = 0V to 20V Gate Charge at 10V Qg(10) VGS = 0V to 10V Threshold Gate Charge Qg(TH) VGS = 0V to 2V Total Gate Charge VDD = 40V, ID = 75A, Ig(REF) = 1.0mA (Figure 13) Gate to Source Gate Charge Qgs - 15 - nC Gate to Drain “Miller” Charge Qgd - 43 - nC - 3750 - pF - 1100 - pF - 350 - pF MIN TYP MAX UNITS ISD = 75A - - 1.25 V ISD = 35A - - 1.00 V trr ISD = 75A, dISD/dt = 100A/µs - - 100 ns QRR ISD = 75A, dISD/dt = 100A/µs - - 300 nC CAPACITANCE SPECIFICATIONS Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge SYMBOL VSD TEST CONDITIONS www.onsemi.com 2 HUF75545P3, HUF75545S3S Typical Performance Curves 80 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 60 VGS = 10V 40 20 0.2 0 0 25 50 75 100 150 125 0 175 25 50 75 TC , CASE TEMPERATURE (oC) 100 125 150 175 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 2 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 ZθJC, NORMALIZED THERMAL IMPEDANCE 1 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE IDM, PEAK CURRENT (A) 2000 TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 1000 175 - TC I = I25 150 VGS = 10V 100 50 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10-5 10-4 10-3 10-2 t, PULSE WIDTH (s) FIGURE 4. PEAK CURRENT CAPABILITY www.onsemi.com 3 10-1 100 101 HUF75545P3, HUF75545S3S Typical Performance Curves (Continued) 600 IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 600 100 100µs OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10 1ms 10ms SINGLE PULSE TJ = MAX RATED TC = 25oC 1 1 10 100 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] STARTING TJ = 25oC 100 STARTING TJ = 150oC 10 0.001 200 0.01 0.1 10 1 tAV, TIME IN AVALANCHE (ms) VDS, DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to ON Semiconductor Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 5. FORWARD BIAS SAFE OPERATING AREA 150 120 90 60 TJ = 175oC 30 TJ = 25oC 120 VGS =5V 90 60 30 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TC = 25oC TJ = -55oC 0 0 2 3 4 5 6 0 1 VGS, GATE TO SOURCE VOLTAGE (V) 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS 1.2 2.5 PULSE DURATION = 80µs VGS = 10V, ID = 75A DUTY CYCLE = 0.5% MAX VGS = VDS, ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED DRAIN TO SOURCE ON RESISTANCE VGS = 7V VGS = 6V VGS = 20V VGS = 10V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 15V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 150 2.0 1.5 1.0 1.0 0.8 0.6 0.4 0.5 -80 -40 0 40 80 120 160 -80 200 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE www.onsemi.com 4 HUF75545P3, HUF75545S3S Typical Performance Curves (Continued) 10000 ID = 250µA CISS = CGS + CGD C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.2 1.1 1.0 0.9 0.8 COSS ≅ CDS + CGD 1000 CRSS = CGD VGS = 0V, f = 1MHz 100 -80 -40 0 40 80 120 160 200 0.1 TJ , JUNCTION TEMPERATURE (oC) 1 FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE VGS , GATE TO SOURCE VOLTAGE (V) 80 FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 10 VDD = 40V 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 75A ID = 35A 2 0 0 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 30 60 90 120 Qg, GATE CHARGE (nC) NOTE: Refer to ON Semiconductor Application Notes AN7254 and AN7260. FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT www.onsemi.com 5 HUF75545P3, HUF75545S3S Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN REQUIRED PEAK IAS IAS + RG VDS VDD VDD - VGS DUT tP 0V IAS 0 0.01Ω tAV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS VDS VDD RL Qg(TOT) VDS VGS = 20V VGS Qg(10) + VDD VGS = 10V VGS DUT VGS = 2V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORMS VDS tON tOFF td(ON) td(OFF) tr RL VDS tf 90% 90% + VGS VDD 10% 10% 0 DUT 90% RGS VGS VGS 0 FIGURE 18. SWITCHING TIME TEST CIRCUIT 10% 50% 50% PULSE WIDTH FIGURE 19. SWITCHING TIME WAVEFORM www.onsemi.com 6 HUF75545P3, HUF75545S3S PSPICE Electrical Model .SUBCKT HUF75545 2 1 3 ; rev 21 May 1999 CA 12 8 5.4e-9 CB 15 14 5.3e-9 CIN 6 8 3.4e-9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD LDRAIN DPLCAP DRAIN 2 5 10 5 51 ESLC 11 - RDRAIN 6 8 EVTHRES + 19 8 + LGATE GATE 1 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD + 50 - IT 8 17 1 EVTEMP RGATE + 18 22 9 20 21 EBREAK 17 18 DBODY - 16 MWEAK 6 MMED MSTRO RLGATE LSOURCE CIN 8 SOURCE 3 7 RSOURCE RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 4.80e-3 RGATE 9 20 0.87 RLDRAIN 2 5 10 RLGATE 1 9 51 RLSOURCE 3 7 44 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 1.6e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B DBREAK + RSLC2 ESG LDRAIN 2 5 1.0e-9 LGATE 1 9 5.1e-9 LSOURCE 3 7 4.4e-9 RLDRAIN RSLC1 51 EBREAK 11 7 17 18 87.4 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 RLSOURCE S1A 12 S2A S1B CA 17 18 RVTEMP S2B 13 CB 6 8 EGS 19 VBAT 5 8 EDS - - IT 14 + + 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD RBREAK 15 14 13 13 8 - + 8 22 RVTHRES VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*320),3))} .MODEL DBODYMOD D (IS = 3.6e-12 RS = 2.1e-3 TRS1 = 1.5e-3 TRS2 = 5.1e-6 CJO = 4.6e-9 TT = 3.3e-8 M = 0.55) .MODEL DBREAKMOD D (RS = 2.3e-1 TRS1 = 0 TRS2 = -1.8e-5) .MODEL DPLCAPMOD D (CJO = 4.8e-9 IS = 1e-30 N = 10 VJ = 1 M = 0.8) .MODEL MMEDMOD NMOS (VTO = 3.04 KP = 6 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.87) .MODEL MSTROMOD NMOS (VTO = 3.5 KP = 105 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.65 KP = 0.12 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 8.7 ) .MODEL RBREAKMOD RES (TC1 = 1.3e-3 TC2 = -1e-6) .MODEL RDRAINMOD RES (TC1 = 9e-3 TC2 = 2.8e-5) .MODEL RSLCMOD RES (TC1 = 1.53e-3 TC2 = 2e-5) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -2.3e-3 TC2 = -1.2e-5) .MODEL RVTEMPMOD RES (TC1 = -2.9e-3 TC2 = 5e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -5 VOFF= -3) VON = -3 VOFF= -5) VON = -1.5 VOFF= 0.5) VON = 0.5 VOFF= -1.5) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. www.onsemi.com 7 HUF75545P3, HUF75545S3S SABER Electrical Model REV 21 may 1999 template huf75545 n2,n1,n3 electrical n2,n1,n3 { var i iscl d..model dbodymod = (is = 3.6e-12, cjo = 4.6e-9, tt = 3.3e-8, m = 0.55) d..model dbreakmod = () d..model dplcapmod = (cjo = 4.8e-9, is = 1e-30, vj=1.0, m = 0.8 ) m..model mmedmod = (type=_n, vto = 3.04, kp = 6, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.5, kp = 105, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 2.65, kp = 0.12, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5, voff = -3) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -3, voff = -5) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.5, voff = 0.5) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.5) LDRAIN DPLCAP 10 RSLC1 51 RLDRAIN RDBREAK RSLC2 c.ca n12 n8 = 5.4e-9 c.cb n15 n14 = 5.3e-9 c.cin n6 n8 = 3.4e-9 72 ISCL RDRAIN 6 8 ESG EVTHRES + 19 8 + LGATE i.it n8 n17 = 1 GATE 1 EVTEMP RGATE + 18 22 9 20 21 DBODY EBREAK + 17 18 MSTRO - 8 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u LSOURCE 7 RSOURCE RLSOURCE S1A res.rbreak n17 n18 = 1, tc1 = 1.3e-3, tc2 = -1e-6 res.rdbody n71 n5 = 2.1e-3, tc1 = 1.5e-3, tc2 = 5.1e-6 res.rdbreak n72 n5 = 2.3e-1, tc1 = 0, tc2 = -1.8e-5 res.rdrain n50 n16 = 4.8e-3, tc1 = 9e-3, tc2 = 2.8e-5 res.rgate n9 n20 = 0.87 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 51 res.rlsource n3 n7 = 44 res.rslc1 n5 n51 = 1e-6, tc1 = 1.53e-3, tc2 = 2e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 1.6e-3, tc1 = 1e-3, tc2 = 1e-6 res.rvtemp n18 n19 = 1, tc1 = -2.9e-3, tc2 = 5e-7 res.rvthres n22 n8 = 1, tc1 = -2.3e-3, tc2 = -1.2e-5 MWEAK MMED CIN 71 11 16 6 RLGATE RDBODY DBREAK 50 - d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 5.1e-9 l.lsource n3 n7 = 4.4e-9 DRAIN 2 5 12 S2A 13 8 14 13 S1B CA RBREAK 15 17 18 RVTEMP S2B 13 CB 6 8 EGS 19 - - IT 14 + + VBAT 5 8 EDS - + 8 22 RVTHRES spe.ebreak n11 n7 n17 n18 = 87.4 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/320))** 3)) } } www.onsemi.com 8 SOURCE 3 HUF75545P3, HUF75545S3S SPICE Thermal Model th JUNCTION REV 21 May 1999 HUF75545T CTHERM1 th 6 6.4e-3 CTHERM2 6 5 3.0e-2 CTHERM3 5 4 1.4e-2 CTHERM4 4 3 1.6e-2 CTHERM5 3 2 5.5e-2 CTHERM6 2 tl 1.5 RTHERM1 RTHERM1 th 6 3.2e-3 RTHERM2 6 5 8.1e-3 RTHERM3 5 4 2.3e-2 RTHERM4 4 3 1.3e-1 RTHERM5 3 2 1.8e-1 RTHERM6 2 tl 3.8e-2 RTHERM2 CTHERM1 6 CTHERM2 5 RTHERM3 CTHERM3 SABER Thermal Model SABER thermal model HUF75545T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 6.4e-3 ctherm.ctherm2 6 5 = 3.0e-2 ctherm.ctherm3 5 4 = 1.4e-2 ctherm.ctherm4 4 3 = 1.6e-2 ctherm.ctherm5 3 2 = 5.5e-2 ctherm.ctherm6 2 tl = 1.5 rtherm.rtherm1 th 6 = 3.2e-3 rtherm.rtherm2 6 5 = 8.1e-3 rtherm.rtherm3 5 4 = 2.3e-2 rtherm.rtherm4 4 3 = 1.3e-1 rtherm.rtherm5 3 2 = 1.8e-1 rtherm.rtherm6 2 tl = 3.8e-2 } 4 RTHERM4 CTHERM4 3 RTHERM5 CTHERM5 2 RTHERM6 CTHERM6 tl www.onsemi.com 9 CASE ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 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