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MOSFET – Power, N-Channel,
Ultrafet
100 V, 56 A, 25 mW
HUF75639G3, HUF75639P3,
HUF75639S3S, HUF75639S3
www.onsemi.com
These N−Channel power MOSFETs are manufactured using the
innovative Ultrafet process. This advanced process technology
achieves the lowest possible on− resistance per silicon area, resulting
in outstanding performance. This device is capable of withstanding
high energy in the avalanche mode and the diode exhibits very low
reverse recovery time and stored charge. It was designed for use in
applications where power efficiency is important, such as switching
regulators, switching converters, motor drivers, relay drivers,
low−voltage bus switches, and power management in portable and
battery− operated products.
Formerly developmental type TA75639.
Features
• 56 A, 100 V
• Simulation Models
Temperature Compensated PSPICE® and SABER™ Electrical
Models
♦ Spice and Saber Thermal Impedance Models
♦ www.onsemi.com
Peak Current vs Pulse Width Curve
UIS Rating Curve
Related Literature
♦ TB334, “Guidelines for Soldering Surface Mount Components to
PC Boards”
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
TO−247−3LD
CASE 340CK
TO−220−3LD
CASE 340AT
D2PAK−3
CASE 418AJ
I2PAK
CASE 418AV
♦
•
•
•
•
MARKING DIAGRAMS
&Y
&Z
&3
&K
75639x
x
$Y&Z&3&K
75639G
$Y&Z&3&K
75639P
$Y&Z&3&K
75639S
$Y&Z&3&K
75639S
= ON Semiconductor Logo
= Assembly Plant Code
= 3−Digit Date Code
= 2−Digit Lot Traceability Code
= Specific Device Code
= G/P/S
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2001
April, 2020 − Rev. 4
1
Publication Order Number:
HUF75639G3/D
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3
ORDERING INFORMATION
PART NUMBER
PACKAGE
BRAND
HUF75639G3
TO−247
75639G
HUF75639P3
TO−220AB
75639P
HUF75639S3ST
TO−263AB
75639S
HUF75639S3
TO−262AA
75639S
PACKAGING
Figure 1.
ABSOLUTE MAXIMUM RATINGS TC = 25°C unless otherwise specified
Symbol
Ratings
Units
Drain to Source Voltage (Note 1)
VDSS
100 V
V
Drain to Gate Voltage (RGS = 20 kW) (Note 1)
Description
VDGR
100 V
V
Gate to Source Voltage
VGS
±20 V
V
Drain Current
Continuous (Figure 2)
Pulsed Drain Current
ID
IDM
56
Figure 4
A
Pulsed Avalanche Rating
EAS
Figures 6, 14, 15
Power Dissipation
Derate Above 25°C
PD
200
1.35
W
W/°C
TJ, TSTG
−55 to 175°C
°C
TL
Tpkg
300
260
°C
Operating and Storage Temperature
Maximum Temperature for Soldering
Leads at 0.063in (1.6 mm) from Case for 10s
Package Body for 10 s, See Techbrief 334
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. TJ = 25°C to 150°C.
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2
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3
ELECTRICAL SPECIFICATION TJ = 25 °C unless otherwise specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
100
−
−
V
OFF STATE SPECIFICATIONS
BVDSS
IDSS
Drain to Source Breakdown Voltage
ID = 250 mA, VGS = 0 V (Figure 11)
Zero Gate Voltage Drain Current
VDS = 95 V, VGS = 0 V
−
−
1
mA
VDS = 90 V, VGS = 0 V, TC = 150°C
−
−
250
mA
VGS = ±20 V
−
−
±100
nA
Gate to Source Leakage Current
IGSS
ON STATE SPECIFICATIONS
VGS(TH)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 mA (Figure 10)
2
−
4
V
rDS(ON)
Drain to Source On Resistance
ID = 56 A, VGS = 10 V (Figure 9)
−
0.021
0.025
mW
THERMAL SPECIFICATIONS
RθJC
Thermal Resistance Junction to Case
(Figure 3)
−
−
0.74
°C/W
RθJA
Thermal Resistance Junction to Ambient
TO−247
−
−
30
°C/W
TO−220, TO−263, TO−262
−
−
62
°C/W
VDD = 50 V, ID ≅ 56 A, RL = 0.89 W,
VGS = 10 V, RGS = 5.1 W
−
−
110
ns
−
15
−
ns
Rise Time
−
60
−
ns
Turn−Off Delay Time
−
20
−
ns
Fall Time
−
25
−
ns
Turn−Off Time
−
−
70
ns
−
110
130
nC
−
57
75
nC
−
3.7
4.5
nC
SWITCHING SPECIFICATIONS (VGS = 10 V)
Turn−On Time
tON
td(ON)
Turn−On Delay Time
tr
td(OFF)
tf
tOFF
GATE CHARGE SPECIFICATIONS
Total Gate Charge
VGS = 0 V to 20 V
Qg(10)
Gate Charge at 10 V
VGS = 0 V to 10 V
Qg(TH)
Threshold Gate Charge
VGS = 0 V to 2 V
Qg(TOT)
VDD = 50 V, ID ≅ 56 A,
RL = 0.89 W
Ig(REF) = 1.0 mA
(Figure 13)
Qgs
Gate to Source Gate Charge
−
9.8
−
nC
Qgd
Gate to Drain “Miller” Charge
−
24
−
nC
−
2000
−
pF
−
500
−
pF
−
65
−
pF
CAPACITANCE SPECIFICATIONS
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
VDS = 25 V, VGS = 0 V,
f = 1 MHz
(Figure 12)
SOURCE TO DRAIN DIODE SPECIFICATIONS
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
SYMBOL
MIN
TYP
MAX
UNITS
ISD = 56 A
−
−
1.25
V
trr
ISD = 56 A, dISD/dt = 100 A/ms
−
−
110
ns
QRR
ISD = 56 A, dISD/dt = 100 A/ms
−
−
320
nC
VSD
TEST CONDITIONS
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3
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3
1.2
60
1.0
50
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
TYPICAL PERFORMANCE CURVES
0.8
0.6
0.4
0.2
0
40
30
20
10
0
25
50
75
100
150
125
0
175
25
50
TC, CASE TEMPERATURE (5C)
75
100
125
150
175
TC, CASE TEMPERATURE (5C)
Figure 1. NORMALIZED POWER DISSIPATION vs
CASE TEMPERATURE
Figure 2. MAXIMUM CONTINUOUS DRAIN
CURRENT vs CASE TEMPERATURE
2
DUTY CYCLE − DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
ZqJC, NORMALIZED
THERMAL IMPEDANCE
1
PDM
0.1
t1
0.01
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZqJC x RqJC + TC
SINGLE PULSE
10−5
10−4
10−3
10−2
10−1
100
101
t, RECTANGULAR PULSE DURATION (s)
Figure 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
IDM, PEAK CURRENT (A)
1000
TC = 25oC
FOR TEMPERATURES
ABOVE 255C DERATE PEAK
CURRENT AS FOLLOWS:
I = I 25
100
175 − TC
150
VGS = 10V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10−5
10−4
10−3
10−2
10−1
t, PULSE WIDTH (s)
Figure 4. PEAK CURRENT CAPABILITY
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4
100
101
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
300 If R = 0
TJ = MAX RATED
TC = 25 oC
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
1000
100
100
100ms
10
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1
tAV = (L)(IAS)/(1.3yRATED BVDSS − VDD)
If R p 0
tAV = (L/R)ln[(IASyR)/(1.3yRATED BVDSS − VDD) +1]
1
10ms
VDSS(MAX)= 100V
10
STARTING TJ = 255C
STARTING TJ = 1505C
10
0.001
100 200
0.01
Figure 5. FORWARD BIAS SAFE OPERATING AREA
100
VGS = 6V
80
VGS = 20V
VGS = 10V
VGS = 7V
60
40
VGS = 5V
20
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
TC = 25 oC
0
1
0
2
3
4
5
60
40
20
25oC
0
7
6
0
3.0
4.5
6.0
7.5
Figure 8. TRANSFER CHARACTERISTICS
1.2
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
VGS = 10V, I D = 56A
NORMALIZED GATE
THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
1.5
−55oC
V GS , GATE TO SOURCE VOLTAGE (V)
Figure 7. SATURATION CHARACTERISTICS
2.5
175 oC
DUTY CYCLE
= 0.5%
MAX
PULSE
DURATION
= 80
ms
V DD= 15V
80
V DS, DRAIN TO SOURCE VOLTAGE (V)
3.0
1
Figure 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
100
0.1
tAV, TIME IN AVALANCHE (ms)
VDS, DRAIN TO SOURCE VOLTAGE (V)
2.0
1.5
1.0
VGS = VDS, ID = 250 mA
1.0
0.8
0.5
0
−80
−40
0
40
80
120
160
0.6
200
−80
TJ, JUNCTION TEMPERATURE (5C)
−40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (5C)
Figure 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
Figure 10. NORMALIZED GATE THRESHOLD VOLTAGE
vs JUNCTION TEMPERATURE
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5
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3
3000
1.2
C, CAPACITANCE (pF)
ID = 250 mA
1.1
1.0
VGS = 0 V, f = 1 MHz
CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
2500
2000
CISS
1500
1000
COSS
500
0.9
−80
−40
0
40
80
120
160
0
200
CRSS
0
10
TJ, JUNCTION TEMPERATURE (5C)
20
30
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 56A
ID = 37A
ID = 18A
2
V DD= 50V
0
10
50
60
Figure 12. CAPACITANCE vs DRAIN TO SOURCE
VOLTAGE
10
0
40
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 11. NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE vs JUNCTION
TEMPERATURE
VGS, GATE TO SOURCE VOLTAGE (V)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
20
30
40
50
60
Qg, GATE CHARGE (nC)
Figure 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
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6
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3
TEST CIRCUITS AND WAVEFORMS
VDS
BVDSS
L
tP
VARY t P TO OBTAIN
REQUIRED PEAK IAS
IAS
+
RG
−
VGS
VDS
VDD
VDD
DUT
tP
0V
IAS
0
0.01 W
tAV
Figure 14. UNCLAMPED ENERGY TEST CIRCUIT
Figure 15. UNCLAMPED ENERGY WAVEFORMS
VDS
VDD
RL
Qg(TOT)
VDS
VGS
Qg(10)
+
−
VGS = 20V
VDD
VGS = 10V
VGS
DUT
VGS = 2V
IG(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 17. GATE CHARGE WAVEFORM
Figure 16. GATE CHARGE TEST CIRCUIT
VDS
tON
tOFF
td(ON)
RL
VDS
tf
90%
90%
+
VGS
VDD
−
RGS
td(OFF)
tr
10%
0
10%
DUT
90%
VGS
VGS
0
Figure 18. SWITCHING TIME TEST CIRCUIT
10%
50%
PULSE WIDTH
50%
Figure 19. RESISTIVE SWITCHING WAVEFORMS
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7
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3
PSPICE Electrical Model
SUBCKT HUF75639 2 1 3 ;
rev Oct. 98
CA 12 8 2.8e−9
CB 15 14 2.65e−9
CIN 6 8 1.9e−9
RLGATE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.3e−2
RGATE 9 20 0.7
RSLC1 5 51 RSLCMOD 1e−6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 4.5e−3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
ESLC
11
−
LGATE
DBREAK
+
+
+
17
EBREAK 18
50
RDRAIN
6
8
EVTHRES
+ 19 −
8
EVTEMP
RGATE + 18 −
22
9
20
21
DBODY
−
16
MWEAK
6
MMED
MSTRO
LSOURCE
CIN
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
S1A
S1B
S2A
S2B
5
51
−
ESG
RLDRAIN
RSLC1
51
RSLC2
IT 8 17 1
RLGATE 1 9 10
RLDRAIN 2 5 20
RLSOURCE 3 7 4.69
DRAIN
2
5
10
EBREAK 11 7 17 18 110
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
LDRAIN 2 5 2e−9
LGATE 1 9 1e−9
GATE
LSOURCE 3 7 0.47e−9
1
LDRAIN
DPLCAP
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
8
7
RSOURCE
12
S1A
S2A
S1B
CA
17
18
RVTEMP
S2B
13
CB
6
8
EDS
VBAT
5
8
−
−
19
−
IT
14
+
+
EGS
RLSOURCE
RBREAK
15
14
13
13
8
SOURCE
3
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
+
8
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE = {(V(5,51)/ABS(V (5,51)))*(PWR(V(5,51)/(1e−6*115),4))}
.MODEL DBODYMOD D (IS = 1.4e−12 RS = 3.3e−3 XTI = 4.7 TRS1 = 2e−3 TRS2 = 0.1e−5 CJO = 3.3e−9 TT = 6.1e−8 M = 0.7)
.MODEL DBREAKMOD D (RS = 3.5e− 1TRS1 = 1e− 3TRS2 = 1e−6)
.MODEL DPLCAPMOD D (CJO = 2.2e− 9IS = 1e−3 0N = 10 M = 0.95 vj = 1.0)
.MODEL MMEDMOD NMOS (VTO = 3.5 KP = 4.8 IS = 1e−30 N = 10 TOX = 1 L = 1u W = 1u Rg = 0.7)
.MODEL MSTROMOD NMOS (VTO = 3.97 KP = 56.5 IS = 1e−30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO =3.11 KP = 0.085 IS = 1e−3
0 N = 10 TOX = 1 L = 1u W = 1u RG = 7 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 0.8e− 3TC2 = 1e−6)
.MODEL RDRAINMOD RES (TC1 = 1e−2 TC2 = 1.75e−5)
.MODEL RSLCMOD RES (TC1 = 2.8e−3 TC2 = 14e−6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC = −2.0e−3 TC2 = −1.75e−5)
.MODEL RVTEMPMOD RES (TC1 = −2.75e− 3TC2 = 0.05e−9)
.MODEL S1AMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = −6.0 VOFF = −3.5)
.MODEL S1BMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = −3.5 VOFF = −6.0)
.MODEL S2AMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = −2.5 VOFF = 4.95)
.MODEL S2AMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = 4.95 VOFF = −2.5)
.ENDS
NOTE:
For further discussion of the PSPICE model, consult A New PSPICE Sub−Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
www.onsemi.com
8
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3
SABER Electrical Model
nom temp=25 deg c 100v Ultrafet
REV Oct. 98
template huf75639 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is=1.4e−12, xti=4.7, cjo=33e−10,tt=6.1e−8, m=0.7) DPLCAP
d..model dbreakmod = ()
10
d..model dplcapmod = (cjo=22e−10,is=1e−30,n=10,m=0.95, vj=1.0)
m..model mmedmod = (type=_n,vto=3.5,kp=4.8,is=1e−30, tox=1)
m..model mstrongmod = (type=_n,vto=3.97,kp=56.5,is=1e−30, tox=1)
RSLC2
m..model mweakmod = (type=_n,vto=3.11,kp=0.085,is=1e−30, tox=1)
sw_vcsp..model s1amod = (ron=1e−5,roff=0.1,von=−6.0,voff=−3.5)
sw_vcsp..model s1bmod = (ron=1e−5,roff=0.1,von=−3.5,voff=−6.0)
sw_vcsp..model s2amod = (ron=1e−5,roff=0.1,von=−2.5,voff=4.95)
−
sw_vcsp..model s2bmod = (ron=1e−5,roff=0.1,von=4.95,voff=−2.5)
c.ca n12 n8 = 28.5e−10
c.cb n15 n14 = 26.5e−10
c.cin n6 n8 = 19e−10
ESG
+
LGATE
GATE
d.dbody n7 n71 = model=dbodymod
1
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
RLGATE
6
8
EVTEMP
RGATE + 18 −
22
9
20
DRAIN
2
RSLC1
51
72
RDRAIN
21
RDBODY
DBREAK
50
71
11
16
MWEAK
6
DBODY
EBREAK
+
17
18
MMED
MSTRO
CIN
l.ldrain n2 n5 = 2.0e−9
l.lgate n1 n9 = 1e−9
l.lsource n3 n7 = 4.69e−10
RLDRAIN
RDBREAK
ISCL
EVTHRES
+ 19 −
8
i.it n8 n17 = 1
−
8
LSOURCE
7
RSOURCE
12
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=0.8e−3,tc2=−1e−6
res.rdbody n71 n5 = 3.3e−3, tc1=2.0e−3, tc2=0.1e−5
res.rdbreak n72 n5 = 3.5e−1, tc1=1e−3, tc2=1e−6
res.rdrain n50 n16 = 13e−3, tc1=1e−2,tc2=1.75e−5
res.rgate n9 n20 = 0.7
res.rldrain n2 n5 = 20
res.rlgate n1 n9 = 10
res.rlsource n3 n7 = 4.69
res.rslc1 n5 n51 = 1e−6, tc1=2.8e−3,tc2=14e−6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 4.5e−3, tc1=0,tc2=0
res.rvtemp n18 n19 = 1, tc1=−2.75e−3,tc2=0.05e−9
res.rvthres n22 n8 = 1, tc1=−2e−3,tc2=−1.75e−5
LDRAIN
5
S1A
S2A
S1B
17
18
RVTEMP
S2B
13
CA
CB
6
8
EDS
−
19
−
IT
14
+
+
EGS
VBAT
5
8
−
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 110
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51−>n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e−9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/115))** 4))
}
}
www.onsemi.com
9
RLSOURCE
RBREAK
15
14
13
13
8
SOURCE
3
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3
Spice Thermal Model
TH
JUNCTION
REV APRIL 1998
HUF75639
CTHERM1 TH 6 2.8e−3
CTHERM2 6 5 4.6e−3
CTHERM3 5 4 5.5e−3
CTHERM4 4 3 9.2e−3
CTHERM5 3 2 1.7e−2
CTHERM6 2 TL 4.3e−2
RTHERM1
RTHERM1 TH 6 5.0e−4
RTHERM2 6 5 1.5e−3
RTHERM3 5 4 2.0e−2
RTHERM4 4 3 9.0e−2
RTHERM5 3 2 1.9e−1
RTHERM6 2 TL 2.9e−1
RTHERM2
CTHERM1
6
CTHERM2
5
RTHERM3
CTHERM3
Saber Thermal Model
Saber thermal model HUF75639
4
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 2.8e−3
ctherm.ctherm2 6 5 = 4.6e−3
ctherm.ctherm3 5 4 = 5.5e−3
ctherm.ctherm4 4 3 = 9.2e−3
ctherm.ctherm5 3 2 = 1.7e−2
ctherm.ctherm6 2 tl = 4.3e−2
CTHERM4
RTHERM4
3
RTHERM5
rtherm.rtherm1 th 6 = 5.0e−4
rtherm.rtherm2 6 5 = 1.5e−3
rtherm.rtherm3 5 4 = 2.0e−2
rtherm.rtherm4 4 3 = 9.0e−2
rtherm.rtherm5 3 2 = 1.9e−1
rtherm.rtherm6 2 tl = 2.9e−1
}
CTHERM5
2
RTHERM6
CTHERM6
TL
PSPICE is a trademark of MicroSim Corporation.
Saber is a registered trademark of Sabremark Limited Partnership.
www.onsemi.com
10
CASE
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3
PACKAGE DIMENSIONS
TO−247−3LD SHORT LEAD
CASE 340CK
ISSUE A
A
DATE 31 JAN 2019
A
E
P1
P
A2
D2
Q
E2
S
B
D
1
2
D1
E1
2
3
L1
A1
L
b4
c
(3X) b
0.25 M
(2X) b2
B A M
DIM
(2X) e
A
A1
A2
b
b2
b4
c
D
D1
D2
E
E1
E2
e
L
L1
P
P1
Q
S
GENERIC
MARKING DIAGRAM*
AYWWZZ
XXXXXXX
XXXXXXX
XXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW = Work Week
ZZ
= Assembly Lot Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
www.onsemi.com
11
MILLIMETERS
MIN NOM MAX
4.58 4.70 4.82
2.20 2.40 2.60
1.40 1.50 1.60
1.17 1.26 1.35
1.53 1.65 1.77
2.42 2.54 2.66
0.51 0.61 0.71
20.32 20.57 20.82
13.08
~
~
0.51 0.93 1.35
15.37 15.62 15.87
12.81
~
~
4.96 5.08 5.20
~
5.56
~
15.75 16.00 16.25
3.69 3.81 3.93
3.51 3.58 3.65
6.60 6.80 7.00
5.34 5.46 5.58
5.34 5.46 5.58
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3
TO−220−3LD
CASE 340AT
ISSUE A
Scale 1:1
www.onsemi.com
12
DATE 03 OCT 2017
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3
D2PAK−3 (TO−263, 3−LEAD)
CASE 418AJ
ISSUE E
SCALE 1:1
GENERIC MARKING DIAGRAMS*
XX
XXXXXXXXX
AWLYWWG
IC
XXXXXXXXG
AYWW
Standard
AYWW
XXXXXXXXG
AKA
Rectifier
XXXXXX
XXYMW
SSG
www.onsemi.com
13
DATE 25 OCT 2019
XXXXXX = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
Y
= Year
WW
= Work Week
W
= Week Code (SSG)
M
= Month Code (SSG)
G
= Pb−Free Package
AKA
= Polarity Indicator
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3
I2PAK (TO−262 3 LD)
CASE 418AV
ISSUE O
www.onsemi.com
14
DATE 30 SEP 2016
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
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