MOSFET – Power, N-Channel,
Ultrafet
100 V, 75 A, 8 mW
HUF75652G3
Features
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• Ultra Low On−Resistance
•
•
•
•
rDS(ON) = 0.008 W, VGS = 10 V
Simulation Models
♦ Temperature Compensated PSPICE™ and SABER™ Electrical
Models
♦ Spice and SABER Thermal Impedance Models
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Peak Current vs Pulse Width Curve
UIS Rating Curve
This Device is Pb−Free, Halogen Free/BFR Free and is RoHS
Compliant
♦
D
G
S
Packing
TO−247−3LD
CASE 340CK
MARKING DIAGRAMS
Figure 1.
$Y&Z&3&K
75652G
$Y
&Z
&3
&K
75652G
= ON Semiconductor Logo
= Assembly Plant Code
= Data Code (Year & Week)
= Lot
= Specific Device Code
ORDERING INFORMATION
© Semiconductor Components Industries, LLC, 2001
March, 2020 − Rev. 3
1
Part Number
Package
Brand
HUF75652G3
TO−247−3LD
75652G
Publication Order Number:
HUF75652G3/D
HUF75652G3
ABSOLUTE MAXIMUM RATINGS TC = 25°C unless otherwise specified
Symbol
Ratings
Units
Drain to Source Voltage (Note 1)
VDSS
100
V
Drain to Gate Voltage (RGS = 20 kW) (Note 1)
VDGR
100
V
VGS
+20
V
A
A
Description
Gate to Source Voltage
Drain Current
− Continuous (TC = 25°C, VGS = 10 V) (Figure 2)
− Continuous (TC = 100°C, VGS = 10 V) (Figure 2)
− Pulsed Drain Current
ID
ID
IDM
75
75
Figure 4
Pulsed Avalanche Rating
UIS
Figures 6
PD
515
3.44
W
W/°C
TJ, TSTG
−55 to 175
°C
TL
Tpkg
300
260
°C
°C
Power Dissipation
− Derate Above 25°C
Operating and Storage Temperature
Maximum Temperature for Soldering
− Leads at 0.063 in (1.6 mm) from Case for 10 s
− Package Body for 10 s, See Techbrief TB334
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. TJ = 25°C to 150°C.
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2
HUF75652G3
ELECTRICAL SPECIFICATIONS TC = 25°C unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
100
−
−
V
OFF STATE SPECIFICATIONS
BVDSS
IDSS
IGSS
Drain to Source Breakdown Voltage
ID = 250 mA, VGS = 0 V (Figure 11)
Zero Gate Voltage Drain Current
VDS = 95 V, VGS = 0 V
−
−
1
mA
VDS = 90 V, VGS = 0 V, TC = 150°C
−
−
250
mA
VGS = ±20 V
−
−
±100
nA
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
VGS(TH)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 mA (Figure 10)
2
−
4
V
rDS(ON)
Drain to Source On Resistance
ID = 75 A, VGS = 10 V (Figure 9)
−
0.0067
0.008
W
TO−247
−
−
0.29
°C/W
−
−
30
°C/W
−
−
320
ns
−
18.5
−
ns
Rise Time
−
195
−
ns
Turn−Off Delay Time
−
80
−
ns
Fall Time
−
190
−
ns
Turn−Off Time
−
−
410
ns
−
393
475
nC
−
211
255
nC
−
14
16.5
nC
THERMAL SPECIFICATIONS
RθJC
Thermal Resistance Junction to Case
RθJA
Thermal Resistance Junction to Ambient
SWITCHING SPECIFICATIONS (VGS = 10 V)
tON
td(ON)
tr
td(OFF)
tf
tOFF
Turn−On Time
Turn−On Delay Time
VDD = 50 V, ID ≅ 75 A, VGS = 10 V,
RGS = 2.0 W
GATE CHARGE SPECIFICATIONS
Total Gate Charge
VGS = 0 V to 20 V
Qg(10)
Gate Charge at 10 V
VGS = 0 V to 10 V
Qg(TH)
Threshold Gate Charge
VGS = 0 V to 2 V
Qg(TOT)
VDD = 50 V, ID = 75 A,
Ig(REF) = 1.0 mA
(Figures 13)
Qgs
Gate to Source Gate Charge
−
26
−
nC
Qgd
Gate to Drain “Miller” Charge
−
74
−
nC
−
7585
−
pF
−
2345
−
pF
−
630
−
pF
CAPACITANCE SPECIFICATIONS
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
VDS = 25 V, VGS = 0 V,
f = 1 MHz
(Figure 12)
SOURCE TO DRAIN DIODE SPECIFICATIONS
SYMBOL
VSD
trr
QRR
PARAMETER
MIN
TYP
MAX
UNITS
ISD = 75 A
−
−
1.25
V
ISD = 35 A
−
−
1.00
V
Reverse Recovery Time
ISD = 75 A, dISD/dt = 100 A/ms
−
−
150
ns
Reverse Recovered Charge
ISD = 75 A, dISD/dt = 100 A/ms
−
−
490
nC
Source to Drain Diode Voltage
TEST CONDITIONS
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3
HUF75652G3
TYPICAL PERFORMANCE CURVES
80
1.0
I D , DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
0.2
0
0
50
75
125
100
150
VGS = 10V
40
20
0
175
25
50
75
100
125
150
TC, CASE TEMPERATURE (5C)
TC, CASE TEMPERATURE (5C)
Figure 1. NORMALIZED POWER DISSIPATION vs
CASE TEMPERATURE
Figure 2. MAXIMUM CONTINUOUS DRAIN
CURRENT vs CASE TEMPERATURE
2
1
ZqJC, NORMALIZED
THERMAL IMPEDANCE
25
60
DUTY CYCLE − DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
0.1
PDM
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM y ZqJC y RqJC + TC
SINGLE PULSE
0.01
10−5
10−4
10−3
10−2
10−1
t1
t2
100
101
t, RECTANGULAR PULSE DURATION (s)
Figure 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
2000
IDM, PEAK CURRENT (A)
TC = 255C
FOR TEMPERATURES
ABOVE 255C DERATE PEAK
CURRENT AS FOLLOWS:
1000
VGS = 10V
VGS = 20V
I = I 25
175 − TC
150
TRANSCONDUCTANCE
100 MAY LIMIT CURRENT
IN THIS REGION
50
10−5
10−4
10−3
10−2
10−1
t, PULSE WIDTH (s)
Figure 4. PEAK CURRENT CAPABILITY
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4
100
101
175
HUF75652G3
TYPICAL PERFORMANCE CURVES (continued)
1000
100
100 ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10
1
10ms
SINGLE PULSE
TJ = MAX RATED
TC = 255C
DUTY CYCLE = 0.5% MAX
VDD = 15V
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
200
100
TJ = 1755C
TJ = 255C
50
TJ = −555C
0
2
150
VGS =5V
100
50
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
TC = 255C
0
3
4
5
VGS , GATE TO SOURCE VOLTAGE (V)
0
6
1
2
3
VDS , DRAIN TO SOURCE VOLTAGE (V)
4
Figure 8. SATURATION CHARACTERISTICS
1.2
PULSE DURATION = 80 ms
VGS = VDS, ID = 250 mA
DUTY CYCLE = 0.5% MAX
NORMALIZED GATE
THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
10
VGS = 7V
VGS = 6V
VGS = 20V
VGS = 10V
Figure 7. TRANSFER CHARACTERISTICS
2.5
0.1
1
tAV , TIME IN AVALANCHE (ms)
Figure 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
PULSE DURATION = 80 ms
150
STARTING TJ = 1505C
10
0.01
500
Figure 5. FORWARD BIAS SAFE OPERATING AREA
200
STARTING TJ = 255C
100
1ms
100
10
VDS , DRAIN TO SOURCE VOLTAGE (V)
1
If R = 0
tAV = (L)(IAS)/(1.3yRATED BVDSS − VDD)
If R 0 0
tAV = (L/R)ln[(IASyR)/(1.3yRATED BVDSS − VDD) +1]
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
1000
2.0
1.5
1.0
1.0
0.8
0.6
VGS = 10V, I D = 75A
0.5
−80
−40
0
40
80
120
160
0.4
−80
200
TJ, JUNCTION TEMPERATURE (5C)
−40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (5C)
Figure 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATU
Figure 10. NORMALIZED GATE THRESHOLD VOLTAGE
vs JUNCTION TEMPERATURE
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HUF75652G3
TYPICAL PERFORMANCE CURVES (continued)
20000
ID = 250 mA
CISS = CGS + CGD
C, CAPACITANCE (pF)
10000
1.1
1.0
0.9
−80
CRSS = CGD
1000
COSS ^ CDS + CGD
VGS = 0V, f = 1MHz
−40
0
40
80
120
100
0.1
200
160
Figure 11. NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE vs JUNCTION
TEMPERATURE
10
1.0
10
Figure 12. CAPACITANCE vs DRAIN TO SOURCE
VOLTAGE
VDD = 50V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 75A
ID = 35A
2
0
0
100
VDS , DRAIN TO SOURCE VOLTAGE (V)
TJ, JUNCTION TEMPERATURE (5C)
VGS , GATE TO SOURCE VOLTAGE (V)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.2
50
100
150
Qg, GATE CHARGE (nC)
200
250
Figure 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
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HUF75652G3
TEST CIRCUITS AND WAVEFORMS
VDS
BVDSS
L
tP
VARY t P TO OBTAIN
REQUIRED PEAK IAS
IAS
+
RG
−
VGS
VDS
VDD
VDD
DUT
tP
0V
IAS
0
0.01 W
tAV
Figure 14. UNCLAMPED ENERGY TEST CIRCUIT
Figure 15. UNCLAMPED ENERGY WAVEFORMS
VDS
VDD
RL
Qg(TOT)
VDS
VGS
Qg(10)
+
−
VGS = 20V
VDD
VGS = 10V
VGS
DUT
VGS = 2V
IG(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 17. GATE CHARGE WAVEFORM
Figure 16. GATE CHARGE TEST CIRCUIT
VDS
tON
tOFF
td(ON)
RL
VDS
tf
90%
90%
+
VGS
VDD
−
RGS
td(OFF)
tr
10%
0
10%
DUT
90%
VGS
VGS
0
Figure 18. SWITCHING TIME TEST CIRCUIT
50%
10%
PULSE WIDTH
50%
Figure 19. SWITCHING TIME WAVEFORM
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HUF75652G3
PSPICE Electrical Model
.SUBCKT HUF75652 2 1 3 ;
rev 11 May 1999
CA 12 8 11.0e−9
CB 15 14 11.4e−9
CIN 6 8 6.95e−9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
LDRAIN
DPLCAP
DRAIN
2
5
10
EBREAK 11 7 17 18 117.5
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
RSLC2
−
+
GATE
1
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 2.80e−3
RGATE 9 20 0.85
RLDRAIN 2 5 10
RLGATE 1 9 57.4
RLSOURCE 3 7 46.5
RSLC1 5 51 RSLCMOD 1e−6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 2.50e−3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
+
ESG
LGATE
RLGATE
11
+
17
EBREAK 18
50
−
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
S1A
S1B
S2A
S2B
DBREAK
ESLC
IT 8 17 1
LDRAIN 2 5 1.0e−9
LGATE 1 9 5.74e−9
LSOURCE 3 7 4.65e−9
RLDRAIN
RSLC1
51
RDRAIN
6
8
EVTHRES
+ 19 −
8
EVTEMP
RGATE + 18 −
22
9
20
21
DBODY
−
16
MWEAK
6
MMED
MSTRO
LSOURCE
CIN
8
7
RSOURCE
12
S2A
S1A
14
13
13
8
S1B
CA
17
18
RVTEMP
CB
6
8
EDS
−
19
−
IT
14
+
+
EGS
RLSOURCE
RBREAK
15
S2B
13
SOURCE
3
VBAT
5
8
−
+
8
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51) /ABS(V(5,51)))*(PWR(V(5,51)/(1e−6*455),2))}
.MODEL DBODYMOD D (IS = 6.55e−12 IKF = 30 RS = 1.69e−3 TRS1
= 1.95e−3 TRS2 = 1.05e−6 CJO = 8.71e−9 TT = 7.81e−8 M = 0.50)
.MODEL DBREAKMOD D (RS = 1.45e− 1TRS1 = 1.02e− 4TRS2 = 1.11e−7)
.MODEL DPLCAPMOD D (CJO = 1.00e− 8IS = 1e−3 0N = 1 M = 0.85)
.MODEL MMEDMOD NMOS (VTO = 2.91 KP = 6.50 IS = 1e−30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.85)
.MODEL MSTROMOD NMOS (VTO = 3.37 KP = 205 IS = 1e−30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.56 KP = 0.10 IS = 1e−30 N = 10 TOX = 1 L = 1u W = 1u RG = 8.5 )
.MODEL RBREAKMOD RES (TC1 = 1.09e− 3TC2 = 1.04e−7)
.MODEL RDRAINMOD RES (TC1 = 1.38e−2 TC2 = 3.75e−5)
.MODEL RSLCMOD RES (TC1 = 1.05e−4 TC2 = 2.13e−7)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = −2.92e−3 TC2 = −1.48e−5)
.MODEL RVTEMPMOD RES (TC1 = −3.0e− 3TC2 = 1.21e−6)
.MODEL S1AMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = −5.0 VOFF= −3.0)
.MODEL S1BMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = −3.0 VOFF= −5.0)
.MODEL S2AMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = −2.0 VOFF= 0.0)
.MODEL S2BMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = 0.0 VOFF= −2.0)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub−Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank W heatley.
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8
HUF75652G3
SABER Electrical Model
REV 11 May 1999
template ta75652 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 6.55e−12, cjo = 8.71e−9, tt = 7.81e−8, m = 0.50)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 1.0e−8, is = 1e−30, n=1, m = 0.85 )
m..model mmedmod = (type=_n, vto = 2.91, kp = 6.5, is = 1e−30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.37, kp = 205, is = 1e−30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.56, kp = 0.1, is = 1e−30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e−5, roff = 0.1, von = −5, voff = −3)
DPLCAP
sw_vcsp..model s1bmod = (ron =1e−5, roff = 0.1, von = −3, voff = −5)
10
sw_vcsp..model s2amod = (ron = 1e−5, roff = 0.1, von = −2, voff = 0)
sw_vcsp..model s2bmod = (ron = 1e−5, roff = 0.1, von = 0, voff = −2)
c.ca n12 n8 = 11.0e−9
c.cb n15 n14 = 11.4e−9
c.cin n6 n8 = 6.95e−9
RSLC1
51
RSLC2
RLDRAIN
72
ESG
+
i.it n8 n17 = 1
GATE
1
LGATE
RLGATE
RDRAIN
6
8
EVTEMP
RGATE + 18 −
22
9
20
6
MWEAK
DBODY
EBREAK
+
17
18
MMED
MSTRO
CIN
71
11
EVTHRES
16
+ 19 − 21
8
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
RDBODY
DBREAK
50
−
−
8
LSOURCE
7
RSOURCE
res.rbreak n17 n18 = 1, tc1 = 1.09e−3, tc2 = 1.04e−7
res.rdbody n71 n5 = 1.69e−3, tc1 = 1.95e−3, tc2 = 1.05e−6
res.rdbreak n72 n5 = 1.45e−1, tc1 = 1.02e−4, tc2 = 1.11e−7
res.rdrain n50 n16 = 2.80e−3, tc1 = 1.38e−2, tc2 = 3.75e−5
res.rgate n9 n20 = 0.85
CA
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 57.4
res.rlsource n3 n7 = 46.5
res.rslc1 n5 n51 = 1e−6, tc1 = 1.05e−4, tc2 = 2.13e−7
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 2.50e−3, tc1 = 0, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = −3.0e−3, tc2 = 1.21e−6
res.rvthres n22 n8 = 1, tc1 = −2.92e−3, tc2 = −1.48e−5
S1A
12
13
8
S2A
14
13
S1B
15
17
RBREAK
CB
+
+
EGS
6
8
EDS
−
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51−>n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e−9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/455))** 2))
}
}
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9
18
19
−
IT
14
5
8
−
+
8
RVTHRES
spe.ebreak n11 n7 n17 n18 = 117.5
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
RLSOURCE
RVTEMP
S2B
13
DRAIN
2
RDBREAK
ISCL
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
l.ldrain n2 n5 = 1e−9
l.lgate n1 n9 = 5.74e−9
l.lsource n3 n7 = 4.65e−9
LDRAIN
5
22
VBAT
SOURCE
3
HUF75652G3
SPICE Thermal Model
th
JUNCTION
REV 1April 1999
HUF75652T
CTHERM1 th 6 9.75e−3
CTHERM2 6 5 3.90e−2
CTHERM3 5 4 2.50e−2
CTHERM4 4 3 2.95e−2
CTHERM5 3 2 6.55e−2
CTHERM6 2 tl 12.55
RTHERM1
RTHERM1 th 6 1.96e−3
RTHERM2 6 5 4.89e−3
RTHERM3 5 4 1.38e−2
RTHERM4 4 3 7.73e−2
RTHERM5 3 2 1.17e−1
RTHERM6 2 tl 1.55e−2
RTHERM2
CTHERM1
6
CTHERM2
5
CTHERM3
RTHERM3
SABER Thermal Model
SABER thermal model HUF75652T
4
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 9.75e−3
ctherm.ctherm2 6 5 = 3.90e−2
ctherm.ctherm3 5 4 = 2.50e−2
ctherm.ctherm4 4 3 = 2.95e−2
ctherm.ctherm5 3 2 = 6.55e−2
ctherm.ctherm6 2 tl = 12.55
CTHERM4
RTHERM4
3
CTHERM5
RTHERM5
rtherm.rtherm1 th 6 = 1.96e−3
rtherm.rtherm2 6 5 = 4.89e−3
rtherm.rtherm3 5 4 = 1.38e−2
rtherm.rtherm4 4 3 = 7.73e−2
rtherm.rtherm5 3 2 = 1.17e−1
rtherm.rtherm6 2 tl = 1.55e−2
}
2
CTHERM6
RTHERM6
tl
PSPICE is a trademark of MicroSim Corporation.
Saber is a registered trademark of Sabremark Limited Partnership.
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10
CASE
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−247−3LD SHORT LEAD
CASE 340CK
ISSUE A
A
DATE 31 JAN 2019
A
E
P1
P
A2
D2
Q
E2
S
B
D
1
2
D1
E1
2
3
L1
A1
L
b4
c
(3X) b
0.25 M
(2X) b2
B A M
DIM
(2X) e
GENERIC
MARKING DIAGRAM*
AYWWZZ
XXXXXXX
XXXXXXX
XXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW = Work Week
ZZ
= Assembly Lot Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13851G
TO−247−3LD SHORT LEAD
A
A1
A2
b
b2
b4
c
D
D1
D2
E
E1
E2
e
L
L1
P
P1
Q
S
MILLIMETERS
MIN NOM MAX
4.58 4.70 4.82
2.20 2.40 2.60
1.40 1.50 1.60
1.17 1.26 1.35
1.53 1.65 1.77
2.42 2.54 2.66
0.51 0.61 0.71
20.32 20.57 20.82
13.08
~
~
0.51 0.93 1.35
15.37 15.62 15.87
12.81
~
~
4.96 5.08 5.20
~
5.56
~
15.75 16.00 16.25
3.69 3.81 3.93
3.51 3.58 3.65
6.60 6.80 7.00
5.34 5.46 5.58
5.34 5.46 5.58
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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