HUF76423D3, HUF76423D3S
Data Sheet
December 2001
20A, 60V, 0.037 Ohm, N-Channel, Logic
Level UltraFET® Power MOSFETFairchild
Packaging
JEDEC TO-251AA
DRAIN
(FLANGE)
JEDEC TO-252AA
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
GATE
SOURCE
HUF76423D3S
HUF76423D3
Features
• Ultra Low On-Resistance
- rDS(ON) = 0.032Ω, VGS = 10V
- rDS(ON) = 0.037Ω, VGS = 5V
• Simulation Models
- Temperature Compensated PSPICE® and SABER™
Electrical Models
- Spice and SABER Thermal Impedance Models
- www.fairchildsemi.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Symbol
• Switching Time vs RGS Curves
D
Ordering Information
PART NUMBER
G
S
Absolute Maximum Ratings
PACKAGE
BRAND
HUF76423D3
TO-251AA
76423D
HUF76423D3S
TO-252AA
76423D
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76423D3ST.
TC = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (TC = 25oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC = 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC = 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC = 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and StorageTemperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
NOTES:
HUF76423D3,
HUF76423D3S
60
UNITS
V
60
V
±16
V
20
20
20
20
Figure 4
Figures 6, 17, 18
85
0.567
A
A
A
A
W
W/oC
-55 to 175
oC
300
260
oC
oC
1. TJ = 25oC to 150oC.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Automotive HUFA series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUF76423D3, HUF76423D3S Rev. B
HUF76423D3, HUF76423D3S
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ID = 250µA, VGS = 0V (Figure 12)
60
-
-
V
ID = 250µA, VGS = 0V , T C = -40oC (Figure 12)
55
-
-
V
-
-
1
µA
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
BVDSS
IDSS
IGSS
VDS = 55V, VGS = 0V
VDS = 50V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = ±16V
-
-
±100
nA
VGS = VDS, ID = 250µA (Figure 11)
1
-
3
V
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
Drain to Source On Resistance
rDS(ON)
ID = 20A, VGS = 10V (Figures 9, 10)
-
0.027
0.032
Ω
ID = 20A, VGS = 5V (Figure 9)
-
0.031
0.037
Ω
ID = 20A, VGS = 4.5V (Figure 9)
-
0.033
0.040
Ω
TO-251 and TO-252
-
-
1.76
oC/W
-
-
100
oC/W
-
-
240
ns
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
RθJC
Thermal Resistance Junction to
Ambient
RθJA
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn-On Time
Turn-On Delay Time
tON
-
12
-
ns
tr
-
145
-
ns
td(OFF)
-
27
-
ns
tf
-
50
-
ns
tOFF
-
-
120
ns
-
-
65
ns
-
7
-
ns
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDD = 30V, ID = 20A
VGS = 4.5V, RGS = 10Ω
(Figures 15, 21, 22)
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
Turn-On Delay Time
Rise Time
tON
td(ON)
-
35
-
ns
td(OFF)
-
52
-
ns
tf
-
50
-
ns
tOFF
-
-
155
ns
-
28
34
nC
tr
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDD = 30V, ID = 20A
VGS = 10V,
RGS = 10Ω
(Figures 16, 21, 22)
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Gate Charge at 5V
Threshold Gate Charge
Qg(TOT)
VGS = 0V to 10V
Qg(5)
VGS = 0V to 5V
Qg(TH)
VGS = 0V to 1V
VDD = 30V,
ID = 20A,
Ig(REF) = 1.0mA
(Figures 14, 19, 20)
-
16
20
nC
-
1.2
1.5
nC
Gate to Source Gate Charge
Qgs
-
3.5
-
nC
Gate to Drain “Miller” Charge
Qgd
-
7
-
nC
-
1060
-
pF
-
315
-
pF
-
65
-
pF
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 13)
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
©2001 Fairchild Semiconductor Corporation
SYMBOL
VSD
MIN
TYP
MAX
UNITS
ISD = 20A
TEST CONDITIONS
-
-
1.25
V
ISD = 10A
-
-
1.0
V
trr
ISD = 20A, dISD/dt = 100A/µs
-
-
90
ns
QRR
ISD = 20A, dISD/dt = 100A/µs
-
-
225
nC
HUF76423D3, HUF76423D3S Rev. B
HUF76423D3, HUF76423D3S
Typical Performance Curves
25
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
0.2
VGS = 10V
20
VGS = 4.5V
15
10
5
0
0
0
25
50
75
100
125
150
175
25
50
TC , CASE TEMPERATURE (oC)
75
100
125
150
175
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10 -5
10 -4
10-3
10 -2
10 -1
10 0
10 1
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
IDM, PEAK CURRENT (A)
500
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
I = I25
100
175 - TC
150
VGS = 10V
VGS = 5V
10
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10-5
10-4
10-3
10-2
t, PULSE WIDTH (s)
10-1
100
101
FIGURE 4. PEAK CURRENT CAPABILITY
©2001 Fairchild Semiconductor Corporation
HUF76423D3, HUF76423D3S Rev. B
HUF76423D3, HUF76423D3S
Typical Performance Curves
(Continued)
200
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
300
100
100µs
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10
1ms
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
1
1
10ms
10
STARTING TJ = 25oC
10
STARTING TJ = 150oC
1
0.01
0.1
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
100
10
tAV, TIME IN AVALANCHE (ms)
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
60
60
ID, DRAIN CURRENT (A)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
50
40
30
20
TJ = 175oC
TJ = 25oC
10
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
VGS = 10V
VGS = 5V
50
VGS = 4V
40
30
VGS = 3.5V
20
VGS = 3V
10
TJ = -55oC
0
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
1
VGS, GATE TO SOURCE VOLTAGE (V)
2
3
4
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
50
2.5
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
1
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
ID, DRAIN CURRENT (A)
100
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
40
ID = 20A
ID = 10A
30
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 20A
2.0
1.5
1.0
0.5
20
2
4
6
8
10
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
©2001 Fairchild Semiconductor Corporation
-80
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
HUF76423D3, HUF76423D3S Rev. B
HUF76423D3, HUF76423D3S
Typical Performance Curves
(Continued)
1.2
1.2
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
1.0
0.8
0.6
ID = 250µA
1.1
1.0
0.9
0.4
-80
-40
0
40
80
120
160
-80
200
-40
TJ, JUNCTION TEMPERATURE (oC)
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
VGS , GATE TO SOURCE VOLTAGE (V)
10
3000
C, CAPACITANCE (pF)
CISS = CGS + CGD
1000
COSS ≅ CDS + CGD
100
CRSS = CGD
VGS = 0V, f = 1MHz
20
VDD = 30V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 20A
ID = 10A
2
0
5
0
0.1
1
10
10
60
VDS , DRAIN TO SOURCE VOLTAGE (V)
15
20
25
30
Qg, GATE CHARGE (nC)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
200
350
VGS = 10V, VDD = 30V, ID = 20A
VGS = 4.5V, VDD = 30V, ID = 20A
tr
SWITCHING TIME (ns)
SWITCHING TIME (ns)
300
250
200
150
tf
td(OFF)
100
150
td(OFF)
tf
100
tr
50
50
td(ON)
td(ON)
0
0
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
©2001 Fairchild Semiconductor Corporation
50
0
10
20
30
40
50
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
HUF76423D3, HUF76423D3S Rev. B
HUF76423D3, HUF76423D3S
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10V
VGS
Qg(5)
+
VDD
VGS = 5V
VGS
DUT
VGS = 1V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON
tOFF
td(ON)
td(OFF)
tr
RL
VDS
tf
90%
90%
+
VGS
VDD
-
10%
0
10%
DUT
90%
RGS
VGS
VGS
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT
©2001 Fairchild Semiconductor Corporation
10%
50%
50%
PULSE WIDTH
FIGURE 22. SWITCHING TIME WAVEFORM
HUF76423D3, HUF76423D3S Rev. B
HUF76423D3, HUF76423D3S
PSPICE Electrical Model
.SUBCKT HUF76423 2 1 3 ;
rev 7 September 1999
CA 12 8 1.46e-9
CB 15 14 1.46e-9
CIN 6 8 1.0e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
LDRAIN
DPLCAP
DRAIN
2
5
10
5
51
ESLC
11
-
RDRAIN
6
8
EVTHRES
+ 19 8
+
LGATE
GATE
1
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
+
50
-
IT 8 17 1
EVTEMP
RGATE + 18 22
9
20
21
EBREAK
17
18
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 7.0e-3
RGATE 9 20 3.6
RLDRAIN 2 5 10
RLGATE 1 9 55
RLSOURCE 3 7 44
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 1.45e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
DBREAK
+
RSLC2
ESG
LDRAIN 2 5 1e-9
LGATE 1 9 5.5e-9
LSOURCE 3 7 4.4e-9
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 66.0
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
RLSOURCE
S1A
12
S2A
13
8
14
13
S1B
CA
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
-
IT
14
+
+
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
RBREAK
15
VBAT
5
8
EDS
-
+
8
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*100),3.5))}
.MODEL DBODYMOD D (IS = 6.3e-13 RS = 6.8e-3 TRS1 = 1e-3 TRS2 = 1e-6 XTI = 4.3 CJO = 1.28e-9 TT = 5.1e-8 M = 0.5)
.MODEL DBREAKMOD D (RS = 2.9e- 1TRS1 = 1e- 4TRS2 = 0)
.MODEL DPLCAPMOD D (CJO = 9.5e-1 0IS = 1e-3 0N = 10 M = 0.82)
.MODEL MMEDMOD NMOS (VTO = 2.10 KP = 6 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.6)
.MODEL MSTROMOD NMOS (VTO = 2.45 KP = 60.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.79 KP = 0.13 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 36 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.2e- 3TC2 = -5e-7)
.MODEL RDRAINMOD RES (TC1 = 1.3e-2 TC2 = 3.1e-5)
.MODEL RSLCMOD RES (TC1 = 5.5e-3 TC2 = 7e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.8e-3 TC2 = -5.8e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.7e- 3TC2 = 8e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -4.8 VOFF= -2.8)
VON = -2.8 VOFF= -4.8)
VON = -0.6 VOFF= 0.5)
VON = 0.5 VOFF= -0.6)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2001 Fairchild Semiconductor Corporation
HUF76423D3, HUF76423D3S Rev. B
HUF76423D3, HUF76423D3S
SABER Electrical Model
REV 7 September 1999
template huf76423 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 6.3e-13, xti = 4.3, cjo = 1.28e-9, tt = 5.1e-8, m = 0.50)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 9.5e-10, is = 1e-30, n = 10, m = 0.82 )
m..model mmedmod = (type=_n, vto = 2.10, kp = 6, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.45, kp = 60.5, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.79, kp = 0.13, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.8, voff = -2.8)
DPLCAP
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.8, voff = -4.8)
10
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.6, voff = 0.5)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -0.6)
c.ca n12 n8 = 1.46e-9
c.cb n15 n14 = 1.46e-9
c.cin n6 n8 = 1.0e-9
DRAIN
2
RSLC1
51
RLDRAIN
RDBREAK
RSLC2
72
ISCL
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
i.it n8 n17 = 1
LGATE
GATE
1
EVTEMP
RGATE + 18 22
9
20
MWEAK
MSTRO
CIN
DBODY
EBREAK
+
17
18
MMED
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
71
11
16
6
RLGATE
res.rbreak n17 n18 = 1, tc1 = 1.2e-3, tc2 = -5.0e-7
res.rdbody n71 n5 = 6.8e-3, tc1 = 1e-3, tc2 = 1e-6
res.rdbreak n72 n5 = 2.9e-1, tc1 = 1e-4, tc2 = 0
res.rdrain n50 n16 = 7.0e-3, tc1 = 1.3e-2, tc2 = 3.1e-5
res.rgate n9 n20 = 3.6
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 55
res.rlsource n3 n7 = 44
res.rslc1 n5 n51 = 1e-6, tc1 = 5.5e-3, tc2 = 7.0e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 1.45e-2, tc1 = 1e-3, tc2 = 1e-6
res.rvtemp n18 n19 = 1, tc1 = -1.7e-3, tc2 = 8.0e-7
res.rvthres n22 n8 = 1, tc1 = -1.8e-3, tc2 = -5.8e-6
21
RDBODY
DBREAK
50
-
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
l.ldrain n2 n5 = 1.0e-9
l.lgate n1 n9 = 5.5e-9
l.lsource n3 n7 = 4.4e-9
LDRAIN
5
-
8
LSOURCE
7
SOURCE
3
RSOURCE
RLSOURCE
S1A
12
S2A
14
13
13
8
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
+
6
8
EGS
19
CB
+
-
-
IT
14
VBAT
5
8
EDS
-
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 66.0
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/100))** 3.5))
}
}
©2001 Fairchild Semiconductor Corporation
HUF76423D3, HUF76423D3S Rev. B
HUF76423D3, HUF76423D3S
SPICE Thermal Model
th
JUNCTION
REV 1 September 1999
HUF76423T
CTHERM1 th 6 1.40e-3
CTHERM2 6 5 8.30e-3
CTHERM3 5 4 7.00e-3
CTHERM4 4 3 3.20e-3
CTHERM5 3 2 1.50e-2
CTHERM6 2 tl 1.10
RTHERM1
RTHERM1 th 6 1.20e-2
RTHERM2 6 5 2.99e-2
RTHERM3 5 4 8.43e-2
RTHERM4 4 3 4.73e-1
RTHERM5 3 2 7.14e-1
RTHERM6 2 tl 9.47e-2
RTHERM2
CTHERM1
6
CTHERM2
5
CTHERM3
RTHERM3
SABER Thermal Model
SABER thermal model HUF76423T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 1.40e-3
ctherm.ctherm2 6 5 = 8.30e-3
ctherm.ctherm3 5 4 = 7.00e-3
ctherm.ctherm4 4 3 = 3.20e-3
ctherm.ctherm5 3 2 = 1.50e-2
ctherm.ctherm6 2 tl = 1.10
rtherm.rtherm1 th 6 = 1.20e-2
rtherm.rtherm2 6 5 = 2.99e-2
rtherm.rtherm3 5 4 = 8.43e-2
rtherm.rtherm4 4 3 = 4.73e-1
rtherm.rtherm5 3 2 = 7.14e-1
rtherm.rtherm6 2 tl = 9.47e-2
}
4
CTHERM4
RTHERM4
3
CTHERM5
RTHERM5
2
CTHERM6
RTHERM6
tl
©2001 Fairchild Semiconductor Corporation
CASE
HUF76423D3, HUF76423D3S Rev. B
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Rev. H4
