HUFA75652G3
Data Sheet
December 2001
75A, 100V, 0.008 Ohm, N-Channel
UltraFET® Power MOSFET
Packaging
JEDEC TO-247
SOURCE
DRAIN
GATE
DRAIN
(TAB)
HUFA75652G3
Features
• Ultra Low On-Resistance
- rDS(ON) = 0.008Ω, VGS = 10V
• Simulation Models
- Temperature Compensated PSPICE® and SABER™
Electrical Models
- Spice and SABER Thermal Impedance Models
- www.fairchildsemi.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Symbol
D
Ordering Information
PART NUMBER
HUFA75652G3
G
PACKAGE
TO-247
BRAND
75652G
NOTE: When ordering, use the entire part number.
S
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
HUFA75652G3
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
100
V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
100
V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
±20
V
Drain Current
Continuous (TC = 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC = 100oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
75
75
Figure 4
A
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS
Figure 6
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
515
3.44
W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
-55 to 175
oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
300
260
oC
oC
NOTES:
1. TJ = 25oC to 150oC.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy
of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUFA75652G3 Rev. B
HUFA75652G3
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
100
-
-
V
VDS = 95V, VGS = 0V
-
-
1
µA
VDS = 90V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = ±20V
-
-
±100
nA
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
BVDSS
IDSS
IGSS
ID = 250µA, VGS = 0V (Figure 11)
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 10)
2
-
4
V
Drain to Source On Resistance
rDS(ON)
ID = 75A, VGS = 10V (Figures 9)
-
0.0067
0.008
Ω
TO-247
-
-
0.29
oC/W
-
-
30
oC/W
-
-
320
ns
td(ON)
-
18.5
-
ns
tr
-
195
-
ns
td(OFF)
-
80
-
ns
tf
-
190
-
ns
tOFF
-
-
410
ns
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
RθJC
Thermal Resistance Junction to
Ambient
RθJA
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
tON
VDD = 50V, ID = 75A, VGS = 10V, RGS = 2.0Ω
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Qg(TOT)
VGS = 0V to 20V
Gate Charge at 10V
Qg(10)
VGS = 0V to 10V
Threshold Gate Charge
Qg(TH)
VGS = 0V to 2V
VDD = 50V,
ID = 75A,
Ig(REF) = 1.0mA
-
393
475
nC
-
211
255
nC
(Figure 13)
-
14
16.5
nC
Gate to Source Gate Charge
Qgs
-
26
-
nC
Gate to Drain “Miller” Charge
Qgd
-
74
-
nC
-
7585
-
pF
-
2345
-
pF
-
630
-
pF
MIN
TYP
MAX
UNITS
ISD = 75A
-
-
1.25
V
ISD = 35A
-
-
1.00
V
trr
ISD = 75A, dISD/dt = 100A/µs
-
-
150
ns
QRR
ISD = 75A, dISD/dt = 100A/µs
-
-
490
nC
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 12)
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
©2001 Fairchild Semiconductor Corporation
SYMBOL
VSD
TEST CONDITIONS
HUFA75652G3 Rev. B
HUFA75652G3
Typical Performance Curves
80
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
60
VGS = 10V
40
20
0.2
0
0
25
50
75
100
0
150
125
175
25
50
75
TC , CASE TEMPERATURE (oC)
100
125
150
175
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
IDM, PEAK CURRENT (A)
2000
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
1000
VGS = 10V
VGS = 20V
175 - TC
I = I25
150
100
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
50
10-5
10-4
10-3
10-2
10-1
100
101
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
©2001 Fairchild Semiconductor Corporation
HUFA75652G3 Rev. B
HUFA75652G3
Typical Performance Curves
(Continued)
1000
100
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
1000
100µs
STARTING TJ = 25oC
100
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10
10ms
SINGLE PULSE
T J = MAX RATED
T C = 25 oC
1
1
10
100
STARTING TJ = 150oC
10
0.01
500
0.1
1
tAV, TIME IN AVALANCHE (ms)
VDS , DRAIN TO SOURCE VOLTAGE (V)
10
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
200
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
150
100
TJ = 175oC
50
TJ = 25oC
150
2
VGS =5V
100
50
TJ = -55oC
0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
0
3
4
5
VGS, GATE TO SOURCE VOLTAGE (V)
0
6
FIGURE 7. TRANSFER CHARACTERISTICS
4
1
2
3
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 8. SATURATION CHARACTERISTICS
2.5
1.2
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = VDS, ID = 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
VGS = 7V
VGS = 6V
VGS = 20V
VGS = 10V
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
200
2.0
1.5
1.0
1.0
0.8
0.6
VGS = 10V, ID = 75A
0.4
0.5
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
200
-80
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
HUFA75652G3 Rev. B
HUFA75652G3
Typical Performance Curves
(Continued)
20000
ID = 250µA
CISS = CGS + CGD
10000
C, CAPACITANCE (pF)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.2
1.1
1.0
CRSS = CGD
1000
COSS ≅ CDS + CGD
VGS = 0V, f = 1MHz
0.9
-80
-40
0
40
80
120
160
200
100
0.1
1.0
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
VGS , GATE TO SOURCE VOLTAGE (V)
10
10
100
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VDD = 50V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 75A
ID = 35A
2
0
0
50
100
150
Qg, GATE CHARGE (nC)
200
250
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
©2001 Fairchild Semiconductor Corporation
HUFA75652G3 Rev. B
HUFA75652G3
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
IAS
+
RG
VDS
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 20V
VGS
Qg(10)
+
VDD
VGS = 10V
VGS
DUT
VGS = 2V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
VDS
tON
tOFF
td(ON)
td(OFF)
tr
RL
VDS
tf
90%
90%
+
VGS
VDD
-
10%
0
10%
DUT
90%
RGS
VGS
VGS
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT
©2001 Fairchild Semiconductor Corporation
10%
50%
50%
PULSE WIDTH
FIGURE 19. SWITCHING TIME WAVEFORM
HUFA75652G3 Rev. B
HUFA75652G3
PSPICE Electrical Model
.SUBCKT HUFA75652 2 1 3 ;
rev 11 May 1999
CA 12 8 11.0e-9
CB 15 14 11.4e-9
CIN 6 8 6.95e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
LDRAIN
DPLCAP
DRAIN
2
5
10
5
51
ESLC
11
-
RDRAIN
6
8
EVTHRES
+ 19 8
+
LGATE
GATE
1
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
+
50
-
IT 8 17 1
EVTEMP
RGATE + 18 22
9
20
21
EBREAK
17
18
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 2.80e-3
RGATE 9 20 0.85
RLDRAIN 2 5 10
RLGATE 1 9 57.4
RLSOURCE 3 7 46.5
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 2.50e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
DBREAK
+
RSLC2
ESG
LDRAIN 2 5 1.0e-9
LGATE 1 9 5.74e-9
LSOURCE 3 7 4.65e-9
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 117.5
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
RLSOURCE
S1A
12
S2A
13
8
14
13
S1B
CA
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
-
IT
14
+
+
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
RBREAK
15
VBAT
5
8
EDS
-
+
8
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*455),2))}
.MODEL DBODYMOD D (IS = 6.55e-12 IKF = 30 RS = 1.69e-3 TRS1 = 1.95e-3 TRS2 = 1.05e-6 CJO = 8.71e-9 TT = 7.81e-8 M = 0.50)
.MODEL DBREAKMOD D (RS = 1.45e- 1TRS1 = 1.02e- 4TRS2 = 1.11e-7)
.MODEL DPLCAPMOD D (CJO = 1.00e- 8IS = 1e-3 0N = 1 M = 0.85)
.MODEL MMEDMOD NMOS (VTO = 2.91 KP = 6.50 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.85)
.MODEL MSTROMOD NMOS (VTO = 3.37 KP = 205 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.56 KP = 0.10 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 8.5 )
.MODEL RBREAKMOD RES (TC1 = 1.09e- 3TC2 = 1.04e-7)
.MODEL RDRAINMOD RES (TC1 = 1.38e-2 TC2 = 3.75e-5)
.MODEL RSLCMOD RES (TC1 = 1.05e-4 TC2 = 2.13e-7)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -2.92e-3 TC2 = -1.48e-5)
.MODEL RVTEMPMOD RES (TC1 = -3.0e- 3TC2 = 1.21e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -5.0 VOFF= -3.0)
VON = -3.0 VOFF= -5.0)
VON = -2.0 VOFF= 0.0)
VON = 0.0 VOFF= -2.0)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2001 Fairchild Semiconductor Corporation
HUFA75652G3 Rev. B
HUFA75652G3
SABER Electrical Model
REV 11 May 1999
template ta75652 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 6.55e-12, cjo = 8.71e-9, tt = 7.81e-8, m = 0.50)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 1.0e-8, is = 1e-30, n=1, m = 0.85 )
m..model mmedmod = (type=_n, vto = 2.91, kp = 6.5, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.37, kp = 205, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.56, kp = 0.1, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5, voff = -3)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -3, voff = -5)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -2, voff = 0)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0, voff = -2)
LDRAIN
DPLCAP
10
RSLC1
51
c.ca n12 n8 = 11.0e-9
c.cb n15 n14 = 11.4e-9
c.cin n6 n8 = 6.95e-9
RLDRAIN
RDBREAK
RSLC2
72
ISCL
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
i.it n8 n17 = 1
LGATE
GATE
1
EVTEMP
RGATE + 18 22
9
20
MWEAK
MSTRO
CIN
DBODY
EBREAK
+
17
18
MMED
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
71
11
16
6
RLGATE
res.rbreak n17 n18 = 1, tc1 = 1.09e-3, tc2 = 1.04e-7
res.rdbody n71 n5 = 1.69e-3, tc1 = 1.95e-3, tc2 = 1.05e-6
res.rdbreak n72 n5 = 1.45e-1, tc1 = 1.02e-4, tc2 = 1.11e-7
res.rdrain n50 n16 = 2.80e-3, tc1 = 1.38e-2, tc2 = 3.75e-5
res.rgate n9 n20 = 0.85
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 57.4
res.rlsource n3 n7 = 46.5
res.rslc1 n5 n51 = 1e-6, tc1 = 1.05e-4, tc2 = 2.13e-7
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 2.50e-3, tc1 = 0, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -3.0e-3, tc2 = 1.21e-6
res.rvthres n22 n8 = 1, tc1 = -2.92e-3, tc2 = -1.48e-5
21
RDBODY
DBREAK
50
-
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 5.74e-9
l.lsource n3 n7 = 4.65e-9
DRAIN
2
5
-
8
LSOURCE
7
SOURCE
3
RSOURCE
RLSOURCE
S1A
12
S2A
14
13
13
8
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
+
6
8
EGS
19
CB
+
-
-
IT
14
VBAT
5
8
EDS
-
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 117.5
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/455))** 2))
}
}
©2001 Fairchild Semiconductor Corporation
HUFA75652G3 Rev. B
HUFA75652G3
SPICE Thermal Model
th
JUNCTION
REV 1April 1999
HUFA75652T
CTHERM1 th 6 9.75e-3
CTHERM2 6 5 3.90e-2
CTHERM3 5 4 2.50e-2
CTHERM4 4 3 2.95e-2
CTHERM5 3 2 6.55e-2
CTHERM6 2 tl 12.55
RTHERM1
RTHERM1 th 6 1.96e-3
RTHERM2 6 5 4.89e-3
RTHERM3 5 4 1.38e-2
RTHERM4 4 3 7.73e-2
RTHERM5 3 2 1.17e-1
RTHERM6 2 tl 1.55e-2
RTHERM2
CTHERM1
6
CTHERM2
5
CTHERM3
RTHERM3
SABER Thermal Model
SABER thermal model HUFA75652T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 9.75e-3
ctherm.ctherm2 6 5 = 3.90e-2
ctherm.ctherm3 5 4 = 2.50e-2
ctherm.ctherm4 4 3 = 2.95e-2
ctherm.ctherm5 3 2 = 6.55e-2
ctherm.ctherm6 2 tl = 12.55
rtherm.rtherm1 th 6 = 1.96e-3
rtherm.rtherm2 6 5 = 4.89e-3
rtherm.rtherm3 5 4 = 1.38e-2
rtherm.rtherm4 4 3 = 7.73e-2
rtherm.rtherm5 3 2 = 1.17e-1
rtherm.rtherm6 2 tl = 1.55e-2
}
4
CTHERM4
RTHERM4
3
CTHERM5
RTHERM5
2
CTHERM6
RTHERM6
tl
©2001 Fairchild Semiconductor Corporation
CASE
HUFA75652G3 Rev. B
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Rev. H4
