ISL9N302AS3ST
N-Channel Logic Level PWM Optimized UltraFET® Trench Power MOSFETs
General Description
Features
This device employs a new advanced trench MOSFET
technology and features low gate charge while maintaining
low on-resistance.
• Fast switching
Optimized for switching applications, this device improves
the overall efficiency of DC/DC converters and allows
operation to higher switching frequencies.
• rDS(ON) = 0.0027Ω (Typ), VGS = 4.5V
Applications
• Qgd (Typ) = 31nC
• DC/DC converters
• CISS (Typ) = 11000pF
• rDS(ON) = 0.0019Ω (Typ), VGS = 10V
• Qg (Typ) = 110nC, VGS = 5V
DRAIN
(FLANGE)
D
GATE
G
SOURCE
S
TO-263AB
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Symbol
VDSS
Drain to Source Voltage
Parameter
Ratings
30
Units
V
VGS
Gate to Source Voltage
±20
V
A
Drain Current
ID
Continuous (TC = 25oC, VGS = 10V)
75
Continuous (TC = 100oC, VGS = 4.5V)
75
A
Continuous (TC = 25oC, VGS = 10V, R θJA = 43oC/W)
28
A
Pulsed
PD
Power dissipation
Derate above 25oC
TJ, TSTG
Operating and Storage Temperature
Figure 4
A
345
2.3
W
W/oC
o
-55 to 175
C
Thermal Characteristics
0.43
o
C/W
Thermal Resistance Junction to Ambient TO-263
62
o
C/W
Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area
43
o
C/W
RθJC
Thermal Resistance Junction to Case TO-263
RθJA
RθJA
Package Marking and Ordering Information
Device Marking
N302AS
©2002 Fairchild Semiconductor Corporation
Device
ISL9N302AS3ST
Package
TO-263AB
Reel Size
330mm
Tape Width
24mm
Quantity
800 units
Rev. B1,April 2002
ISL9N302AS3ST
April 2002
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
30
-
-
-
V
-
1
-
-
250
µA
-
-
±100
nA
3
V
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
VDS = 25V
VGS = 0V
TC = 150o
VGS = ±20V
On Characteristics
VGS(TH)
rDS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
VGS = VDS, ID = 250µA
1
ID = 75A, VGS = 10V
-
0.0019 0.0023
-
ID = 75A, VGS = 4.5V
-
0.0027 0.0033
-
11000
-
-
2000
-
pF
-
900
-
pF
nC
Ω
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
VDS = 15V, VGS = 0V,
f = 1MHz
Qg(TOT)
Total Gate Charge at 10V
VGS = 0V to 10V
Qg(5)
Total Gate Charge at 5V
Qg(TH)
Threshold Gate Charge
Qgs
Gate to Source Gate Charge
VGS = 0V to 5V V = 15V
DD
VGS = 0V to 1V ID = 75A
Ig = 1.0mA
Qgd
Gate to Drain “Miller” Charge
pF
200
300
-
110
165
nC
-
12
18
nC
-
25
-
nC
-
31
-
nC
ns
Switching Characteristics (VGS = 4.5V)
tON
Turn-On Time
-
-
224
td(ON)
Turn-On Delay Time
-
29
-
ns
tr
Rise Time
-
120
-
ns
td(OFF)
Turn-Off Delay Time
-
45
-
ns
tf
Fall Time
-
34
-
ns
tOFF
Turn-Off Time
-
-
119
ns
ns
VDD = 15V, ID = 28A
VGS = 4.5V, RGS = 1.5Ω
Switching Characteristics (VGS = 10V)
tON
Turn-On Time
-
-
204
td(ON)
Turn-On Delay Time
-
16
-
ns
tr
Rise Time
-
120
-
ns
td(OFF)
Turn-Off Delay Time
-
70
-
ns
tf
Fall Time
-
30
-
ns
tOFF
Turn-Off Time
-
-
150
ns
480
-
-
µs
V
VDD = 15V, ID = 28A
VGS = 10V, R GS = 1.5Ω
Unclamped Inductive Switching
tAV
Avalanche Time
ID = 7.2A, L = 3.0mH
Drain-Source Diode Characteristics
ISD = 75A
-
-
1.25
ISD = 40A
-
-
1.0
V
Reverse Recovery Time
ISD = 75A, dISD /dt = 100A/µs
-
-
42
ns
Reverse Recovered Charge
ISD = 75A, dISD /dt = 100A/µs
-
-
34
nC
VSD
Source to Drain Diode Voltage
trr
QRR
©2002 Fairchild Semiconductor Corporation
Rev. B1 April 2002
ISL9N302AS3ST
Electrical Characteristics TA = 25°C unless otherwise noted
ISL9N302AS3ST
Typical Characteristic
POWER DISSIPATION MULTIPLIER
1.2
80
ID, DRAIN CURRENT (A)
1.0
0.8
0.6
0.4
VGS = 10V
60
VGS = 4.5V
40
20
0.2
0
0
0
25
50
75
100
150
125
175
25
50
75
TC , CASE TEMPERATURE (oC)
100
125
150
175
TC, CASE TEMPERATURE (o C)
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t , RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
IDM , PEAK CURRENT (A)
5000
1000
TC = 25 oC
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 10V
175 - TC
I = I25
150
VGS = 5V
100
50
10-5
10-4
10-3
10-2
10-1
100
101
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
©2002 Fairchild Semiconductor Corporation
Rev. B1 April 2002
ISL9N302AS3ST
Typical Characteristic (Continued)
150
150
PULSE DURATION = 80µs
125
ID, DRAIN CURRENT (A)
ID , DRAIN CURRENT (A)
VGS = 3.5V
DUTY CYCLE = 0.5% MAX
VDD = 15V
125
100
75
TJ = 25oC
50
TJ = 175 oC
VGS = 3V
100
75
VGS = 4.5V
50
25
TC = 25oC
VGS = 10V
25
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TJ = -55oC
0
0
1.5
2.0
2.5
3.0
0
3.5
0.5
VGS , GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics
2.0
1.8
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
8
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
1.5
Figure 6. Saturation Characteristics
10
ID = 75A
6
ID = 10A
4
2
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
1.6
1.4
1.2
1.0
0.8
VGS = 10V, ID = 75A
0.6
0
2
4
6
8
-80
10
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 7. Drain to Source On Resistance vs Gate
Voltage and Drain Current
Figure 8. Normalized Drain to Source On
Resistance vs Junction Temperature
1.2
1.4
VGS = VDS, ID = 250µA
ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.2
NORMALIZED GATE
THRESHOLD VOLTAGE
1.0
VDS , DRAIN TO SOURCE VOLTAGE (V)
1.0
0.8
0.6
0.4
1.1
1.0
0.9
0.2
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE
160
200
(o C)
Figure 9. Normalized Gate Threshold Voltage vs
Junction Temperature
©2002 Fairchild Semiconductor Corporation
-80
-40
0
40
80
120
TJ , JUNCTION TEMPERATURE
160
200
(oC)
Figure 10. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
Rev. B1 April 2002
ISL9N302AS3ST
Typical Characteristic (Continued)
20000
VGS , GATE TO SOURCE VOLTAGE (V)
10
10000
C, CAPACITANCE (pF)
CISS = CGS + CGD
COSS ≅ CDS + C GD
CRSS = C GD
1000
VGS = 0V, f = 1MHz
500
0.1
1
10
VDD = 15V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 75A
ID = 28A
2
0
0
30
50
100
VDS , DRAIN TO SOURCE VOLTAGE (V)
150
200
250
Qg, GATE CHARGE (nC)
Figure 11. Capacitance vs Drain to Source
Voltage
Figure 12. Gate Charge Waveforms for Constant
Gate Currents
1000
1400
VGS = 10V, VDD = 15V, ID = 28A
VGS = 4.5V, VDD = 15V, ID = 28A
1200
600
tr
SWITCHING TIME (ns)
SWITCHING TIME (ns)
800
tf
400
td(OFF)
1000
800
td(OFF)
600
tf
400
tr
200
200
td(ON)
td(ON)
0
0
0
10
20
30
40
0
50
RGS, GATE TO SOURCE RESISTANCE (Ω)
10
20
30
40
50
RGS, GATE TO SOURCE RESISTANCE (Ω)
Figure 13. Switching Time vs Gate Resistance
Figure 14. Switching Time vs Gate Resistance
Test Circuits and Waveforms
BVDSS
VDS
tP
VDS
L
IAS
VDD
VARY tP TO OBTAIN
REQUIRED PEAK I AS
+
RG
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
Figure 15. Unclamped Energy Test Circuit
©2002 Fairchild Semiconductor Corporation
Figure 16. Unclamped Energy Waveforms
Rev. B1 April 2002
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10V
VGS
Qg(5)
+
VDD
VGS = 5V
VGS
-
VGS = 1V
DUT
0
Ig(REF)
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON
tOFF
td(ON)
td(OFF)
tr
RL
VDS
tf
90%
90%
+
VGS
VDD
-
10%
0
10%
DUT
90%
RGS
VGS
VGS
0
Figure 19. Switching Time Test Circuit
©2002 Fairchild Semiconductor Corporation
50%
10%
50%
PULSE WIDTH
Figure 20. Switching Time Waveforms
Rev. B1 April 2002
ISL9N302AS3ST
Test Circuits and Waveforms (Continued)
ISL9N302AS3ST
Thermal Resistance vs. Mounting Pad Area
(T
–T )
JM
A
P D M = ----------------------------Z θJA
(EQ. 1)
In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
80
RθJA = 26.51+ 19.84/(0.262+Area)
60
RθJA (oC/W)
The maximum rated junction temperature, TJM , and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM , in an
application.
Therefore the application’s ambient
temperature, TA (oC), and thermal resistance R θJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
40
20
0.1
1
10
AREA, TOP COPPER AREA (in2)
Figure 21. Thermal Resistance vs Mounting
Pad Area
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Displayed on the curve are R θJA values listed in the
Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
PDM .
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. R θJA is defined as the natural log of the area
times a coefficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
19.84
( 0.262 + Area )
RθJA = 26.51 + -------------------------------------
©2002 Fairchild Semiconductor Corporation
(EQ. 2)
Rev. B1 April 2002
SUBCKT ISL9N302AS3ST 2 1 3 ;
rev May 2001
CA 12 8 5e-9
Cb 15 14 5.5e-9
Cin 6 8 1e-8
LDRAIN
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
DPLCAP
10
5
51
-
EVTEMP
RGATE + 18 22
9
20
GATE
1
11
+
17
EBREAK 18
-
50
EVTHRES
16
21
+ 19 8
+
LGATE
ESLC
RDRAIN
6
8
ESG
DBREAK
+
RSLC2
It 8 17 1
6
DBODY
MWEAK
MMED
MSTRO
RLGATE
LSOURCE
CIN
RLgate 1 9 56.1
RLdrain 2 5 15
RLsource 3 7 19.8
8
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
12
13
8
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 4e-4
Rgate 9 20 5.93e-1
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 1.3e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
RLDRAIN
RSLC1
51
Ebreak 11 7 17 18 30.4
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
Lgate 1 9 5.618e-9
Ldrain 2 5 1e-9
Lsource 3 7 1.98e-9
DRAIN
2
5
S2A
15
14
13
S1B
CA
RBREAK
17
18
RVTEMP
S2B
13
CB
6
8
EGS
5
8
EDS
-
19
VBAT
+
IT
14
+
+
-
8
22
RVTHRES
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),3))}
.MODEL DbodyMOD D (IS=2e-10 N=1.05 RS=1.8e-3 TRS1=9e-4 TRS2=1e-6 + CJO=4.9e-9 M=4.9e-1 TT=1e-13 XTI=0)
.MODEL DbreakMOD D (RS=2.5e-1 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=3.5e-9 IS=1e-30 N=10 M=4.7e-1)
.MODEL MstroMOD NMOS (VTO=2.1 KP=550 IS=1e-25 N=10 TOX=1 L=1u W=1u)
.MODEL MmedMOD NMOS (VTO=1.6 KP=30 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=5.93e-1)
.MODEL MweakMOD NMOS (VTO=1.22 KP=1e-1 IS=1e-40 N=10 TOX=1 L=1u W=1u RG=5.93 RS=1e-1)
.MODEL RbreakMOD RES (TC1=1e-3 TC2=-7e-7)
.MODEL RdrainMOD RES (TC1=1.2e-2 TC2=2.5e-5)
.MODEL RSLCMOD RES (TC1=3.5e-9 TC2=5e-6)
.MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-2.9e-3 TC2=-9e-6)
.MODEL RvtempMOD RES (TC1=-1.8e-3 TC2=1e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-1.5)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-3.5)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.4 VOFF=0.1)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.1 VOFF=-0.4)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2002 Fairchild Semiconductor Corporation
Rev. B1 April 2002
ISL9N302AS3ST
PSPICE Electrical Model
REV May 2001
template ISL9N302AS3ST n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=2e-10,nl=1.05,rs=1.8e-3,trs1=9e-4,trs2=1e-6,cjo=4.9e-9,m=4.9e-1,tt=1e-13,xti=0)
dp..model dbreakmod = (rs=2.5e-1,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=3.5e-9,isl=10e-30,nl=10,m=4.7e-1)
m..model mstrongmod = (type=_n,vto=2.1,kp=550,is=1e-25, tox=1)
m..model mmedmod = (type=_n,vto=1.6,kp=30,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.22,kp=1e-1,is=1e-40, tox=1,rs=1e-1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-3.5,voff=-1.5)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-1.5,voff=-3.5)
LDRAIN
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.4,voff=0.1)
DPLCAP 5
DRAIN
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.1,voff=-0.4)
2
c.ca n12 n8 = 5e-9
10
c.cb n15 n14 = 5.5e-9
RLDRAIN
RSLC1
c.cin n6 n8 = 1e-8
51
RSLC2
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 30.4
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
ISCL
RDRAIN
6
8
ESG
LGATE
EVTEMP
RGATE + 18 22
9
20
6
MWEAK
EBREAK
+
MMED
RLGATE
res.rlgate n1 n9 = 56.1
res.rldrain n2 n5 = 15
res.rlsource n3 n7 = 19.8
DBODY
MSTRO
i.it n8 n17 = 1
CIN
l.lgate n1 n9 = 5.618e-9
l.ldrain n2 n5 = 1e-9
l.lsource n3 n7 = 1.98e-9
11
EVTHRES
16
21
+ 19 8
+
GATE
1
DBREAK
50
-
17
18
-
8
LSOURCE
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
12
13
8
S2A
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
15
14
13
S1B
CA
RBREAK
17
18
RVTEMP
S2B
13
CB
6
8
EGS
-
19
IT
14
+
+
VBAT
5
8
EDS
-
+
8
22
res.rbreak n17 n18 = 1, tc1=1e-3,tc2=-7e-7
res.rdrain n50 n16 = 4e-4, tc1=1.2e-2,tc2=2.5e-5
res.rgate n9 n20 = 5.93e-1
res.rslc1 n5 n51 = 1e-6, tc1=3.5e-9,tc2=5e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 1.3e-3, tc1=1e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-2.9e-3,tc2=-9e-6
res.rvtemp n18 n19 = 1, tc1=-1.8e-3,tc2=1e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
RVTHRES
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 3))
}
©2002 Fairchild Semiconductor Corporation
Rev. B1 April 2002
ISL9N302AS3ST
SABER Electrical Model
th
ISL9N302AS3ST
SPICE Thermal Model
JUNCTION
REV May 2001
ISL9N302AS3ST
CTHERM1 th 6 4.5e-3
CTHERM2 6 5 2e-2
CTHERM3 5 4 1.5e-2
CTHERM4 4 3 2.5e-2
CTHERM5 3 2 7e-2
CTHERM6 2 tl 2.5e-1
RTHERM1 th 6 2e-3
RTHERM2 6 5 8.5e-3
RTHERM3 5 4 6e-2
RTHERM4 4 3 8e-2
RTHERM5 3 2 9e-2
RTHERM6 2 tl 1e-1
SABER Thermal Model
RTHERM1
CTHERM1
6
RTHERM2
CTHERM2
5
CTHERM3
RTHERM3
SABER thermal model ISL9N302AS3ST
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 4.5e-3
ctherm.ctherm2 6 5 = 2e-2
ctherm.ctherm3 5 4 = 1.5e-2
ctherm.ctherm4 4 3 = 2.5e-2
ctherm.ctherm5 3 2 = 7e-2
ctherm.ctherm6 2 tl = 2.5e-1
4
RTHERM4
CTHERM4
3
rtherm.rtherm1 th 6 =2e-3
rtherm.rtherm2 6 5 = 8.5e-3
rtherm.rtherm3 5 4 = 6e-2
rtherm.rtherm4 4 3 = 8e-2
rtherm.rtherm5 3 2 = 9e-2
rtherm.rtherm6 2 tl = 1e-1
}
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
©2002 Fairchild Semiconductor Corporation
CASE
Rev. B1 April 2002
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