J111RL1G

J111, J112 JFET Chopper Transistors N−Channel — Depletion Features • Pb−Free Packages are Available* http://onsemi.com 1 DRAIN MAXIMUM RATINGS Rating Symbol Value Unit Drain −Gate Voltage VDG −35 Vdc Gate −Source Voltage VGS −35 Vdc Gate Current IG 50 mAdc Total Device Dissipation @ TA = 25°C Derate above = 25°C PD 350 2.8 mW mW/°C Lead Temperature TL 300 °C TJ, Tstg −65 to +150 °C Operating and Storage Junction Temperature Range Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 3 GATE 2 SOURCE TO−92 CASE 29−11 STYLE 5 1 2 3 MARKING DIAGRAM J11x AYWW G G J11x = Device Code x = 1 or 2 A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 March, 2006 − Rev. 2 1 Publication Order Number: J111/D J111, J112 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Max Unit V(BR)GSS 35 − Vdc IGSS − − 1.0 nAdc − 3.0 − 1.0 − 10 − 5.0 − 1.0 20 5.0 2.0 − − − − − 30 50 OFF CHARACTERISTICS Gate −Source Breakdown Voltage (IG = −1.0 mAdc) Gate Reverse Current (VGS = −15 Vdc) Gate Source Cutoff Voltage (VDS = 5.0 Vdc, ID = 1.0 mAdc) VGS(off) J111 J112 Drain−Cutoff Current (VDS = 5.0 Vdc, VGS = −10 Vdc) ID(off) Vdc nAdc ON CHARACTERISTICS Zero−Gate−Voltage Drain Current(1) (VDS = 15 Vdc) IDSS J111 J112 Static Drain−Source On Resistance (VDS = 0.1 Vdc) mAdc W rDS(on) J111 J112 Drain Gate and Source Gate On−Capacitance (VDS = VGS = 0, f = 1.0 MHz) Cdg(on) + Csg(on) − 28 pF Drain Gate Off−Capacitance (VGS = −10 Vdc, f = 1.0 MHz) Cdg(off) − 5.0 pF Source Gate Off−Capacitance (VGS = −10 Vdc, f = 1.0 MHz) Csg(off) − 5.0 pF 1. Pulse Width = 300 ms, Duty Cycle = 3.0%. ORDERING INFORMATION Device J111RL1 Package TO−92 J111RL1G TO−92 (Pb−Free) J111RLRA TO−92 J111RLRAG J111RLRP J111RLRPG J112 J112G J112RL1 TO−92 (Pb−Free) 2000 Units / Tape & Reel 2000 Units / Tape & Reel TO−92 TO−92 (Pb−Free) 2000 Units / Tape & Reel TO−92 TO−92 (Pb−Free) 1000 Units / Bulk TO−92 J112RL1G TO−92 (Pb−Free) J112RLRA TO−92 J112RLRAG Shipping † TO−92 (Pb−Free) 2000 Units / Tape & Reel 2000 Units / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 2 J111, J112 TYPICAL SWITCHING CHARACTERISTICS 1000 TJ = 25°C 500 RK = RD′ 200 J111 J112 J113 100 500 VGS(off) = 12 V = 7.0 V = 5.0 V 50 20 10 RK = 0 5.0 RK = RD′ 200 t r , RISE TIME (ns) t d(on), TURN−ON DELAY TIME (ns) 1000 TJ = 25°C VGS(off) = 12 V = 7.0 V = 5.0 V 100 50 20 10 RK = 0 5.0 2.0 2.0 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) 20 30 1.0 0.5 0.7 1.0 50 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) Figure 1. Turn−On Delay Time 1000 1000 TJ = 25°C 500 J111 J112 J113 200 100 VGS(off) = 12 V = 7.0 V = 5.0 V RK = RD′ J111 J112 J113 200 20 10 RK = 0 5.0 30 50 TJ = 25°C 500 RK = RD′ 50 20 Figure 2. Rise Time t f , FALL TIME (ns) t d(off), TURN−OFF DELAY TIME (ns) J111 J112 J113 100 VGS(off) = 12 V = 7.0 V = 5.0 V 50 20 RK = 0 10 5.0 2.0 2.0 1.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) 20 30 1.0 0.5 0.7 1.0 50 Figure 3. Turn−Off Delay Time 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) 20 30 50 Figure 4. Fall Time NOTE 1 +VDD RD SET VDS(off) = 10 V INPUT RK RGEN 50 W RT OUTPUT 50 W RGG VGEN INPUT PULSE tr ≤ 0.25 ns tf ≤ 0.5 ns PULSE WIDTH = 2.0 ms DUTY CYCLE ≤ 2.0% 50 W VGG RGG & RK RD(RT ) 50) RDȀ + RD ) RT ) 50 Figure 5. Switching Time Test Circuit The switching characteristics shown above were measured using a test circuit similar to Figure 5. At the beginning of the switching interval, the gate voltage is at Gate Supply Voltage (−VGG). The Drain−Source Voltage (VDS) is slightly lower than Drain Supply Voltage (VDD) due to the voltage divider. Thus Reverse Transfer Capacitance (Crss) or Gate−Drain Capacitance (Cgd) is charged to VGG + VDS. During the turn−on interval, Gate−Source Capacitance (Cgs) discharges through the series combination of RGen and RK. Cgd must discharge to VDS(on) through RG and RK in series with the parallel combination of effective load impedance (R′D) and Drain−Source Resistance (rds). During the turn−off, this charge flow is reversed. Predicting turn−on time is somewhat difficult as the channel resistance rds is a function of the gate−source voltage. While Cgs discharges, VGS approaches zero and rds decreases. Since Cgd discharges through rds, turn−on time is non−linear. During turn−off, the situation is reversed with rds increasing as Cgd charges. The above switching curves show two impedance conditions; 1) RK is equal to RD, which simulates the switching behavior of cascaded stages where the driving source impedance is normally the load impedance of the previous stage, and 2) RK = 0 (low impedance) the driving source impedance is that of the generator. http://onsemi.com 3 20 15 J112 10 J111 10 J113 7.0 5.0 Cgs C, CAPACITANCE (pF) y fs, FORWARD TRANSFER ADMITTANCE (mmho J111, J112 Tchannel = 25°C VDS = 15 V 7.0 5.0 Cgd 3.0 2.0 3.0 Tchannel = 25°C (Cds IS NEGLIGIBLE) 1.5 2.0 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 ID, DRAIN CURRENT (mA) 20 30 1.0 0.03 0.05 50 0.1 Figure 6. Typical Forward Transfer Admittance IDSS = 10 160 mA 25 mA 50mA 75mA 100mA 80 0 Tchannel = 25°C 0 1.0 2.0 3.0 4.0 5.0 6.0 VGS, GATE−SOURCE VOLTAGE (VOLTS) 30 2.0 125mA 120 40 10 Figure 7. Typical Capacitance 7.0 rds(on), DRAIN−SOURCE ON−STATE RESISTANCE (NORMALIZED) rds(on), DRAIN−SOURCE ON−STATE RESISTANCE (OHMS) 200 0.3 0.5 1.0 3.0 5.0 VR, REVERSE VOLTAGE (VOLTS) 8.0 ID = 1.0 mA VGS = 0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 −70 Figure 8. Effect of Gate−Source Voltage On Drain−Source Resistance −40 −10 20 50 80 110 Tchannel, CHANNEL TEMPERATURE (°C) 140 170 Figure 9. Effect of Temperature On Drain−Source On−State Resistance NOTE 2 90 10 Tchannel = 25°C 9.0 80 70 8.0 7.0 rDS(on) @ VGS = 0 60 50 6.0 VGS(off) 5.0 40 4.0 30 3.0 20 2.0 10 1.0 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 IDSS, ZERO−GATE−VOLTAGE DRAIN CURRENT (mA) Figure 10. Effect of IDSS On Drain−Source Resistance and Gate−Source Voltage VGS, GATE−SOURCE VOLTAGE (VOLTS) rds(on), DRAIN−SOURCE ON−STATE RESISTANCE (OHMS) 100 The Zero−Gate−Voltage Drain Current (IDSS), is the principle determinant of other J-FET characteristics. Figure 10 shows the relationship of Gate−Source Off Voltage (VGS(off) and Drain−Source On Resistance (rds(on)) to IDSS. Most of the devices will be within ±10% of the values shown in Figure 10. This data will be useful in predicting the characteristic variations for a given part number. For example: Unknown rds(on) and VGS range for an J112 The electrical characteristics table indicates that an J112 has an IDSS range of 25 to 75 mA. Figure 10, shows rds(on) = 52 W for IDSS = 25 mA and 30 W for IDSS = 75 mA. The corresponding VGS values are 2.2 V and 4.8 V. http://onsemi.com 4 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TO−92 (TO−226) CASE 29−11 ISSUE AM SCALE 1:1 1 12 3 STRAIGHT LEAD BULK PACK DATE 09 MAR 2007 2 3 BENT LEAD TAPE & REEL AMMO PACK A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. CONTOUR OF PACKAGE BEYOND DIMENSION R IS UNCONTROLLED. 4. LEAD DIMENSION IS UNCONTROLLED IN P AND BEYOND DIMENSION K MINIMUM. STRAIGHT LEAD BULK PACK R P L SEATING PLANE K DIM A B C D G H J K L N P R V D X X G J H V C SECTION X−X N 1 INCHES MIN MAX 0.175 0.205 0.170 0.210 0.125 0.165 0.016 0.021 0.045 0.055 0.095 0.105 0.015 0.020 0.500 --0.250 --0.080 0.105 --0.100 0.115 --0.135 --- MILLIMETERS MIN MAX 4.45 5.20 4.32 5.33 3.18 4.19 0.407 0.533 1.15 1.39 2.42 2.66 0.39 0.50 12.70 --6.35 --2.04 2.66 --2.54 2.93 --3.43 --- N A R NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. CONTOUR OF PACKAGE BEYOND DIMENSION R IS UNCONTROLLED. 4. LEAD DIMENSION IS UNCONTROLLED IN P AND BEYOND DIMENSION K MINIMUM. BENT LEAD TAPE & REEL AMMO PACK B P T SEATING PLANE G K DIM A B C D G J K N P R V D X X J V 1 C N SECTION X−X MILLIMETERS MIN MAX 4.45 5.20 4.32 5.33 3.18 4.19 0.40 0.54 2.40 2.80 0.39 0.50 12.70 --2.04 2.66 1.50 4.00 2.93 --3.43 --- STYLES ON PAGE 2 DOCUMENT NUMBER: STATUS: 98ASB42022B ON SEMICONDUCTOR STANDARD NEW STANDARD: © Semiconductor Components Industries, LLC, 2002 October, DESCRIPTION: 2002 − Rev. 0 TO−92 (TO−226) http://onsemi.com 1 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. Case Outline Number: PAGE 1 OFXXX 3 TO−92 (TO−226) CASE 29−11 ISSUE AM DATE 09 MAR 2007 STYLE 1: PIN 1. EMITTER 2. BASE 3. COLLECTOR STYLE 2: PIN 1. BASE 2. EMITTER 3. COLLECTOR STYLE 3: PIN 1. ANODE 2. ANODE 3. CATHODE STYLE 4: PIN 1. CATHODE 2. CATHODE 3. ANODE STYLE 5: PIN 1. DRAIN 2. SOURCE 3. GATE STYLE 6: PIN 1. GATE 2. SOURCE & SUBSTRATE 3. DRAIN STYLE 7: PIN 1. SOURCE 2. DRAIN 3. GATE STYLE 8: PIN 1. DRAIN 2. GATE 3. SOURCE & SUBSTRATE STYLE 9: PIN 1. BASE 1 2. EMITTER 3. BASE 2 STYLE 10: PIN 1. CATHODE 2. GATE 3. ANODE STYLE 11: PIN 1. ANODE 2. CATHODE & ANODE 3. CATHODE STYLE 12: PIN 1. MAIN TERMINAL 1 2. GATE 3. MAIN TERMINAL 2 STYLE 13: PIN 1. ANODE 1 2. GATE 3. CATHODE 2 STYLE 14: PIN 1. EMITTER 2. COLLECTOR 3. BASE STYLE 15: PIN 1. ANODE 1 2. CATHODE 3. ANODE 2 STYLE 16: PIN 1. ANODE 2. GATE 3. CATHODE STYLE 17: PIN 1. COLLECTOR 2. BASE 3. EMITTER STYLE 18: PIN 1. ANODE 2. CATHODE 3. NOT CONNECTED STYLE 19: PIN 1. GATE 2. ANODE 3. CATHODE STYLE 20: PIN 1. NOT CONNECTED 2. CATHODE 3. ANODE STYLE 21: PIN 1. COLLECTOR 2. EMITTER 3. BASE STYLE 22: PIN 1. SOURCE 2. GATE 3. DRAIN STYLE 23: PIN 1. GATE 2. SOURCE 3. DRAIN STYLE 24: PIN 1. EMITTER 2. COLLECTOR/ANODE 3. CATHODE STYLE 25: PIN 1. MT 1 2. GATE 3. MT 2 STYLE 26: PIN 1. VCC 2. GROUND 2 3. OUTPUT STYLE 27: PIN 1. MT 2. SUBSTRATE 3. MT STYLE 28: PIN 1. CATHODE 2. ANODE 3. GATE STYLE 29: PIN 1. NOT CONNECTED 2. ANODE 3. CATHODE STYLE 30: PIN 1. DRAIN 2. GATE 3. SOURCE STYLE 31: PIN 1. GATE 2. DRAIN 3. SOURCE STYLE 32: PIN 1. BASE 2. COLLECTOR 3. EMITTER STYLE 33: PIN 1. RETURN 2. INPUT 3. OUTPUT STYLE 34: PIN 1. INPUT 2. GROUND 3. LOGIC STYLE 35: PIN 1. GATE 2. COLLECTOR 3. EMITTER DOCUMENT NUMBER: STATUS: 98ASB42022B ON SEMICONDUCTOR STANDARD NEW STANDARD: © Semiconductor Components Industries, LLC, 2002 October, DESCRIPTION: 2002 − Rev. 0 TO−92 (TO−226) http://onsemi.com 2 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. Case Outline Number: PAGE 2 OFXXX 3 DOCUMENT NUMBER: 98ASB42022B PAGE 3 OF 3 ISSUE AM REVISION ADDED BENT−LEAD TAPE & REEL VERSION. REQ. BY J. SUPINA. DATE 09 MAR 2007 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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