KAC-06040 IMAGE SENSOR
2832 (H) X 2128 (V) CMOS IMAGE SENSOR
JUNE 13, 2014
DEVICE PERFORMANCE SPECIFICATION
REVISION 1.1 PS-1593
KAC-06040 Image Sensor
TABLE OF CONTENTS
Summary Specification ........................................................................................................................................................................................ 5
Description ................................................................................................................................................................................................... 5
Features ........................................................................................................................................................................................................ 5
Applications ................................................................................................................................................................................................. 5
Ordering Information ........................................................................................................................................................................................... 6
KAC-06040 Image Sensor ......................................................................................................................................................................... 6
Evaluation Support..................................................................................................................................................................................... 6
Device Description ................................................................................................................................................................................................ 7
Architecture ................................................................................................................................................................................................. 7
Physical Orientation................................................................................................................................................................................... 8
Primary Pin Description ............................................................................................................................................................................ 9
Power Pin Description ............................................................................................................................................................................... 9
LVDS Pin Description ...............................................................................................................................................................................10
Imaging Performance ......................................................................................................................................................................................... 11
Typical Operation Conditions ................................................................................................................................................................11
Performance Specifications All Configurations ................................................................................................................................11
KAC-06040-ABA Configuration (Monochrome) ............................................................................................................................12
KAC-06040-CBA Configuration (Bayer RGB) .................................................................................................................................12
Typical Performance Curves ........................................................................................................................................................................... 13
Quantum Efficiency..................................................................................................................................................................................13
Monochrome with Microlens .............................................................................................................................................................13
Color (Bayer RGB) with Microlens ....................................................................................................................................................14
Angular Quantum Efficiency ..................................................................................................................................................................15
Dark Current versus Temperature .......................................................................................................................................................17
Power vs Frame Rate ...............................................................................................................................................................................18
Power and Frame Rate vs ADC Bit depth .......................................................................................................................................19
Defect Definitions ............................................................................................................................................................................................... 21
Operation Conditions for Defect Testing ..........................................................................................................................................21
Defect Definitions for Testing ..............................................................................................................................................................21
Test Definitions .................................................................................................................................................................................................... 22
Test Regions of Interest .........................................................................................................................................................................22
Tests .............................................................................................................................................................................................................22
Operation ................................................................................................................................................................................................................. 28
Register Addresses ..................................................................................................................................................................................28
Sensor States .............................................................................................................................................................................................28
Encoded Syncs ...........................................................................................................................................................................................29
Line Time ....................................................................................................................................................................................................30
Frame Time ................................................................................................................................................................................................31
Global Shutter Readout ..........................................................................................................................................................................32
Rolling Shutter Readout .........................................................................................................................................................................33
8 Bank LVDS Data Readout .............................................................................................................................................................................. 34
LVDS Banks ................................................................................................................................................................................................34
Ports per LVDS Bank ................................................................................................................................................................................34
8 Bank Pixel Order ....................................................................................................................................................................................35
De-Serializer Settings ..............................................................................................................................................................................36
Register Definition .............................................................................................................................................................................................. 37
Absolute Maximum Ratings ............................................................................................................................................................................. 38
Supplies .......................................................................................................................................................................................................38
CMOS Inputs ..............................................................................................................................................................................................38
Operating Ratings ................................................................................................................................................................................................ 39
Input Clock Conditions ............................................................................................................................................................................39
Operating Temperature..........................................................................................................................................................................39
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Revision 1.1 PS-1593 Pg 2
KAC-06040 Image Sensor
CMOS IN/OUT ............................................................................................................................................................................................39
Supplies .......................................................................................................................................................................................................40
SPI (Serial Peripheral Interface) .................................................................................................................................................................... 41
Clock Polarity and Phase.........................................................................................................................................................................41
SPI Protocol ................................................................................................................................................................................................42
SPI interface ...............................................................................................................................................................................................44
SPI timing specification ...........................................................................................................................................................................44
LVDS Interface ...................................................................................................................................................................................................... 45
Standard LVDS characteristics ..............................................................................................................................................................45
Sub-LVDS characteristics ........................................................................................................................................................................45
In-block LVDS timing specification .......................................................................................................................................................46
Inter-block LVDS timing specification .................................................................................................................................................46
Storage and Handling ......................................................................................................................................................................................... 47
Storage Conditions...................................................................................................................................................................................47
ESD ...............................................................................................................................................................................................................47
Cover Glass Care and Cleanliness .........................................................................................................................................................47
Environmental Exposure ........................................................................................................................................................................47
Soldering Recommendations ................................................................................................................................................................47
Mechanical Information .................................................................................................................................................................................... 48
Completed Assembly ...............................................................................................................................................................................48
MAR (Multi-layer Anti-Reflective coating) Cover Glass...................................................................................................................52
Quality Assurance and Reliability ................................................................................................................................................................. 53
Quality and Reliability .............................................................................................................................................................................53
Replacement ..............................................................................................................................................................................................53
Liability of the Supplier ...........................................................................................................................................................................53
Liability of the Customer ........................................................................................................................................................................53
Test Data Retention .................................................................................................................................................................................53
Mechanical..................................................................................................................................................................................................53
Life Support Applications Policy ................................................................................................................................................................... 53
Revision Changes.................................................................................................................................................................................................. 54
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Revision 1.1 PS-1593 Pg 3
KAC-06040 Image Sensor
TABLE OF FIGURES
Figure 1: Block Diagram ................................................................................................................................................................................ 7
Figure 2: Package Pin Orientation – Top x-ray view ............................................................................................................................... 8
Figure 3: Monochrome QE (with Microlens) ..........................................................................................................................................13
Figure 4: Bayer QE (with Microlens) .........................................................................................................................................................14
Figure 5: Monochrome Relative Angular QE (with Microlens) ..........................................................................................................15
Figure 6: Monochrome Relative Angular QE (with Microlens) ..........................................................................................................16
Figure 7: Dark Current vs Temperature ..................................................................................................................................................17
Figure 8: Dual-Scan Power vs Frame Rate, 10 bit mode ......................................................................................................................18
Figure 9: Tri-Scan Power vs Frame Rate, 10 bit mode .........................................................................................................................18
Figure 10: Dual-Scan ADC Bit Depth impact on Frame Rate and Power .........................................................................................19
Figure 11: Tri-Scan vs Dual-Scan Power ...................................................................................................................................................20
Figure 12: Regions of Interest ...................................................................................................................................................................22
Figure 13: Sensor State Diagram ..............................................................................................................................................................28
Figure 14: Encoded Frame Syncs ..............................................................................................................................................................29
Figure 15: Dual-Scan Line Time Relationship .........................................................................................................................................30
Figure 16: Tri-Scan Line Time Relationship.............................................................................................................................................30
Figure 17: Default frame time configuration (Frame A) .....................................................................................................................31
Figure 18: Frame time with extended integration time. ....................................................................................................................31
Figure 19: Illustration of frame time for Global Shutter readout .....................................................................................................32
Figure 20: Illustration of Frame time for Rolling Shutter readout ...................................................................................................33
Figure 21: LVDS Bank labeling ...................................................................................................................................................................34
Figure 22: Number of LVDS pairs (ports) used vs. bit depth ..............................................................................................................34
Figure 23: Pixel readout order diagram ..................................................................................................................................................35
Figure 24: Pixel readout order table ........................................................................................................................................................36
Figure 25: Data stream of one LVDS Bank for 10bits ADC resolution.............................................................................................36
Figure 26: CPOL = 1 and CPHA = 1 configuration .................................................................................................................................41
Figure 27: SPI Write byte order .................................................................................................................................................................42
Figure 28: SPI Read byte order ..................................................................................................................................................................42
Figure 29: SPI Read with FBRB handshaking..........................................................................................................................................43
Figure 30: SPI timing chronogram ............................................................................................................................................................44
Figure 31: LVDS timing chronogram ........................................................................................................................................................46
Figure 32: Completed Assembly (1 of 5) .................................................................................................................................................48
Figure 33: Completed Assembly (2 of 5) .................................................................................................................................................49
Figure 34: Completed Assembly (3 of 5) .................................................................................................................................................50
Figure 35: Completed Assembly (4 of 5) .................................................................................................................................................51
Figure 36: Completed Assembly (5 of 5) .................................................................................................................................................51
Figure 37: MAR Cover Glass Specification ..............................................................................................................................................52
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Revision 1.1 PS-1593 Pg 4
KAC-06040 Image Sensor
Summary Specification
KAC-06040 Image Sensor
DESCRIPTION
The KAC-06040 Image Sensor is a high-speed 6 megapixel
CMOS image sensor in a 1” optical format based on a
4.7 μm 5T CMOS platform. The image sensor features
very fast frame rate, excellent NIR sensitivity, and
flexible readout modes with multiple regions of interest
(ROI). The readout architecture enables use of 8, 4, or 2
LVDS output banks for full resolution readout of 160
frames per second.
Parameter
Typical Value
Architecture
5T Global Shutter CMOS
Resolution
6 megapixels
Aspect Ratio
4:3
Pixel Size
4.7 µm (H) x 4.7 µm (V)
Total Number of Pixels
3024 (H) x 2320 (V)
The image sensor has a pre-configured QHD (4 x 720p,
16:9) video mode, fully programmable, multiple ROI for
windowing, programmable sub-sampling, and reverse
readout (flip and mirror).
The two ADCs can be
configured for 8-bit, 10-bit, 12-bit or 14-bit conversion
and output.
Number of Effective Pixels
2848 (H) x 2144 (V)
Number of Active Pixels
2832 (H) x 2128 (V)
Active Image Size
13.1 mm (H) x 10.0 mm (V)
16.65 mm (diag.), 1” optical format
Master Clock Input Speed
5 MHz to 50 MHz
Maximum Pixel Clock Speed
200 MHz DDR LVDS, 400 Mbps
Number of LVDS Outputs
64 differential pairs
Additional features include interspersed video streams
(dual-video), on-chip responsivity calibration, black
clamping, overflow pixel for blooming reduction, blacksun correction (anti-eclipse), column and row noise
correction, and integrated timing generation with SPI
control, 4:1 and 9:1 averaging decimation modes.
Number of Output Banks
8, 4, or 2
Frame Rate, 6 MP
1 - 160 fps 10 bits
Charge Capacity
17,000 electrons
Quantum Efficiency
KAC-06040-CBA
KAC-06040-ABA
40%, 47%, 45% (470, 540, 620 nm)
53%, 15%, 10% (500, 850, 900 nm)
Read Noise
(at maximum LVDS clock)
3.4 e- rms, Rolling Shutter
25 e- rms, Global Shutter
FEATURES
Dynamic Range
74 dB, Rolling Shutter
57 dB, Global Shutter
Blooming Suppression
>10,000x
Image Lag
1.6 electron
Digital Core Supply
2.0 V
Analog Core Supply
1.8 V
Pixel Supply
2.8 V & 3.5 V
Power Consumption
2.3 W for 6 Mp @ 160 fps 10 bits
Package
267 pin ceramic micro-PGA
Each LVDS output bank consists of up to 8 differential
pairs operating at 200 MHz DDR for a 400 Mbps data rate
per pair. The pixel architecture allows rolling shutter
operation for motion capture with optimized dynamic
range or global shutter for precise still image capture.
Global shutter and rolling shutter
Very fast frame rate
High NIR sensitivity
Multiple regions of interest
Interspersed video streams
APPLICATIONS
Machine Vision
Intelligent Transportation Systems
Surveillance
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Cover Glass
AR Coated, 2-sides
All parameters are specified at T = 40 °C unless otherwise noted
Revision 1.1 PS-1593 Pg 5
KAC-06040 Image Sensor
Ordering Information
KAC-06040 IMAGE SENSOR
Catalog
Number
Product Name
Description
Marking Code
4H2284
KAC-06040-ABA-JD-AA
Monochrome, micro-PGA Package,
Sealed Clear Cover Glass with AR coating(both sides), Standard Grade
KAC-06040-ABA
Serial Number
4H2286 (1)
KAC-06040-ABA-JD-AE
Monochrome, micro-PGA Package,
Sealed Clear Cover Glass with AR coating(both sides), Engineering Grade
KAC-06040-ABA
Serial Number
4H2287
KAC-06040-CBA-JD-AA
Bayer (RGB) Color Filter Pattern, micro-PGA Package,
Sealed Clear Cover Glass with AR coating(both sides), Standard Grade
KAC-06040-CBA
Serial Number
4H2289 (1)
KAC-06040-CBA-JD-AE
Bayer (RGB) Color Filter Pattern, micro-PGA Package,
Sealed Clear Cover Glass with AR coating(both sides), Engineering Grade
KAC-06040-CBA
Serial Number
Notes:
1.
Engineering Grade samples might not meet final production testing limits, especially for cosmetic defects such as clusters,
but also possibly column and row artifacts. Overall performance is representative of final production parts.
EVALUATION SUPPORT
Catalog
Number
Product Name
Description
4H2306
KEK-TBD-KAC-06040-CB
Evaluation Hardware for KAC-06040 Image Sensor (Bayer). Includes Image Sensor.
4H2307
KEK-TBD-KAC-06040-AB
Evaluation Hardware for KAc-06040 Image Sensor (monochrome). Includes Image Sensor.
4H2211
Lens Mount Kit
Lens Mount Kit that supports C, CS, and F mount lenses. Includes IR cut-filter for color imaging.
See Application Note Product Naming Convention for a full description of the naming convention used for image
sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.truesenseimaging.com.
Please address all inquiries and purchase orders to:
Truesense Imaging, Inc.
1964 Lake Avenue
Rochester, New York 14615
Phone: (585) 784-5500
E-mail: info@truesenseimaging.com
ON Semiconductor reserves the right to change any information contained herein without notice. All information
furnished by ON Semiconductor is believed to be accurate.
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Revision 1.1 PS-1593 Pg 6
KAC-06040 Image Sensor
Device Description
LVDS Bank 3
LVDS Bank 5
7D0 à 7D6
Clk7
5D0 à 5D6
Clk5
Clk3
3D0 à 3D6
ARCHITECTURE
LVDS Bank 7
Clk0
88
8
B G
G R
B G
G R
8
8
88
88
2832 (H) x 2128 (V)
4.7 µm pixel
B G
G R
B G
G R
8
(0,0)
88
Timing Control, Sub-Sampling/Averaging
0D0 à 0D6
Digital Gain/Offset, Noise Correcction
Clk1
LVDS Bank 0
1D0 à 1D6
LVDS Bank 1
Odd Row ADC, Analog Gain, Black-Sun Correction
Even Row ADC, Analog Gain, Black-Sun Correction
LVDS Bank 2
LVDS Bank 4
3.50 VA
3.3 VD
2.80 VA
2.0 VD
1.8 VA
Chip Clock
Trigger
ResetN
CSN
Sclk
MOSI
MISO
RBFB
}
Serial
Peripheral
Interface
(SPI)
ADC_Ref1
4.02 kΩ ±1%
ADC_Ref2
LVDS Bank 6
6D0 à 6D6
Clk6
4D0 à 4D6
Clk4
2D0 à 2D6
Clk2
VSS 0V
Figure 1: Block Diagram
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Revision 1.1 PS-1593 Pg 7
KAC-06040 Image Sensor
PHYSICAL ORIENTATION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
A
B
C
D
E
LVDS Bank 5
LVDS Bank 7
LVDS Bank 2
LVDS Bank 4
LVDS Bank 6
LVDS Bank 0
LVDS Bank 1
LVDS Bank 3
AA
AB
AC
AD
AE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Figure 2: Package Pin Orientation – Top x-ray view
Notes:
1.
2.
3.
4.
5.
The center of the pixel array is aligned to the physical package center.
The region under the sensor die is clear of pins enabling the use of a heat sink.
Non-symmetric mounting holes provide orientation and mounting precision.
Non-symmetric pins prevent incorrect placement in PCB.
Letter “F” indicator shows default readout direction relative to package pin 1
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Revision 1.1 PS-1593 Pg 8
KAC-06040 Image Sensor
PRIMARY PIN DESCRIPTION
Pin
Name
Type
Description
AB09
RESETN
DI
Sensor reset (0 V = Reset State)
E07
CLK_In1
DI
Sensor Input Clk_In1 (5 – 50 MHz)
D08
CLK_In2
DI
Sensor Input Clk_In2 (connect to Clk1)
AB08
TRIGGER
DI
Trigger input (optional)
AA05
SCLK
DI
SPI Master Clock
AA06
CSN
DI
SPI Chip Select (0 V = Selected)
AA07
MISO
DO
SPI Master Input, Slave Output
AA08
MOSI
DI
SPI Master Output Slave Input
AB05
FB
DO
SPI register read feedback
D07
SPI_MS
DI
SPI CPOL/CPHA mode select
AA14
ADC_Ref1
AO
4.02 kΩ ±1% resistor between Ref1 & Ref2
AA15
ADC_Ref2
AO
4.02 kΩ ±1% resistor between Ref1 & Ref2
AB06
FLO
DO
Flash output sync (optional)
AB07
MSO
DO
Mechanical Shutter output sync (optional)
E05
FEN
DO
Frame ENable reference output (optional)
E06
LEN
DO
Line ENable reference output (optional)
Notes:
1.
2.
3.
4.
5.
6.
7.
DI = Digital Input, DO = Digital Output, AO = Analog Output
Tie unused DI pins to Ground, No Connect (NC) unused DO pins
By default Clk_In2 should equal Clk_In1 and should be the same source clock.
The RESETN pin has a 62 kΩ internal pull-up resistor, so if left floating the chip will not be in reset mode.
The TRIGGER pin has an internal 100 kΩ pull down resistor. If left floating (and at default polarity) then the sensor state
will not be affected by this pin (ie defaults to ‘not triggered’ mode if floated)
All of the DI and DO pins nominally operate at 0 V 2.0 V and are associated with the VDD_DIG power supply.
The SPI_MS pin has an internal 100 kΩ pull down resistor. If left floating the CPOL/CHPA will be compatible with
CPOL=CPHA=0 or CPOL=CPHA=1
POWER PIN DESCRIPTION
Name
Voltage
Pins
Description
VDD_LVDS
3.3V D
C04, C05, C23, C24, D04, D24, E04, E24, AA04, AA24, AB04, AB24, AC04,
AC05, AC23, AC24
LVDS output supply
VDD_DIG
2.0V D
C18, C19, C20, C21, C22, D18, D19, D20, D21, D22, D23, E08, E18, E20, E21,
E22, AA18, AA20, AA21, AA22, AB18, AB19, AB20, AB21, AB22, AB23, AC18,
AC19, AC20, AC21, AC22, AB15
Digital core supply
VDD_HV
3.5V A
C11, D11, E11, AA11, AB11, AC11, C10, D10, E10, AA10, AB10, AC10
Pixel supply 1
Vref_P
2.8V A
C13, D13, E13, AA13, AB13, AC13
Pixel supply 2
AVDD_LV
1.8V A
C17, D16, D17, E17, AA17, AB16, AB17, AC17
Analog low voltage supply
Vpixel_low
0V
E09
Pixel Supply 3. Combine with VSS for
normal operation. Can be pulsed for
Extended Dynamic Range Operation
VSS
0V
A02, A14, A26, B14, C03, C06, C12, C14, C25, D03, D12, D14, D25, E03, E12,
E19, E23, E25, AA03, AA12, AA19, AA23, AA25, AB03, AB12, AB14, AB25,
AC03, AC06, AC12, AC14, AC25, AD14, AE02, AE14, AE26, D15, E15, AA09
Sensor ground reference
No Connect
NA
A01, E14, E16, C09, D09, D05, D06, AA16, AC09
Unused and test-only pins. These pins
must be floated.
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Revision 1.1 PS-1593 Pg 9
KAC-06040 Image Sensor
LVDS PIN DESCRIPTION
Pin
E01
1DCLK+
E02
1DCLK-
D01
D02
C01
Name
Descr
Pin
Name
C07
3DCLK+
C08
3DCLK-
1DATA0+
A07
1DATA0-
B07
1DATA1+
A08
Bank 1 LVDS
Clock
Descr
Pin
Name
C15
5DCLK+
C16
5DCLK-
3DATA0+
A15
3DATA0-
B15
3DATA1+
A16
Bank 3
LVDS Clock
Descr
Pin
A22
7DCLK+
B22
7DCLK-
5DATA0+
A23
7DATA0+
5DATA0-
B23
7DATA0-
5DATA1+
A24
7DATA1+
Bank 5
LVDS Clock
C02
1DATA1-
B08
3DATA1-
B16
5DATA1-
B24
7DATA1-
B01
1DATA2+
A09
3DATA2+
A17
5DATA2+
A25
7DATA2+
B02
1DATA2-
A03
1DATA3+
B03
1DATA3-
A04
1DATA4+
Bank 1 LVDS
Data
B09
3DATA2-
A10
3DATA3+
B10
3DATA3-
A11
3DATA4+
Bank 3
LVDS Data
B17
5DATA2-
A18
5DATA3+
B18
5DATA3-
A19
5DATA4+
Bank 5
LVDS Data
B25
7DATA2-
B27
7DATA3+
B26
7DATA3-
C27
7DATA4+
B04
1DATA4-
B11
3DATA4-
B19
5DATA4-
C26
7DATA4-
A05
1DATA5+
A12
3DATA5+
A20
5DATA5+
D27
7DATA5+
B05
1DATA5-
B12
3DATA5-
B20
5DATA5-
D26
7DATA5-
A06
1DATA6+
A13
3DATA6+
A21
5DATA6+
E27
7DATA6+
B06
1DATA6-
B13
3DATA6-
B21
5DATA6-
E26
7DATA6-
Pin
AA01
0DCLK+
AA02
0DCLK-
AB01
Name
Descr
Pin
Name
AC07
2DCLK+
AC08
2DCLK-
0DATA0+
AE07
AB02
0DATA0-
AC01
0DATA1+
AC02
0DATA1-
AD01
0DATA2+
AD02
0DATA2-
AE03
0DATA3+
AD03
0DATA3-
Bank 0
LVDS Clock
Bank 0
LVDS Data
Descr
Pin
Name
Descr
Pin
Name
AC15
4DCLK+
AC16
4DCLK-
AD22
6DCLK-
2DATA0+
AE15
4DATA0+
AE23
6DATA0+
AD07
2DATA0-
AD15
4DATA0-
AD23
6DATA0-
AE08
2DATA1+
AE16
4DATA1+
AE24
6DATA1+
AD08
2DATA1-
AD16
4DATA1-
AD24
6DATA1-
AE09
2DATA2+
AE17
4DATA2+
AE25
6DATA2+
AD09
2DATA2-
AD17
4DATA2-
AD25
6DATA2-
AE10
2DATA3+
AE18
4DATA3+
AD26
6DATA3+
AD10
2DATA3-
AD18
4DATA3-
AD27
6DATA36DATA4+
Bank 2
LVDS Clock
Bank 2
LVDS Data
Bank 4
LVDS Clock
Bank 4
LVDS Data
AE22
6DCLK+
AE04
0DATA4+
AE11
2DATA4+
AE19
4DATA4+
AC26
AD04
0DATA4-
AD11
2DATA4-
AD19
4DATA4-
AC27
6DATA4-
AE05
0DATA5+
AE12
2DATA5+
AE20
4DATA5+
AB26
6DATA5+
AD05
0DATA5-
AD12
2DATA5-
AD20
4DATA5-
AB27
6DATA5-
AE06
0DATA6+
AE13
2DATA6+
AE21
4DATA6+
AA26
6DATA6+
AD06
0DATA6-
AD13
2DATA6-
AD21
4DATA6-
AA27
6DATA6-
Notes:
1.
2.
3.
4.
5.
6.
Des
cr
Name
Bank 7
LVDS
Clock
Bank 7
LVDS
Data
Descr
Bank 6
LVDS
Clock
Bank 6
LVDS
Data
All LVDS Data and Clock lines must be routed with 100 Ω differential transmission line traces.
All the traces for a single LVDS Bank should be the same physical length to minimize skew between the clock and data
lines.
In 2 Bank mode, only LVDS banks 0 and 1 are active.
In 4 Bank mode, only LVDS bank 0, 1, 2, and 3 are active.
Float the pins of unused LVDS Banks to conserve power.
Unused pins in active banks (due to ADC bit depth 10,000
-
W/cm2
Design
27
7
13
Parasitic Light Sensitivity
PLS
-
728
-
-
Design
27
6
9
Dual-Video WDR
-
140 RS
120 GS
-
dB
Design
27
10, 11
Pulsed Pixel WDR (GS only)
-
100
-
dB
Design
27
12, 11
Description
Row Noise
xIlumSat
Notes
3
RS = Rolling Shutter operation mode, GS = Global Shutter operation mode, GR = Global Reset
DS = Dual-Scan, TS = Tri-Scan
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Revision 1.1 PS-1593 Pg 11
KAC-06040 Image Sensor
KAC-06040-ABA Configuration (Monochrome)
Description
Symbol
Wavelength
(nm)
Nom.
Units
Sampling
Plan
Temperature
Tested At (°C)
QEmax
550
850
900
52
15
9.0
%
Design
27
Peak Quantum Efficiency Green
NIR1
NIR2
Notes
Test
Responsivity
83
Design
27
20
Responsivity
7.3
Design
27
21
KAC-06040-CBA Configuration (Bayer RGB)
Symbol
Wavelengt
h
(nm)
Nom.
Units
Sampling
Plan
Temperature
Tested At
(°C)
QEmax
470
540
620
850
900
42
47
44
16
9.8
%
Design
27
Responsivity
Blue
Green
Red
18
36
39
Design
27
20
Responsivity
Blue
Green
Red
1.6
3.1
3.4
Design
27
21
Description
Peak Quantum Efficiency
Gree
n
NIR1
NIR2
Notes
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Notes
Test
Measured per color, worst of all colors reported
Value is over the range of 10% to 90% of photodiode saturation, Green response used.
Uses 20LOG(PNe/ ne-T)
Photodiode dark current made negligible
Column Noise Correction active
Row Noise Correction active
Measured at ~70% illumination
Storage node dark current made negligible
GSE (Global Shutter Efficiency) = 1-1/PLS
Min vs Max integration time at 30 fps
WDR measures expanded exposure latitude from linear mode DR
Min/Max responsivity in a 30 fps image
Saturation Illumination referenced to a three line time integration.
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Typical Performance Curves
QUANTUM EFFICIENCY
Monochrome with Microlens
Figure 3: Monochrome QE (with Microlens)
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Color (Bayer RGB) with Microlens
Figure 4: Bayer QE (with Microlens)
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ANGULAR QUANTUM EFFICIENCY
For the curves marked “Horizontal”, the incident light angle is varied along the wider array dimension.
For the curves marked “Vertical”, the incident light angle is varied along the shorter array dimension.
Figure 5: Monochrome Relative Angular QE (with Microlens)
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Figure 6: Monochrome Relative Angular QE (with Microlens)
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DARK CURRENT VERSUS TEMPERATURE
Figure 7: Dark Current vs Temperature
Note: “Dbl” denotes an approximate doubling temperature for the dark current for the displayed temperature range.
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POWER VS FRAME RATE
The most effective method to set the frame rate is to use vertical blanking (Register 01F1h). Unnecessary chip
operations are suspended during vertical blanking conserving significant power consumption and also minimizing the
image storage time on the storage node when in Global Shutter Operation. Tri-scan can reach higher frame rates, but
consumes more power at all frame rates. It is recommended use Dual-Scan unless the frame rate required can only be
reached with Tri-Scan. The LVDS clock is ½ the PLL2 clock frequency.
Figure 8: Dual-Scan Power vs Frame Rate, 10 bit mode
Figure 9: Tri-Scan Power vs Frame Rate, 10 bit mode
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Power and Frame Rate vs ADC Bit depth
Increasing the ADC bit depth impacts the frame rate by changing the ADC conversion time. The following figure shows
the power and Frame rate range for several typical cases. For optimum image quality and power consumption the
PLL2 and vertical blanking have been optimized for each bit depth and target frame rate. Because of the different
parameters impacting the line time, Tri-Scan only has significant benefit at 10 bit operation. At 8 bit operation the
LVDS readout time dominates the line time; and at 12 and 14 bit the ADC time dominates the line time and the pixel
time is not significant. But at 10 bit operation Tri-Scan can almost halve the line time at the cost of additional power
consumption.
Figure 10: Dual-Scan ADC Bit Depth impact on Frame Rate and Power
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Figure 11: Tri-Scan vs Dual-Scan Power
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Defect Definitions
OPERATION CONDITIONS FOR DEFECT TESTING
Description
Condition
Operational Mode
10 bit ADC, 8 LVDS outputs, Global Shutter and Rolling Shutter modes, Dual-Scan, Black
Level Clamp on, Column/Row Noise Correction on, 1x Analog Gain, 1x Digital Gain
Notes
Pixels Per Line
2832
Lines Per Frame
2128
Line Time
6.875 μsec
Frame Time
8.25 msec
Photodiode Integration Time
33 msec
Storage Readout Time
7.85 msec
Temperature
40 °C and 30 °C
Light Source
Continuous red, green and blue LED illumination (green only for monochrome sensor)
Operation
Nominal operating voltages and timing, PLL1 = 320 MHz, PLL2 = 410 MHz
DEFECT DEFINITIONS FOR TESTING
Description
Definition
Dark Field Defective Pixel
29 °C
RS: Defect ≥ 20 dn
GS: Defect ≥ 180 dn
Limit
Bright Field Defective Pixel
Defect ≥ ±12% from local mean
Cluster Defect
A group of 2 to 10 contiguous defective pixels, but no more than 3
adjacent defects horizontally
11
Column/Row Major Defect
A group of more than 10 contiguous defective pixels along a single
column or row
0
Dark Field Faint Column/Row Defect
RS: 3 dn threshold
GS: 10 dn threshold
0
17
Bright Field Faint Column/Row Defect
RS: 12 dn threshold
GS: 18 dn threshold
0
18
40 °C
RS: Defect ≥ 30 dn
GS: Defect ≥ 240 dn
60
Test
Notes
4
3, 4
5
1, 4
2
Notes:
RS = Rolling Shutter, GS = Global Shutter
1. For the color devices, all bright defects are defined within a single color plane, each color plane is tested
2. Cluster defects are separated by no less than two good pixels in any direction.
3. Rolling Shutter Dark Field points are dominated by photodiode integration time, Global Shutter Dark Field defects are
dominated by the readout time.
4. The net sum of all bright and dark field pixel defects in rolling and global shutter are combined and then compared to the
test limit
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Test Definitions
TEST REGIONS OF INTEREST
Image Area ROI:
Pixel (0, 0) to Pixel (2847, 2143)
Active Area ROI:
Pixel (8, 8) to Pixel (2839, 2135)
Only the Active Area ROI pixels are used for performance and defect tests.
88
8
B G
B G
G
R
G
R
2832 (H) x 2128 (V)
4.7 µm pixel
8,8
88
8
8
88
0,0
B G
G
R
8
88
Figure 12: Regions of Interest
TESTS
1) Dark Field Local Non-Uniformity Floor (DSNU_flr)
This test is performed under dark field conditions. A 4 frame average image is collected. This image is partitioned into
180 subregions of interest, each of which is 190 by 178 pixels in size. For each sub-region the standard deviation of all
its pixels is calculated. The dark field local non-uniformity is the largest standard deviation found from all the sub
regions of interest. Units: e rms (electrons rms)
2) Bright Field Local Photoresponse Non-Uniformity (PRNU_1)
The sensor illuminated to 70% of saturation (~700 dn). In this condition a 4 frame average image is collected. From this
4 frame average image a 4 frame average dark image is subtracted. The Active Area Standard Deviation is the standard
deviation of the resultant image and the Active Area Signal is the average of the resultant image.
Active Area Standard Deviation
PRNU_1 100 *
Active Area Signal
Units: %rms
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3) Bright Field Global Non-Uniformity (PRNU_2)
This test is performed with the sensor uniformly illuminated to 70% of saturation (~700 dn), a 4 frame average image is
collected and a 4 frame averaged dark image is subtracted. The resultant image is partitioned into 180 subregions of
interest, each of which is 190 by 178 pixels in size. The average signal level of each sub regions of interest (sub-ROI) is
calculated.
The highest sub-ROI average (Maximum Signal) and the lowest sub-ROI average (Minimum Signal) are then used in the
following formula to calculate PRNU_2.
PRNU_2 100 *
Maximum Signal - Minimum Signal
Active Area Signal
Units: %pp
4) Dark Field Defect Test
This test is performed under dark field conditions. The sensor is partitioned into 390 subregions of interest, each of
which is 128 by 128 pixels in size. In each region of interest, the median value of all pixels is found. For each region of
interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the
defect threshold specified in the Defect Definition Table section.
5) Bright Field Defect Test
This test is performed with the imager illuminated to a level such that the output is at approximately 700 dn. The
average signal level of all active pixels is found. The bright and dark thresholds are set as:
Dark defect threshold = Active Area Signal * threshold
Bright defect threshold = Active Area Signal * threshold
The sensor is then partitioned into 390 subregions of interest, each of which is 128 by 128 pixels in size. In each region
of interest, the average value of all pixels is found. For each region of interest, a pixel is marked defective if it is
greater than or equal to the median value of that region of interest plus the bright threshold specified or if it is less
than or equal to the median value of that region of interest minus the dark threshold specified.
Example for bright field defective pixels:
Average value of all active pixels is found to be 700 dn
Lower defect threshold:
A specific 128 x 128 ROI is selected:
700 dn * 12 % = 84 dn
o
Median of this region of interest is found to be 690 dn.
o
Any pixel in this region of interest that is ≤ (690 - 84 dn) in intensity will be marked defective.
o
Any pixel in this region of interest that is ≥ (690 - 84 dn) in intensity will be marked defective
All remaining 299 sub regions of interest are analyzed for defective pixels in the same manner.
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6) Parasitic Light Sensitivity (PLS)
Parasitic Light Sensitivity is the ratio of the light sensitivity of the photodiode to the light sensitivity of the storage
node in Global Shutter. There is no equivalent distortion in Rolling Shutter. A low PLS value can provide distortion of
the image on the storage node by the scene during readout.
(unitless ratio)
GSE (Global Shutter Efficiency) is a related unit.
(
)
Detailed method: Photodiode Responsivity:
The sensor is set in global shutter serial mode (integration time not overlapping readout) and the FLO signal is
used to control a 550 nm normal incident (or large f# focused) illumination source so that the sensor is
illuminated only during photodiode integration time (not illuminated during readout time). The integration
time is not critical but should be large enough to create a measurable mean during this time. A 16 frameaverage illuminated photodiode image is recorded. A 16 frame-average dark frame using the same sensor
settings is captured and is subtracted from the illuminated image.
Detailed method: Storage Node Responsivity:
The sensor is set to a special characterization mode where the PD signal is discarded and does not impact the
storage node. A long total frame time (storage node exposure time) is used to increase the storage node
signal. A 16 frame-average dark frame is captured. The sensor is illuminated by the same 550nm incident light
source used for the photodiode responsivity. A 16 frame-average illuminated photodiode image is recorded;
the dark frame image is subtracted from this. The integration time is not critical but should be set such that a
significant response is detected, typically several orders of magnitude greater than the photodiode integration
time.
7) Black-Sun Anti-blooming
A typical CMOS image sensor has a light response profile that goes from 0 dn to saturation (1023 dn for KAC-06040 in
10 bit ADC mode) and, with enough light, back to 0 dn. The sensor reaching 0 dn at very bright illumination is often
called the “Black-sun” artifact and is undesirable. Black-sun artifact is typically the dominant form of anti-blooming
image distortion. For the KAC-06040 the Black-sun artifact threshold is measured at the onset of saturation distortion,
not at the point where the output goes to 0 dn. To first order the onset of black-sun artifact for the KAC-06040 is not
proportional to the integration time or readout time.
2
The sensor is placed in the dark at unity gain and illuminated with a 532 nm laser with the intensity of about 26 W/cm
at the center of the sensor. The laser is strong enough to make the center of the laser spot below 1020 dn without any
ND filters. ND filters are added to adjust the laser intensity until the signal in the region at the center of the spot
increases to >1020 dn.
2
This illumination intensity at this ND filter is recorded (W/cm ) as the Black-Sun Anti-blooming.
The ‘xIlumSat’ unit is calculated using and integration time of 100 µsec.
Exposing the sensor to very strong illumination for extended periods of time will permanently alter the sensor
performance in that localized region.
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8) Read Noise
This test is performed with no illumination and one line of integration time. The read noise is defined as one standard
deviation of the frequency histogram containing the values of all pixels after the excessively deviant pixels (± three
standard deviations) are removed.
9) Column Noise
After all rows are averaged together. Shading (low frequency change wrt column address) is removed. A frequency
histogram is constructed of the resulting column values. The column noise is the standard deviation of the frequency
histogram of the column values. This Metric includes both temporal and FPN.
10) Row Noise
All columns are averaged together. Shading (low frequency change wrt row address) is removed. A frequency
histogram is constructed of the resulting row values. The row noise is the standard deviation of the frequency
histogram of the row values. This Metric includes both temporal and FPN.
11) Maximum Photoresponse Non-Linearity
The photoresponse nonlinearity is defined as the deviation from the best fit of the sensor response using 70% of
saturation and zero signal as the reference points. The different signal levels are determined by varying the integration
time. The sensor saturation level is (1023-dark offset). The dark offset is subtracted from the image for the following
Mavg and Lavg.
The integration time is varied until the integration time required to reach the 70% saturation is determined.
Mavg = the active array mean at the 70% saturation integration time.
The integration is set to 1/14 (5% exposure point). Lavg = meant at the 5% exposure point
PRNL (@ 5% saturation) =( (Lavg/Mavg) * (14/1) -1) * 100
12) Maximum Gain Difference Between Outputs
The LVDS outputs contain no gain or offset error since these are purely digital segmentations. The predominant
output mismatch comes from the pixel array readout segmentation. The sensor contains two ADC banks and four
channels of analog line stores in its highest frame rate configuration, Tri-Scan. The sensor is factory calibrated to
th
match the gain differences between all four possible gain channels. The gain variations are manifest as an every 4 row
gain pattern. In tri-scan, and an even/odd row gain difference in Dual-Scan. The sensor is factory calibrated to match
the four possible row gains. This test is performed in Tri-Scan mode to test the worst case gain error including all
possible 4 row gains after the calibration has been applied. The sensor is illuminated at 70% of saturation. The entire
th
test frame ROI into 4 groups of every 4 row. The first row group(average) is used as a reference and the following
three row groups are compared to the first. The largest error is reported.
( (Second Row Average/First Row Average) -1 ) * 100
( (Third Row Average/Frist Row Average) -1 ) * 100
( (Fourth Row Average/First Row Average) -1 ) * 100
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13) Photodiode Dark Current
The photodiode dark current is measured in rolling shutter read out mode using 105 msec integration time and an
analog gain = 8. The value is converted to electrons/pix/sec using the formula:
Photodiode dark current = average signal (DN) * el-per-DN (gain=8) / .105 seconds
where ‘average signal (DN)’ is the average of all pixels in the sensor array, and ‘el-per-DN(gain=8)’ is measured on each
sensor using the photon transfer method.
14) Storage Node Dark Current
The storage node dark current is measured in global shutter read out mode using a special timing mode to prevent the
photodiode dark current from being transferred to the storage node. In global shutter mode, the integration time of
the storage node is the time it takes to read out a frame. The sensor analog gain is set to 2:
Storage node dark current = average signal (DN) * el-per-DN (gain=2) / .0138 seconds
where ‘average signal (DN)’ is the average of all pixels in the sensor array and ‘el-per-DN(gain=2)’ is measured on each
sensor using the photon transfer method.
15) Lag
Lag is measured as the number of electrons left in the photodiode after readout when the sensor is illuminated at 70%
of Photodiode Charge Capacity.
Analog gain is set to 8. With no illumination a 64 average dark image is recorded (Dark_ref). The ‘el-per-DN’ is
measured using the photon transfer method.
Illumination is adjusted blink every other frame such that the mean image output is 70% of the Photodiode Charge
Capacity for even frames, and with no illumination for odd frames. A 64 frame average of Odd Dark Frames is recorded
as Dark_Lag.
Lag = (Dark_Lag - Dark_Ref) * el-per-DN’ Units: electrons rms
16) Photodiode Charge Capacity
The sensor analog gain is reduced to 5 Sigma). All columns or rows are averaged together. The average of the local ROI of 128 columns or
rows about the column/row being tested is determined. Any columns/rows greater than the local average by more
than the threshold are identified.
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18) Bright Field Faint Column/Row Defect
A 4 frame average, 70% illumination image is acquired at one line time of integration. Major defective pixels are
removed (> 5 Sigma). All columns or rows are averaged together. The average of the local ROI of 128 columns or
rows about the column/row being tested is determined. Any columns/rows greater than the local average by more
than the threshold are identified.
19) Total Pixelized Noise
This test is performed with no illumination and one line of integration time. A single image is captured including both
Temporal and Fixed Pattern Noise (FPN). A spatial low pass filter is applied to remove shading and excessively deviant
pixels (± three standard deviations) are removed. The Total Pixelized Noise is defined as one standard deviation of the
frequency histogram.
20) Responsivity ke/lux-sec
This number is calculated by integrating the multiplication of the sensor QE by the human photopic response assuming
a 3200K light source with a QT100 IR filter. This is a sharp 650nm cutoff filter. If the IR filter is removed a higher
response value will result.
21) Responsivity V/lux-sec
Voltage levels are not output from the sensor. This value uses the pixel output before analog gain to match the ADC
input range. Including the ADC matching gain will result in a larger responsivity value.
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Operation
This section is a brief discussion of the most common features and functions assuming default conditions. See the
KAC-06040 User Guide for a full explanation of the sensor operation modes, options, and registers.
REGISTER ADDRESSES
The last bit of any register address is a Read/Write bit. Most references in this document refer to the Write address.
All SPI reads are to an even address, all SPI writes are to an odd address.
SENSOR STATES
Figure 13 shows the sensor states, see the KAC-06040 User Guide for detailed explanation of the States.
RESETN low or
reset Reg 4060h
RESET
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